imx: cortexa53: remove KSZ9477 static driver

The KSZ9477 driver was added to the cortexa53 kernel to support the
Gateworks Venice product family which has a board with this switch. Now
that the kmod-dsa-ksz9477 driver is available as a package remove the
static configuration ad add the package.

This resolves an issue caused by having the switch driver static and the
PHY driver as a module such that the PHY driver was not registered early
enough to be used causing some errata to not be worked around.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/22120
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 231553b280)

.github/workflows/build-on-comment.yml

@@ -0,0 +1,164 @@
+name: Build on Comment
+
+on:
+  issue_comment:
+    types: [created, edited]
+
+permissions:
+  pull-requests: write
+
+concurrency:
+  group: build-on-comment-${{ github.event.issue.number || github.event.pull_request.number }}
+  cancel-in-progress: true
+
+jobs:
+  check-and-build:
+    if: github.event.issue.pull_request != null
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Check if user is in reviewers team
+        id: check-reviewer
+        run: |
+          USERNAME="${{ github.event.comment.user.login }}"
+
+          STATUS_CODE=$(curl -s -H "Authorization: token ${{ secrets.LOOKUP_MEMBERS }}" \
+                -o response.json -w "%{http_code}" \
+                https://api.github.com/orgs/openwrt/teams/reviewers/memberships/$USERNAME)
+
+          if grep -q '"state": "active"' response.json && [ "$STATUS_CODE" -eq 200 ]; then
+            echo "authorized=true" >> $GITHUB_OUTPUT
+          else
+            echo "authorized=false" >> $GITHUB_OUTPUT
+          fi
+
+      - name: Parse build command
+        if: steps.check-reviewer.outputs.authorized == 'true'
+        id: parse-command
+        run: |
+          COMMENT="${{ github.event.comment.body }}"
+          if echo "$COMMENT" | grep -q "build [a-zA-Z0-9_-]\+/[a-zA-Z0-9_-]\+/[a-zA-Z0-9_-]\+"; then
+            BUILD_PATH=$(echo "$COMMENT" | grep -o "build [a-zA-Z0-9_-]\+/[a-zA-Z0-9_-]\+/[a-zA-Z0-9_-]\+" | sed 's/build //')
+            TARGET=$(echo "$BUILD_PATH" | cut -d'/' -f1)
+            SUBTARGET=$(echo "$BUILD_PATH" | cut -d'/' -f2)
+            PROFILE=$(echo "$BUILD_PATH" | cut -d'/' -f3)
+            echo "build_requested=true" >> $GITHUB_OUTPUT
+            echo "target=$TARGET" >> $GITHUB_OUTPUT
+            echo "subtarget=$SUBTARGET" >> $GITHUB_OUTPUT
+            echo "profile=$PROFILE" >> $GITHUB_OUTPUT
+            echo "build_path=$BUILD_PATH" >> $GITHUB_OUTPUT
+          else
+            echo "build_requested=false" >> $GITHUB_OUTPUT
+          fi
+
+      - name: Find existing build comment
+        if: steps.parse-command.outputs.build_requested == 'true'
+        id: find-comment
+        uses: peter-evans/find-comment@v2
+        with:
+          issue-number: ${{ github.event.pull_request.number || github.event.issue.number }}
+          comment-author: "github-actions[bot]"
+
+      - name: Create early build comment
+        if: steps.parse-command.outputs.build_requested == 'true'
+        id: start-comment
+        uses: peter-evans/create-or-update-comment@v3
+        with:
+          issue-number: ${{ github.event.pull_request.number || github.event.issue.number }}
+          comment-id: ${{ steps.find-comment.outputs.comment-id }}
+          body: |
+            🚧 **Build in progress for** `${{ steps.parse-command.outputs.build_path }}`...
+
+            You can follow progress [here](https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }})
+
+            *Triggered by: @${{ github.event.comment.user.login }}*
+          edit-mode: replace
+
+      - name: Checkout repository
+        if: steps.parse-command.outputs.build_requested == 'true'
+        uses: actions/checkout@v4
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+          fetch-depth: 0
+          ref: refs/pull/${{ github.event.issue.number }}/merge
+
+      - name: Setup build environment
+        if: steps.parse-command.outputs.build_requested == 'true'
+        continue-on-error: true
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y build-essential libncurses5-dev gawk git subversion libssl-dev gettext zlib1g-dev swig unzip time rsync
+
+      - name: Build target
+        if: steps.parse-command.outputs.build_requested == 'true'
+        id: build
+        run: |
+          make defconfig
+          echo "CONFIG_DEVEL=y" > .config
+          echo "CONFIG_BPF_TOOLCHAIN_HOST=y" >> .config
+          echo "CONFIG_TARGET_${{ steps.parse-command.outputs.target }}=y" >> .config
+          echo "CONFIG_TARGET_${{ steps.parse-command.outputs.target }}_${{ steps.parse-command.outputs.subtarget }}=y" >> .config
+          echo "CONFIG_TARGET_${{ steps.parse-command.outputs.target }}_${{ steps.parse-command.outputs.subtarget }}_DEVICE_${{ steps.parse-command.outputs.profile }}=y" >> .config
+
+          make defconfig
+          make -j$(nproc) BUILD_LOG=1
+
+          echo "build_success=true" >> $GITHUB_OUTPUT
+
+      - name: Upload log
+        uses: actions/upload-artifact@v4
+        if: steps.check-reviewer.outputs.authorized == 'true' && (success() || failure())
+        with:
+          name: build-log-${{ steps.parse-command.outputs.target }}-${{ steps.parse-command.outputs.subtarget }}-${{ steps.parse-command.outputs.profile }}
+          path: logs/
+
+      - name: Create artifact archive
+        if: steps.build.outputs.build_success == 'true'
+        run: |
+          cd bin/
+          tar -czf ../build-artifacts.tar.gz *
+          cd ..
+
+      - name: Upload build artifacts
+        if: steps.build.outputs.build_success == 'true'
+        uses: actions/upload-artifact@v4
+        with:
+          name: build-${{ steps.parse-command.outputs.target }}-${{ steps.parse-command.outputs.subtarget }}-${{ steps.parse-command.outputs.profile }}
+          path: build-artifacts.tar.gz
+
+      - name: Update comment with build results
+        if: steps.build.outputs.build_success == 'true'
+        uses: peter-evans/create-or-update-comment@v3
+        with:
+          comment-id: ${{ steps.start-comment.outputs.comment-id }}
+          issue-number: ${{ github.event.pull_request.number || github.event.issue.number }}
+          body: |
+            ## Build Results for `${{ steps.parse-command.outputs.build_path }}`
+
+            ✅ **Build completed successfully!**
+
+            **Target:** `${{ steps.parse-command.outputs.target }}`
+            **Subtarget:** `${{ steps.parse-command.outputs.subtarget }}`
+            **Profile:** `${{ steps.parse-command.outputs.profile }}`
+
+            📦 **Artifacts:** [Download build-${{ steps.parse-command.outputs.target }}-${{ steps.parse-command.outputs.subtarget }}-${{ steps.parse-command.outputs.profile }}](https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }})
+
+            *Build triggered by: @${{ github.event.comment.user.login }}*
+            *Last updated: ${{ github.event.comment.created_at }}*
+          edit-mode: replace
+
+      - name: Update comment on build failure
+        if: steps.parse-command.outputs.build_requested == 'true' && steps.build.outputs.build_success == 'false'
+        uses: peter-evans/create-or-update-comment@v3
+        with:
+          comment-id: ${{ steps.start-comment.outputs.comment-id }}
+          issue-number: ${{ github.event.pull_request.number || github.event.issue.number }}
+          body: |
+            ## Build Results for `${{ steps.parse-command.outputs.build_path }}`
+
+            ❌ **Build failed!**
+
+            Please check the [action logs](https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id }}) for more details.
+
+            *Build triggered by: @${{ github.event.comment.user.login }}*
+          edit-mode: replace

.github/workflows/build-pr-profile.yml

@@ -1,12 +0,0 @@
-name: Build PR Profile
-
-on:
-  pull_request:
-    types: [opened, edited, synchronize]
-
-permissions:
-  pull-requests: write
-
-jobs:
-  build-pr-profile:
-    uses: openwrt/actions-shared-workflows/.github/workflows/build-pr-profile.yml@main

config/Config-kernel.in

@@ -413,102 +413,6 @@ config KERNEL_PREEMPT_TRACER
 	  enabled. This option and the irqs-off timing option can be
 	  used together or separately.)
 
-config KERNEL_HWLAT_TRACER
-	bool "Tracer to detect hardware latencies (like SMIs)"
-	depends on KERNEL_FTRACE
-	help
-	  This tracer, when enabled will create one or more kernel threads,
-	  depending on what the cpumask file is set to, which each thread
-	  spinning in a loop looking for interruptions caused by
-	  something other than the kernel. For example, if a
-	  System Management Interrupt (SMI) takes a noticeable amount of
-	  time, this tracer will detect it. This is useful for testing
-	  if a system is reliable for Real Time tasks.
-
-	  Some files are created in the tracing directory when this
-	  is enabled:
-
-	    hwlat_detector/width   - time in usecs for how long to spin for
-	    hwlat_detector/window  - time in usecs between the start of each
-				     iteration
-
-	  A kernel thread is created that will spin with interrupts disabled
-	  for "width" microseconds in every "window" cycle. It will not spin
-	  for "window - width" microseconds, where the system can
-	  continue to operate.
-
-	  The output will appear in the trace and trace_pipe files.
-
-	  When the tracer is not running, it has no affect on the system,
-	  but when it is running, it can cause the system to be
-	  periodically non responsive. Do not run this tracer on a
-	  production system.
-
-	  To enable this tracer, echo in "hwlat" into the current_tracer
-	  file. Every time a latency is greater than tracing_thresh, it will
-	  be recorded into the ring buffer.
-
-config KERNEL_OSNOISE_TRACER
-	bool "OS Noise tracer"
-	depends on KERNEL_FTRACE
-	help
-	  In the context of high-performance computing (HPC), the Operating
-	  System Noise (osnoise) refers to the interference experienced by an
-	  application due to activities inside the operating system. In the
-	  context of Linux, NMIs, IRQs, SoftIRQs, and any other system thread
-	  can cause noise to the system. Moreover, hardware-related jobs can
-	  also cause noise, for example, via SMIs.
-
-	  The osnoise tracer leverages the hwlat_detector by running a similar
-	  loop with preemption, SoftIRQs and IRQs enabled, thus allowing all
-	  the sources of osnoise during its execution. The osnoise tracer takes
-	  note of the entry and exit point of any source of interferences,
-	  increasing a per-cpu interference counter. It saves an interference
-	  counter for each source of interference. The interference counter for
-	  NMI, IRQs, SoftIRQs, and threads is increased anytime the tool
-	  observes these interferences' entry events. When a noise happens
-	  without any interference from the operating system level, the
-	  hardware noise counter increases, pointing to a hardware-related
-	  noise. In this way, osnoise can account for any source of
-	  interference. At the end of the period, the osnoise tracer prints
-	  the sum of all noise, the max single noise, the percentage of CPU
-	  available for the thread, and the counters for the noise sources.
-
-	  In addition to the tracer, a set of tracepoints were added to
-	  facilitate the identification of the osnoise source.
-
-	  The output will appear in the trace and trace_pipe files.
-
-	  To enable this tracer, echo in "osnoise" into the current_tracer
-	  file.
-
-config KERNEL_TIMERLAT_TRACER
-	bool "Timerlat tracer"
-	depends on KERNEL_FTRACE
-	help
-	  The timerlat tracer aims to help the preemptive kernel developers
-	  to find sources of wakeup latencies of real-time threads.
-
-	  The tracer creates a per-cpu kernel thread with real-time priority.
-	  The tracer thread sets a periodic timer to wakeup itself, and goes
-	  to sleep waiting for the timer to fire. At the wakeup, the thread
-	  then computes a wakeup latency value as the difference between
-	  the current time and the absolute time that the timer was set
-	  to expire.
-
-	  The tracer prints two lines at every activation. The first is the
-	  timer latency observed at the hardirq context before the
-	  activation of the thread. The second is the timer latency observed
-	  by the thread, which is the same level that cyclictest reports. The
-	  ACTIVATION ID field serves to relate the irq execution to its
-	  respective thread execution.
-
-	  The tracer is build on top of osnoise tracer, and the osnoise:
-	  events can be used to trace the source of interference from NMI,
-	  IRQs and other threads. It also enables the capture of the
-	  stacktrace at the IRQ context, which helps to identify the code
-	  path that can cause thread delay.
-
 config KERNEL_HIST_TRIGGERS
 	bool "Histogram triggers"
 	depends on KERNEL_FTRACE
@@ -1589,72 +1493,3 @@ config KERNEL_WERROR
 	  and unusual warnings, or you have some architecture with problems,
 	  you may need to disable this config option in order to
 	  successfully build the kernel.
-
-choice
-	prompt "Preemption Model"
-	default KERNEL_PREEMPT_NONE
-
-config KERNEL_PREEMPT_NONE
-	bool "No Forced Preemption (Server)"
-	help
-	  This is the traditional Linux preemption model, geared towards
-	  throughput. It will still provide good latencies most of the
-	  time, but there are no guarantees and occasional longer delays
-	  are possible.
-
-	  Select this option if you are building a kernel for a server or
-	  scientific/computation system, or if you want to maximize the
-	  raw processing power of the kernel, irrespective of scheduling
-	  latencies.
-
-config KERNEL_PREEMPT_VOLUNTARY
-	bool "Voluntary Kernel Preemption (Desktop)"
-	help
-	  This option reduces the latency of the kernel by adding more
-	  "explicit preemption points" to the kernel code. These new
-	  preemption points have been selected to reduce the maximum
-	  latency of rescheduling, providing faster application reactions,
-	  at the cost of slightly lower throughput.
-
-	  This allows reaction to interactive events by allowing a
-	  low priority process to voluntarily preempt itself even if it
-	  is in kernel mode executing a system call. This allows
-	  applications to run more 'smoothly' even when the system is
-	  under load.
-
-	  Select this if you are building a kernel for a desktop system.
-
-config KERNEL_PREEMPT
-	bool "Preemptible Kernel (Low-Latency Desktop)"
-	help
-	  This option reduces the latency of the kernel by making
-	  all kernel code (that is not executing in a critical section)
-	  preemptible.  This allows reaction to interactive events by
-	  permitting a low priority process to be preempted involuntarily
-	  even if it is in kernel mode executing a system call and would
-	  otherwise not be about to reach a natural preemption point.
-	  This allows applications to run more 'smoothly' even when the
-	  system is under load, at the cost of slightly lower throughput
-	  and a slight runtime overhead to kernel code.
-
-	  Select this if you are building a kernel for a desktop or
-	  embedded system with latency requirements in the milliseconds
-	  range.
-
-config KERNEL_PREEMPT_RT
-	bool "Fully Preemptible Kernel (Real-Time)"
-	depends on (x86_64 || aarch64 || riscv64)
-	help
-	  This option turns the kernel into a real-time kernel by replacing
-	  various locking primitives (spinlocks, rwlocks, etc.) with
-	  preemptible priority-inheritance aware variants, enforcing
-	  interrupt threading and introducing mechanisms to break up long
-	  non-preemptible sections. This makes the kernel, except for very
-	  low level and critical code paths (entry code, scheduler, low
-	  level interrupt handling) fully preemptible and brings most
-	  execution contexts under scheduler control.
-
-	  Select this if you are building a kernel for systems which
-	  require real-time guarantees.
-
-endchoice

feeds.conf.default

@@ -1,8 +1,5 @@
-src-git packages https://git.openwrt.org/feed/packages.git
-src-git luci https://git.openwrt.org/project/luci.git
-src-git routing https://git.openwrt.org/feed/routing.git
-src-git telephony https://git.openwrt.org/feed/telephony.git
-src-git video https://github.com/openwrt/video.git
-#src-git targets https://github.com/openwrt/targets.git
-#src-git oldpackages http://git.openwrt.org/packages.git
-#src-link custom /usr/src/openwrt/custom-feed
+src-git packages https://git.openwrt.org/feed/packages.git;openwrt-25.12
+src-git luci https://git.openwrt.org/project/luci.git;openwrt-25.12
+src-git routing https://git.openwrt.org/feed/routing.git;openwrt-25.12
+src-git telephony https://git.openwrt.org/feed/telephony.git;openwrt-25.12
+src-git video https://github.com/openwrt/video.git;openwrt-25.12

include/download.mk

@@ -34,9 +34,11 @@ $(strip \
       $(if $(filter @OPENWRT @APACHE/% @DEBIAN/% @GITHUB/% @GNOME/% @GNU/% @KERNEL/% @SF/% @SAVANNAH/% ftp://% http://% https://% file://%,$(1)),default, \
         $(if $(filter git://%,$(1)),$(call dl_method_git,$(1),$(2)), \
           $(if $(filter svn://%,$(1)),svn, \
-            $(if $(filter hg://%,$(1)),hg, \
-              $(if $(filter sftp://%,$(1)),bzr, \
-                unknown \
+            $(if $(filter cvs://%,$(1)),cvs, \
+              $(if $(filter hg://%,$(1)),hg, \
+                $(if $(filter sftp://%,$(1)),bzr, \
+                  unknown \
+                ) \
               ) \
             ) \
           ) \
@@ -47,7 +49,7 @@ $(strip \
 )
 endef
 
-# code for creating tarballs from svn/git/bzr/hg/darcs checkouts - useful for mirror support
+# code for creating tarballs from cvs/svn/git/bzr/hg/darcs checkouts - useful for mirror support
 dl_pack/bz2=bzip2 -c > $(1)
 dl_pack/gz=gzip -nc > $(1)
 dl_pack/xz=xz -zc -7e > $(1)
@@ -169,6 +171,21 @@ $(if $(filter check,$(1)), \
 )
 endef
 
+define DownloadMethod/cvs
+	$(call wrap_mirror,$(1),$(2), \
+		echo "Checking out files from the cvs repository..."; \
+		mkdir -p $(TMP_DIR)/dl && \
+		cd $(TMP_DIR)/dl && \
+		rm -rf $(SUBDIR) && \
+		[ \! -d $(SUBDIR) ] && \
+		cvs -d $(URL) export $(SOURCE_VERSION) $(SUBDIR) && \
+		echo "Packing checkout..." && \
+		$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
+		mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
+		rm -rf $(SUBDIR); \
+	)
+endef
+
 define DownloadMethod/svn
 	$(call wrap_mirror,$(1),$(2), \
 		echo "Checking out files from the svn repository..."; \
@@ -288,6 +305,7 @@ define DownloadMethod/darcs
 	)
 endef
 
+Validate/cvs=SOURCE_VERSION SUBDIR
 Validate/svn=SOURCE_VERSION SUBDIR
 Validate/git=SOURCE_VERSION SUBDIR
 Validate/bzr=SOURCE_VERSION SUBDIR

include/kernel.mk

@@ -212,8 +212,9 @@ define KernelPackage
     TITLE:=$(TITLE)
     SECTION:=kernel
     CATEGORY:=Kernel modules
-    EXTRA_DEPENDS:=kernel (=$(subst -rc,_rc,$(LINUX_VERSION))~$(LINUX_VERMAGIC)-r$(LINUX_RELEASE))
-    VERSION:=$(subst -rc,_rc,$(LINUX_VERSION))$(if $(PKG_VERSION),.$(PKG_VERSION))-r$(if $(PKG_RELEASE),$(PKG_RELEASE),$(LINUX_RELEASE))
+    DESCRIPTION:=$(DESCRIPTION)
+    EXTRA_DEPENDS:=kernel (=$(LINUX_VERSION)~$(LINUX_VERMAGIC)-r$(LINUX_RELEASE))
+    VERSION:=$(LINUX_VERSION)$(if $(PKG_VERSION),.$(PKG_VERSION))-r$(if $(PKG_RELEASE),$(PKG_RELEASE),$(LINUX_RELEASE))
     PKGFLAGS:=$(PKGFLAGS)
     $(call KernelPackage/$(1))
     $(call KernelPackage/$(1)/$(BOARD))

include/netfilter.mk

@@ -358,6 +358,7 @@ $(eval $(if $(NF_KMOD),$(call nf_add,NFT_CONNLIMIT,CONFIG_NFT_CONNLIMIT, $(P_XT)
 IPT_BUILTIN += $(NF_IPT-y) $(NF_IPT-m)
 IPT_BUILTIN += $(IPT_CORE-y) $(IPT_CORE-m)
 IPT_BUILTIN += $(NF_CONNTRACK-y)
+IPT_BUILTIN += $(NF_CONNTRACK6-y)
 IPT_BUILTIN += $(IPT_CONNTRACK-y)
 IPT_BUILTIN += $(IPT_CONNTRACK_EXTRA-y)
 IPT_BUILTIN += $(IPT_EXTRA-y)

include/package-pack.mk

@@ -435,7 +435,7 @@ Installed-Size: 0
 $(_endef)
 
     $$(PACK_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)
-    $$(PACK_$(1)) : $(call shexport,Package/$(1)/description)
+    $$(PACK_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
     $$(PACK_$(1)) : export PATH=$$(TARGET_PATH_PKG)
     $$(PACK_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
     $$(PACK_$(1)) : export SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
@@ -450,7 +450,7 @@ endif
 	$(call Package/$(1)/install,$$(IDIR_$(1)))
 	$(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
 	$(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)
-	-find $$(IDIR_$(1)) -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
+	-find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
 	@( \
 		find $$(IDIR_$(1)) -name lib\*.so\* -or -name \*.ko | awk -F/ '{ print $$$$NF }'; \
 		for file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \
@@ -493,7 +493,7 @@ ifeq ($(CONFIG_USE_APK),)
 	(cd $$(IDIR_$(1))/CONTROL; \
 		( \
 			echo "$$$$CONTROL"; \
-			printf "Description: "; echo "$$$$$(call shvar,Package/$(1)/description)" | sed -e 's,^[[:space:]]*, ,g'; \
+			printf "Description: "; echo "$$$$DESCRIPTION" | sed -e 's,^[[:space:]]*, ,g'; \
 		) > control; \
 		chmod 644 control; \
 		( \

include/package.mk

@@ -339,6 +339,10 @@ define BuildPackage
   # default, so wget-ssl can explicitly provide @wget-any as well.
   $(eval PROVIDES:=$(strip @$(1)-any $(PROVIDES)))
 
+ifdef DESCRIPTION
+$$(error DESCRIPTION:= is obsolete, use Package/PKG_NAME/description)
+endif
+
 ifndef Package/$(1)/description
 define Package/$(1)/description
 	$(TITLE)
@@ -391,7 +395,7 @@ prepare-package-install:
 $(PACKAGE_DIR):
 	mkdir -p $@
 
-compile: prepare-package-install
+compile:
 .install: .compile
 install: compile
 

include/rootfs.mk

@@ -113,7 +113,7 @@ define prepare_rootfs
 		done || true \
 	)
 
-	@-find $(1) -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
+	@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
 	rm -rf \
 		$(1)/boot \
 		$(1)/tmp/* \

include/target.mk

@@ -359,7 +359,7 @@ endif
 
 define BuildTargets/DumpCurrent
   .PHONY: dumpinfo
-  dumpinfo: $(call shexport,Target/Description)
+  dumpinfo : export DESCRIPTION=$$(Target/Description)
   dumpinfo:
 	@echo 'Target: $(TARGETID)'; \
 	 echo 'Target-Board: $(BOARD)'; \
@@ -376,7 +376,7 @@ define BuildTargets/DumpCurrent
 	 echo 'Linux-Kernel-Arch: $(LINUX_KARCH)'; \
 	$(if $(SUBTARGET),,$(if $(DEFAULT_SUBTARGET), echo 'Default-Subtarget: $(DEFAULT_SUBTARGET)'; )) \
 	 echo 'Target-Description:'; \
-	 echo "$$$$$(call shvar,Target/Description);"; \
+	 echo "$$$$DESCRIPTION"; \
 	 echo '@@'; \
 	 $(if $(DEFAULT_PROFILE),echo 'Target-Default-Profile: $(DEFAULT_PROFILE)';) \
 	 echo 'Default-Packages: $(DEFAULT_PACKAGES)'; \

include/u-boot.mk

@@ -104,7 +104,7 @@ define Build/U-Boot/Target
       endif
     endif
     $(if $(DEFAULT),DEFAULT:=$(DEFAULT))
-    URL:=https://docs.u-boot.org/en/latest/
+    URL:=http://www.denx.de/wiki/U-Boot
   endef
 
   define Package/u-boot-$(1)/install

include/version.mk

@@ -27,13 +27,13 @@ PKG_CONFIG_DEPENDS += \
 sanitize = $(call tolower,$(subst _,-,$(subst $(space),-,$(1))))
 
 VERSION_NUMBER:=$(call qstrip,$(CONFIG_VERSION_NUMBER))
-VERSION_NUMBER:=$(if $(VERSION_NUMBER),$(VERSION_NUMBER),SNAPSHOT)
+VERSION_NUMBER:=$(if $(VERSION_NUMBER),$(VERSION_NUMBER),25.12-SNAPSHOT)
 
 VERSION_CODE:=$(call qstrip,$(CONFIG_VERSION_CODE))
 VERSION_CODE:=$(if $(VERSION_CODE),$(VERSION_CODE),$(REVISION))
 
 VERSION_REPO:=$(call qstrip,$(CONFIG_VERSION_REPO))
-VERSION_REPO:=$(if $(VERSION_REPO),$(VERSION_REPO),https://downloads.openwrt.org/snapshots)
+VERSION_REPO:=$(if $(VERSION_REPO),$(VERSION_REPO),https://downloads.openwrt.org/releases/25.12-SNAPSHOT)
 
 VERSION_DIST:=$(call qstrip,$(CONFIG_VERSION_DIST))
 VERSION_DIST:=$(if $(VERSION_DIST),$(VERSION_DIST),OpenWrt)

package/Makefile

@@ -103,9 +103,9 @@ ifneq ($(CONFIG_USE_APK),)
 		--repositories-file /dev/null --repository file://$(PACKAGE_DIR_ALL)/packages.adb \
 		$(if $(CONFIG_SIGNED_PACKAGES),,--allow-untrusted) \
 		$$(cat $(TMP_DIR)/apk_install_list) \
-			"base-files=$(shell cat $(STAGING_DIR)/base-files.version)" \
-			"libc=$(shell cat $(STAGING_DIR)/libc.version)" \
-			"kernel=$(subst -rc,_rc,$(shell cat $(STAGING_DIR)/kernel.version))"
+			"base-files=$(shell cat $(TMP_DIR)/base-files.version)" \
+			"libc=$(shell cat $(TMP_DIR)/libc.version)" \
+			"kernel=$(shell cat $(TMP_DIR)/kernel.version)"
 
 	rm -rf $(TARGET_DIR)/run
 else

package/base-files/Makefile

@@ -45,7 +45,7 @@ define Package/base-files
 	+SELINUX:procd-selinux +!SELINUX:procd +USE_SECCOMP:procd-seccomp \
 	+SELINUX:busybox-selinux +!SELINUX:busybox
   TITLE:=Base filesystem for OpenWrt
-  URL:=https://openwrt.org/
+  URL:=http://openwrt.org/
   VERSION:=$(PKG_RELEASE)~$(lastword $(subst -, ,$(REVISION)))
 endef
 
@@ -256,7 +256,7 @@ ifneq ($(CONFIG_USE_APK),)
 
 	rm -f $(1)/etc/uci-defaults/13_fix-group-user
 	rm -f $(1)/sbin/pkg_check
-	echo $(PKG_RELEASE)~$(lastword $(subst -, ,$(REVISION))) >$(STAGING_DIR)/base-files.version
+	echo $(PKG_RELEASE)~$(lastword $(subst -, ,$(REVISION))) >$(TMP_DIR)/base-files.version
 else
 	$(if $(CONFIG_CLEAN_IPKG),, \
 		mkdir -p $(1)/etc/opkg; \

package/base-files/files/etc/group

@@ -5,6 +5,7 @@ mail:x:8:
 dialout:x:20:
 audio:x:29:
 www-data:x:33:
+ftp:x:55:
 users:x:100:
 network:x:101:
 nogroup:x:65534:

package/base-files/files/etc/passwd

@@ -1,4 +1,5 @@
 root:x:0:0:root:/root:/bin/ash
 daemon:*:1:1:daemon:/var:/bin/false
+ftp:*:55:55:ftp:/home/ftp:/bin/false
 network:*:101:101:network:/var:/bin/false
 nobody:*:65534:65534:nobody:/var:/bin/false

package/base-files/files/etc/shadow

@@ -1,4 +1,5 @@
 root:::0:99999:7:::
 daemon:*:0:0:99999:7:::
+ftp:*:0:0:99999:7:::
 network:*:0:0:99999:7:::
 nobody:*:0:0:99999:7:::

package/base-files/image-config.in

@@ -198,7 +198,7 @@ if VERSIONOPT
 	config VERSION_REPO
 		string
 		prompt "Release repository"
-		default "https://downloads.openwrt.org/snapshots"
+		default "https://downloads.openwrt.org/releases/25.12-SNAPSHOT"
 		help
 			This is the repository address embedded in the image, it defaults
 			to the trunk snapshot repo; the url may contain the following placeholders:

package/boot/arm-trusted-firmware-mediatek/Makefile

@@ -211,8 +211,8 @@ define Trusted-Firmware-A/mt7981-emmc-ddr3
   DDR_TYPE:=ddr3
 endef
 
-define Trusted-Firmware-A/mt7981-emmc-ddr3-1866
-  NAME:=MediaTek MT7981 (eMMC, DDR3 1866 MT/s)
+define Trusted-Firmware-A/mt7981-emmc-ddr3-1866mhz
+  NAME:=MediaTek MT7981 (eMMC, DDR3 1866 MHz)
   BOOT_DEVICE:=emmc
   BUILD_SUBTARGET:=filogic
   PLAT:=mt7981
@@ -244,8 +244,8 @@ define Trusted-Firmware-A/mt7981-spim-nand-ddr3
   DDR_TYPE:=ddr3
 endef
 
-define Trusted-Firmware-A/mt7981-spim-nand-ddr3-1866
-  NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR3 1866 MT/s)
+define Trusted-Firmware-A/mt7981-spim-nand-ddr3-1866mhz
+  NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR3 1866 MHz)
   BOOT_DEVICE:=spim-nand
   BUILD_SUBTARGET:=filogic
   PLAT:=mt7981
@@ -645,34 +645,6 @@ define Trusted-Firmware-A/mt7988-spim-nand-ubi-ddr4
   USE_UBI:=1
 endef
 
-define Trusted-Firmware-A/mt7988-emmc-comb-4bg
-  NAME:=MediaTek MT7988 (eMMC, DDR4 8GB)
-  BOOT_DEVICE:=emmc
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7988
-  DRAM_USE_COMB:=1
-  DDR4_4BG_MODE:=1
-endef
-
-define Trusted-Firmware-A/mt7988-sdmmc-comb-4bg
-  NAME:=MediaTek MT7988 (SD card, DDR4 8GB)
-  BOOT_DEVICE:=sdmmc
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7988
-  DRAM_USE_COMB:=1
-  DDR4_4BG_MODE:=1
-endef
-
-define Trusted-Firmware-A/mt7988-spim-nand-ubi-comb-4bg
-  NAME:=MediaTek MT7988 (SPI-NAND via SPIM, UBI, DDR4 8GB)
-  BOOT_DEVICE:=spim-nand
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7988
-  DRAM_USE_COMB:=1
-  DDR4_4BG_MODE:=1
-  USE_UBI:=1
-endef
-
 TFA_TARGETS:= \
 	mt7622-nor-1ddr \
 	mt7622-nor-2ddr \
@@ -688,13 +660,13 @@ TFA_TARGETS:= \
 	mt7622-sdmmc-2ddr \
 	mt7981-ram-ddr3 \
 	mt7981-emmc-ddr3 \
-	mt7981-emmc-ddr3-1866 \
+	mt7981-emmc-ddr3-1866mhz \
 	mt7981-nor-ddr3 \
 	mt7981-nor-ddr4 \
 	mt7981-sdmmc-ddr3 \
 	mt7981-snand-ddr3 \
 	mt7981-spim-nand-ddr3 \
-	mt7981-spim-nand-ddr3-1866 \
+	mt7981-spim-nand-ddr3-1866mhz \
 	mt7981-spim-nand-ubi-ddr4 \
 	mt7981-ram-ddr4 \
 	mt7981-emmc-ddr4 \
@@ -744,10 +716,7 @@ TFA_TARGETS:= \
 	mt7988-snand-ubi-comb \
 	mt7988-spim-nand-comb \
 	mt7988-spim-nand-ubi-comb \
-	mt7988-spim-nand-ubi-ddr4 \
-	mt7988-emmc-comb-4bg \
-	mt7988-sdmmc-comb-4bg \
-	mt7988-spim-nand-ubi-comb-4bg
+	mt7988-spim-nand-ubi-ddr4
 
 TFA_MAKE_FLAGS += \
 	BOOT_DEVICE=$(BOOT_DEVICE) \

package/boot/arm-trusted-firmware-rockchip/Makefile

@@ -7,10 +7,10 @@
 
 include $(TOPDIR)/rules.mk
 
-PKG_VERSION:=2.14.0
+PKG_VERSION:=2.13
 PKG_RELEASE:=1
 
-PKG_HASH:=b2a3bc360307c929714ffd8e7f1441c4888cd5d80531276e809c2de54db5dc16
+PKG_HASH:=afb5c408392fcec840bd30de9b02a236b0108142024f9853b542b596b0d894e3
 
 PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de>
 

package/boot/arm-trusted-firmware-sunxi/Makefile

@@ -7,10 +7,10 @@
 
 include $(TOPDIR)/rules.mk
 
-PKG_VERSION:=2.14
+PKG_VERSION:=2.10
 PKG_RELEASE:=1
 
-PKG_HASH:=14fb6101f2ef424ec84c0296c3cbdeb7f79b22f5fbb46529bea0e362d0fab0d5
+PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201
 
 PKG_LICENSE:=BSD-3-Clause
 PKG_LICENSE_FILES:=license.md
@@ -46,6 +46,9 @@ TFA_TARGETS:= \
 	sunxi-h6 \
 	sunxi-h616
 
+TFA_MAKE_FLAGS+= \
+	$(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments")
+
 define Package/trusted-firmware-a/install
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
 	$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31_$(BUILD_VARIANT).bin

package/boot/grub2/Makefile

@@ -34,7 +34,7 @@ define Package/grub2/Default
   CATEGORY:=Boot Loaders
   SECTION:=boot
   TITLE:=GRand Unified Bootloader ($(2))
-  URL:=https://www.gnu.org/software/grub/
+  URL:=http://www.gnu.org/software/grub/
   DEPENDS:=@TARGET_$(1)
   VARIANT:=$(2)
 endef
@@ -49,7 +49,7 @@ define Package/grub2-editenv
   SECTION:=utils
   SUBMENU:=Boot Loaders
   TITLE:=Grub2 Environment editor
-  URL:=https://www.gnu.org/software/grub/
+  URL:=http://www.gnu.org/software/grub/
   DEPENDS:=@TARGET_x86
   VARIANT:=none
 endef
@@ -63,7 +63,7 @@ define Package/grub2-bios-setup
   SECTION:=utils
   SUBMENU:=Boot Loaders
   TITLE:=Grub2 BIOS boot setup tool
-  URL:=https://www.gnu.org/software/grub/
+  URL:=http://www.gnu.org/software/grub/
   DEPENDS:=@TARGET_x86
   VARIANT:=none
 endef

package/boot/kexec-tools/Config.in

@@ -11,9 +11,4 @@ config KEXEC_LZMA
 	prompt "lzma support"
 	default n
 
-config KEXEC_ZSTD
-	bool
-	prompt "zstd support"
-	default n
-	
 endmenu

package/boot/kexec-tools/Makefile

@@ -8,18 +8,18 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=kexec-tools
-PKG_VERSION:=2.0.32
-PKG_RELEASE:=3
+PKG_VERSION:=2.0.28
+PKG_RELEASE:=2
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec
-PKG_HASH:=8f81422a5fd2362cf6cb001b511e535565ed0f32c2f4451fb5eb68fed6710a5d
+PKG_HASH:=d2f0ef872f39e2fe4b1b01feb62b0001383207239b9f8041f98a95564161d053
 
 PKG_LICENSE:=GPL-2.0-only
 PKG_LICENSE_FILES:=COPYING
 PKG_CPE_ID:=cpe:/a:kernel:kexec-tools
 
-PKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA CONFIG_KEXEC_ZSTD
+PKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA
 
 PKG_BUILD_FLAGS:=gc-sections
 
@@ -47,8 +47,8 @@ define Package/kexec
   $(call Package/kexec-tools/Default)
   TITLE:=Kernel boots kernel
   DEPENDS:=\
-	@(armeb||arm||aarch64||i386||x86_64||powerpc64||mipsel||mips) \
-	+KEXEC_ZLIB:zlib +KEXEC_LZMA:liblzma +KEXEC_ZSTD:libzstd @KERNEL_KEXEC
+	@(armeb||arm||i386||x86_64||powerpc64||mipsel||mips) \
+	+KEXEC_ZLIB:zlib +KEXEC_LZMA:liblzma @KERNEL_KEXEC
 endef
 
 define Package/kexec/description
@@ -58,7 +58,7 @@ endef
 define Package/kdump
   $(call Package/kexec-tools/Default)
   TITLE:=Kernel crash analysis
-  DEPENDS:=+kexec @(i386||x86_64||arm||aarch64) @KERNEL_CRASH_DUMP
+  DEPENDS:=+kexec @(i386||x86_64||arm) @KERNEL_CRASH_DUMP
 endef
 
 define Package/kdump/description
@@ -86,7 +86,6 @@ CONFIGURE_ARGS = \
 		--sysconfdir=/etc \
 		$(if $(CONFIG_KEXEC_ZLIB),--with,--without)-zlib \
 		$(if $(CONFIG_KEXEC_LZMA),--with,--without)-lzma \
-		$(if $(CONFIG_KEXEC_ZSTD),--with,--without)-zstd \
 		TARGET_LD="$(TARGET_CROSS)ld"
 
 CONFIGURE_VARS += \

package/boot/kexec-tools/patches/010-Fix-building-on-x86_64-with-binutils-2.41.patch

@@ -0,0 +1,81 @@
+From 328de8e00e298f00d7ba6b25dc3950147e9642e6 Mon Sep 17 00:00:00 2001
+From: Michel Lind <salimma@fedoraproject.org>
+Date: Tue, 30 Jan 2024 04:14:31 -0600
+Subject: [PATCH] Fix building on x86_64 with binutils 2.41
+
+Newer versions of the GNU assembler (observed with binutils 2.41) will
+complain about the ".arch i386" in files assembled with "as --64",
+with the message "Error: 64bit mode not supported on 'i386'".
+
+Fix by moving ".arch i386" below the relevant ".code32" directive, so
+that the assembler is no longer expecting 64-bit instructions to be used
+by the time that the ".arch i386" directive is encountered.
+
+Based on similar iPXE fix:
+https://github.com/ipxe/ipxe/commit/6ca597eee
+
+Signed-off-by: Michel Lind <michel@michel-slm.name>
+Signed-off-by: Simon Horman <horms@kernel.org>
+---
+ purgatory/arch/i386/entry32-16-debug.S | 2 +-
+ purgatory/arch/i386/entry32-16.S       | 2 +-
+ purgatory/arch/i386/entry32.S          | 2 +-
+ purgatory/arch/i386/setup-x86.S        | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/purgatory/arch/i386/entry32-16-debug.S
++++ b/purgatory/arch/i386/entry32-16-debug.S
+@@ -25,10 +25,10 @@
+ 	.globl entry16_debug_pre32
+ 	.globl entry16_debug_first32
+ 	.globl entry16_debug_old_first32
+-	.arch i386
+ 	.balign 16
+ entry16_debug:
+ 	.code32
++	.arch i386
+ 	/* Compute where I am running at (assumes esp valid) */
+ 	call	1f
+ 1:	popl	%ebx
+--- a/purgatory/arch/i386/entry32-16.S
++++ b/purgatory/arch/i386/entry32-16.S
+@@ -20,10 +20,10 @@
+ #undef i386	
+ 	.text
+ 	.globl entry16, entry16_regs
+-	.arch i386
+ 	.balign 16
+ entry16:
+ 	.code32
++	.arch i386
+ 	/* Compute where I am running at (assumes esp valid) */
+ 	call	1f
+ 1:	popl	%ebx
+--- a/purgatory/arch/i386/entry32.S
++++ b/purgatory/arch/i386/entry32.S
+@@ -20,10 +20,10 @@
+ #undef i386
+ 
+ 	.text
+-	.arch	i386
+ 	.globl entry32, entry32_regs
+ entry32:
+ 	.code32
++	.arch	i386
+ 
+ 	/* Setup a gdt that should that is generally usefully */
+ 	lgdt	%cs:gdt
+--- a/purgatory/arch/i386/setup-x86.S
++++ b/purgatory/arch/i386/setup-x86.S
+@@ -21,10 +21,10 @@
+ #undef i386
+ 
+ 	.text
+-	.arch	i386
+ 	.globl purgatory_start
+ purgatory_start:
+ 	.code32
++	.arch	i386
+ 
+ 	/* Load a gdt so I know what the segment registers are */
+ 	lgdt	%cs:gdt

package/boot/kexec-tools/patches/020-i386-improve-basename-compatibility.patch

@@ -0,0 +1,37 @@
+From 99f62f58fac57214ecc3c9aabf6bf61ac1e1201d Mon Sep 17 00:00:00 2001
+From: Tony Ambardar <itugrok@yahoo.com>
+Date: Fri, 7 Jun 2024 21:54:56 -0700
+Subject: [PATCH] i386: improve basename() compatibility
+
+Drop usage of glibc basename() in favour of a simpler implementation that
+works across GNU and musl libc, and is similar to existing code in fs2dt.c.
+
+This fixes compile errors seen building against musl.
+
+Signed-off-by: Tony Ambardar <itugrok@yahoo.com>
+---
+ kexec/arch/i386/x86-linux-setup.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/kexec/arch/i386/x86-linux-setup.c
++++ b/kexec/arch/i386/x86-linux-setup.c
+@@ -318,6 +318,7 @@ static int add_edd_entry(struct x86_linu
+ 	uint8_t devnum, version;
+ 	uint32_t mbr_sig;
+ 	struct edd_info *edd_info;
++	char *basename = strrchr(sysfs_name,'/') + 1;
+ 
+ 	if (!current_mbr || !current_edd) {
+ 		fprintf(stderr, "%s: current_edd and current_edd "
+@@ -329,9 +330,9 @@ static int add_edd_entry(struct x86_linu
+ 	memset(edd_info, 0, sizeof(struct edd_info));
+ 
+ 	/* extract the device number */
+-	if (sscanf(basename(sysfs_name), "int13_dev%hhx", &devnum) != 1) {
++	if (sscanf(basename, "int13_dev%hhx", &devnum) != 1) {
+ 		fprintf(stderr, "Invalid format of int13_dev dir "
+-				"entry: %s\n", basename(sysfs_name));
++				"entry: %s\n", basename);
+ 		return -1;
+ 	}
+ 

package/boot/uboot-airoha/Makefile

@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2026.01
-PKG_HASH:=b60d5865cefdbc75da8da4156c56c458e00de75a49b80c1a2e58a96e30ad0d54
+PKG_VERSION:=2025.10
+PKG_HASH:=b4f032848e56cc8f213ad59f9132c084dbbb632bc29176d024e58220e0efdf4a
 PKG_BUILD_DEPENDS:=arm-trusted-firmware-tools/host
 
 UBOOT_USE_INTREE_DTC:=1
@@ -16,16 +16,6 @@ define U-Boot/Default
   FIP_COMPRESS:=1
 endef
 
-define U-Boot/en7523_rfb
-  NAME:=EN7523 Reference Board
-  UBOOT_CONFIG:=en7523_evb
-  BUILD_DEVICES:=airoha_en7523-evb
-  BUILD_SUBTARGET:=en7523
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_IMAGE:=en7523-bl2.bin
-  BL31_IMAGE:=en7523-bl31.bin
-endef
-
 define U-Boot/an7581_rfb
   NAME:=AN7581 Reference Board
   UBOOT_CONFIG:=an7581_evb
@@ -47,7 +37,6 @@ define U-Boot/an7583_rfb
 endef
 
 UBOOT_TARGETS := \
-	en7523_rfb \
 	an7581_rfb \
 	an7583_rfb
 

package/boot/uboot-airoha/patches/202-mtd-spinand-Use-the-spi-mem-dirmap-API.patch

@@ -0,0 +1,315 @@
+From f45ae9019afb838979792e4237e344003151fbf7 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Sun, 12 Nov 2023 20:57:52 +0300
+Subject: [PATCH 1/5] mtd: spinand: Use the spi-mem dirmap API
+
+Make use of the spi-mem direct mapping API to let advanced controllers
+optimize read/write operations when they support direct mapping.
+
+Based on a linux commit 981d1aa0697c ("mtd: spinand: Use the spi-mem dirmap API")
+created by Boris Brezillon <bbrezillon@kernel.org> with additional
+fixes taken from Linux 6.10.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
+---
+ drivers/mtd/nand/spi/core.c | 185 +++++++++++++++++-------------------
+ include/linux/mtd/spinand.h |   7 ++
+ 2 files changed, 95 insertions(+), 97 deletions(-)
+
+--- a/drivers/mtd/nand/spi/core.c
++++ b/drivers/mtd/nand/spi/core.c
+@@ -41,21 +41,6 @@ struct spinand_plat {
+ /* SPI NAND index visible in MTD names */
+ static int spi_nand_idx;
+ 
+-static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
+-					  const struct nand_page_io_req *req,
+-					  u16 *column)
+-{
+-	struct nand_device *nand = spinand_to_nand(spinand);
+-	unsigned int shift;
+-
+-	if (nand->memorg.planes_per_lun < 2)
+-		return;
+-
+-	/* The plane number is passed in MSB just above the column address */
+-	shift = fls(nand->memorg.pagesize);
+-	*column |= req->pos.plane << shift;
+-}
+-
+ static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
+ {
+ 	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
+@@ -249,27 +234,21 @@ static int spinand_load_page_op(struct spinand_device *spinand,
+ static int spinand_read_from_cache_op(struct spinand_device *spinand,
+ 				      const struct nand_page_io_req *req)
+ {
+-	struct spi_mem_op op = *spinand->op_templates.read_cache;
+ 	struct nand_device *nand = spinand_to_nand(spinand);
+ 	struct mtd_info *mtd = nanddev_to_mtd(nand);
+-	struct nand_page_io_req adjreq = *req;
++	struct spi_mem_dirmap_desc *rdesc;
+ 	unsigned int nbytes = 0;
+ 	void *buf = NULL;
+ 	u16 column = 0;
+-	int ret;
++	ssize_t ret;
+ 
+ 	if (req->datalen) {
+-		adjreq.datalen = nanddev_page_size(nand);
+-		adjreq.dataoffs = 0;
+-		adjreq.databuf.in = spinand->databuf;
+ 		buf = spinand->databuf;
+-		nbytes = adjreq.datalen;
++		nbytes = nanddev_page_size(nand);
++		column = 0;
+ 	}
+ 
+ 	if (req->ooblen) {
+-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
+-		adjreq.ooboffs = 0;
+-		adjreq.oobbuf.in = spinand->oobbuf;
+ 		nbytes += nanddev_per_page_oobsize(nand);
+ 		if (!buf) {
+ 			buf = spinand->oobbuf;
+@@ -277,28 +256,19 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
+ 		}
+ 	}
+ 
+-	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
+-	op.addr.val = column;
++	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
+ 
+-	/*
+-	 * Some controllers are limited in term of max RX data size. In this
+-	 * case, just repeat the READ_CACHE operation after updating the
+-	 * column.
+-	 */
+ 	while (nbytes) {
+-		op.data.buf.in = buf;
+-		op.data.nbytes = nbytes;
+-		ret = spi_mem_adjust_op_size(spinand->slave, &op);
+-		if (ret)
++		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
++		if (ret < 0)
+ 			return ret;
+ 
+-		ret = spi_mem_exec_op(spinand->slave, &op);
+-		if (ret)
+-			return ret;
++		if (!ret || ret > nbytes)
++			return -EIO;
+ 
+-		buf += op.data.nbytes;
+-		nbytes -= op.data.nbytes;
+-		op.addr.val += op.data.nbytes;
++		nbytes -= ret;
++		column += ret;
++		buf += ret;
+ 	}
+ 
+ 	if (req->datalen)
+@@ -322,14 +292,12 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
+ static int spinand_write_to_cache_op(struct spinand_device *spinand,
+ 				     const struct nand_page_io_req *req)
+ {
+-	struct spi_mem_op op = *spinand->op_templates.write_cache;
+ 	struct nand_device *nand = spinand_to_nand(spinand);
+ 	struct mtd_info *mtd = nanddev_to_mtd(nand);
+-	struct nand_page_io_req adjreq = *req;
+-	unsigned int nbytes = 0;
+-	void *buf = NULL;
+-	u16 column = 0;
+-	int ret;
++	struct spi_mem_dirmap_desc *wdesc;
++	unsigned int nbytes, column = 0;
++	void *buf = spinand->databuf;
++	ssize_t ret;
+ 
+ 	/*
+ 	 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
+@@ -338,19 +306,12 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
+ 	 * the data portion of the page, otherwise we might corrupt the BBM or
+ 	 * user data previously programmed in OOB area.
+ 	 */
+-	memset(spinand->databuf, 0xff,
+-	       nanddev_page_size(nand) +
+-	       nanddev_per_page_oobsize(nand));
++	nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
++	memset(spinand->databuf, 0xff, nbytes);
+ 
+-	if (req->datalen) {
++	if (req->datalen)
+ 		memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
+ 		       req->datalen);
+-		adjreq.dataoffs = 0;
+-		adjreq.datalen = nanddev_page_size(nand);
+-		adjreq.databuf.out = spinand->databuf;
+-		nbytes = adjreq.datalen;
+-		buf = spinand->databuf;
+-	}
+ 
+ 	if (req->ooblen) {
+ 		if (req->mode == MTD_OPS_AUTO_OOB)
+@@ -361,52 +322,21 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
+ 		else
+ 			memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
+ 			       req->ooblen);
+-
+-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
+-		adjreq.ooboffs = 0;
+-		nbytes += nanddev_per_page_oobsize(nand);
+-		if (!buf) {
+-			buf = spinand->oobbuf;
+-			column = nanddev_page_size(nand);
+-		}
+ 	}
+ 
+-	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
+-
+-	op = *spinand->op_templates.write_cache;
+-	op.addr.val = column;
++	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
+ 
+-	/*
+-	 * Some controllers are limited in term of max TX data size. In this
+-	 * case, split the operation into one LOAD CACHE and one or more
+-	 * LOAD RANDOM CACHE.
+-	 */
+ 	while (nbytes) {
+-		op.data.buf.out = buf;
+-		op.data.nbytes = nbytes;
+-
+-		ret = spi_mem_adjust_op_size(spinand->slave, &op);
+-		if (ret)
+-			return ret;
+-
+-		ret = spi_mem_exec_op(spinand->slave, &op);
+-		if (ret)
++		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
++		if (ret < 0)
+ 			return ret;
+ 
+-		buf += op.data.nbytes;
+-		nbytes -= op.data.nbytes;
+-		op.addr.val += op.data.nbytes;
++		if (!ret || ret > nbytes)
++			return -EIO;
+ 
+-		/*
+-		 * We need to use the RANDOM LOAD CACHE operation if there's
+-		 * more than one iteration, because the LOAD operation resets
+-		 * the cache to 0xff.
+-		 */
+-		if (nbytes) {
+-			column = op.addr.val;
+-			op = *spinand->op_templates.update_cache;
+-			op.addr.val = column;
+-		}
++		nbytes -= ret;
++		column += ret;
++		buf += ret;
+ 	}
+ 
+ 	return 0;
+@@ -819,6 +749,59 @@ static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
+ 	return ret;
+ }
+ 
++static int spinand_create_dirmap(struct spinand_device *spinand,
++				 unsigned int plane)
++{
++	struct nand_device *nand = spinand_to_nand(spinand);
++	struct spi_mem_dirmap_info info = {
++		.length = nanddev_page_size(nand) +
++			  nanddev_per_page_oobsize(nand),
++	};
++	struct spi_mem_dirmap_desc *desc;
++
++	/* The plane number is passed in MSB just above the column address */
++	info.offset = plane << fls(nand->memorg.pagesize);
++
++	info.op_tmpl = *spinand->op_templates.update_cache;
++	desc = spi_mem_dirmap_create(spinand->slave, &info);
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++
++	spinand->dirmaps[plane].wdesc = desc;
++
++	info.op_tmpl = *spinand->op_templates.read_cache;
++	desc = spi_mem_dirmap_create(spinand->slave, &info);
++	if (IS_ERR(desc)) {
++		spi_mem_dirmap_destroy(spinand->dirmaps[plane].wdesc);
++		return PTR_ERR(desc);
++	}
++
++	spinand->dirmaps[plane].rdesc = desc;
++
++	return 0;
++}
++
++static int spinand_create_dirmaps(struct spinand_device *spinand)
++{
++	struct nand_device *nand = spinand_to_nand(spinand);
++	int i, ret;
++
++	spinand->dirmaps = devm_kzalloc(spinand->slave->dev,
++					sizeof(*spinand->dirmaps) *
++					nand->memorg.planes_per_lun,
++					GFP_KERNEL);
++	if (!spinand->dirmaps)
++		return -ENOMEM;
++
++	for (i = 0; i < nand->memorg.planes_per_lun; i++) {
++		ret = spinand_create_dirmap(spinand, i);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
+ static const struct nand_ops spinand_ops = {
+ 	.erase = spinand_erase,
+ 	.markbad = spinand_markbad,
+@@ -1134,6 +1117,14 @@ static int spinand_init(struct spinand_device *spinand)
+ 		goto err_free_bufs;
+ 	}
+ 
++	ret = spinand_create_dirmaps(spinand);
++	if (ret) {
++		dev_err(spinand->slave->dev,
++			"Failed to create direct mappings for read/write operations (err = %d)\n",
++			ret);
++		goto err_manuf_cleanup;
++	}
++
+ 	/* After power up, all blocks are locked, so unlock them here. */
+ 	for (i = 0; i < nand->memorg.ntargets; i++) {
+ 		ret = spinand_select_target(spinand, i);
+diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
+index 6fe6fd520a4..163269313f6 100644
+--- a/include/linux/mtd/spinand.h
++++ b/include/linux/mtd/spinand.h
+@@ -363,6 +363,11 @@ struct spinand_info {
+ 		__VA_ARGS__						\
+ 	}
+ 
++struct spinand_dirmap {
++	struct spi_mem_dirmap_desc *wdesc;
++	struct spi_mem_dirmap_desc *rdesc;
++};
++
+ /**
+  * struct spinand_device - SPI NAND device instance
+  * @base: NAND device instance
+@@ -406,6 +411,8 @@ struct spinand_device {
+ 		const struct spi_mem_op *update_cache;
+ 	} op_templates;
+ 
++	struct spinand_dirmap *dirmaps;
++
+ 	int (*select_target)(struct spinand_device *spinand,
+ 			     unsigned int target);
+ 	unsigned int cur_target;

package/boot/uboot-airoha/patches/203-spi-airoha-remove-unnecessary-operation-adjust_op_si.patch

@@ -0,0 +1,46 @@
+From 1e29cf13c183ee457ed70055f5cbff60ff56a726 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Sat, 7 Jun 2025 07:18:12 +0300
+Subject: [PATCH 2/5] spi: airoha: remove unnecessary operation adjust_op_size
+
+This operation is not needed because airoha_snand_write_data() and
+airoha_snand_read_data() will properly handle data transfers above
+SPI_MAX_TRANSFER_SIZE.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/spi/airoha_snfi_spi.c | 16 ----------------
+ 1 file changed, 16 deletions(-)
+
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -525,21 +525,6 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
+ 				  SPI_NFI_CUS_SEC_SIZE, val);
+ }
+ 
+-static int airoha_snand_adjust_op_size(struct spi_slave *slave,
+-				       struct spi_mem_op *op)
+-{
+-	size_t max_len;
+-
+-	max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
+-	if (max_len >= 160)
+-		return -EOPNOTSUPP;
+-
+-	if (op->data.nbytes > 160 - max_len)
+-		op->data.nbytes = 160 - max_len;
+-
+-	return 0;
+-}
+-
+ static bool airoha_snand_supports_op(struct spi_slave *slave,
+ 				     const struct spi_mem_op *op)
+ {
+@@ -691,7 +676,6 @@ static int airoha_snand_nfi_setup(struct spi_slave *slave,
+ }
+ 
+ static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+-	.adjust_op_size = airoha_snand_adjust_op_size,
+ 	.supports_op = airoha_snand_supports_op,
+ 	.exec_op = airoha_snand_exec_op,
+ };

package/boot/uboot-airoha/patches/204-spi-airoha-add-support-of-dual-quad-wires-spi-modes-.patch

@@ -0,0 +1,257 @@
+From fe8c32af9d8c8ff8875efece82001680fc300ad5 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Sat, 7 Jun 2025 09:09:38 +0300
+Subject: [PATCH 3/5] spi: airoha: add support of dual/quad wires spi modes
+ to exec_op() handler
+
+Booting without this patch and disabled dirmap support results in
+
+[    2.980719] spi-nand spi0.0: Micron SPI NAND was found.
+[    2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
+[    2.994709] 2 fixed-partitions partitions found on MTD device spi0.0
+[    3.001075] Creating 2 MTD partitions on "spi0.0":
+[    3.005862] 0x000000000000-0x000000020000 : "bl2"
+[    3.011272] 0x000000020000-0x000010000000 : "ubi"
+...
+[    6.195594] ubi0: attaching mtd1
+[   13.338398] ubi0: scanning is finished
+[   13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found
+[   13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
+[   13.356897] UBI error: cannot attach mtd1
+
+If dirmap is disabled or not supported in the spi driver, the dirmap requests
+will be executed via exec_op() handler. Thus, if the hardware supports
+dual/quad spi modes, then corresponding requests will be sent to exec_op()
+handler. Current driver does not support such requests, so error is arrised.
+As result the flash can't be read/write.
+
+This patch adds support of dual and quad wires spi modes to exec_op() handler.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/spi/airoha_snfi_spi.c | 143 +++++++++++++++++++++++++++-------
+ 1 file changed, 117 insertions(+), 26 deletions(-)
+
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -186,6 +186,14 @@
+ #define SPI_NAND_OP_RESET			0xff
+ #define SPI_NAND_OP_DIE_SELECT			0xc2
+ 
++/* SNAND FIFO commands */
++#define SNAND_FIFO_TX_BUSWIDTH_SINGLE		0x08
++#define SNAND_FIFO_TX_BUSWIDTH_DUAL		0x09
++#define SNAND_FIFO_TX_BUSWIDTH_QUAD		0x0a
++#define SNAND_FIFO_RX_BUSWIDTH_SINGLE		0x0c
++#define SNAND_FIFO_RX_BUSWIDTH_DUAL		0x0e
++#define SNAND_FIFO_RX_BUSWIDTH_QUAD		0x0f
++
+ #define SPI_NAND_CACHE_SIZE			(SZ_4K + SZ_256)
+ #define SPI_MAX_TRANSFER_SIZE			511
+ 
+@@ -380,10 +388,26 @@ static int airoha_snand_set_mode(struct airoha_snand_priv *priv,
+ 	return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
+ }
+ 
+-static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
+-				   const u8 *data, int len)
++static int airoha_snand_write_data(struct airoha_snand_priv *priv,
++				   const u8 *data, int len, int buswidth)
+ {
+ 	int i, data_len;
++	u8 cmd;
++
++	switch (buswidth) {
++	case 0:
++	case 1:
++		cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
++		break;
++	case 2:
++		cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
++		break;
++	case 4:
++		cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
++		break;
++	default:
++		return -EINVAL;
++	}
+ 
+ 	for (i = 0; i < len; i += data_len) {
+ 		int err;
+@@ -402,16 +426,32 @@ static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
+ 	return 0;
+ }
+ 
+-static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data,
+-				  int len)
++static int airoha_snand_read_data(struct airoha_snand_priv *priv,
++				  u8 *data, int len, int buswidth)
+ {
+ 	int i, data_len;
++	u8 cmd;
++
++	switch (buswidth) {
++	case 0:
++	case 1:
++		cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
++		break;
++	case 2:
++		cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
++		break;
++	case 4:
++		cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
++		break;
++	default:
++		return -EINVAL;
++	}
+ 
+ 	for (i = 0; i < len; i += data_len) {
+ 		int err;
+ 
+ 		data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
+-		err = airoha_snand_set_fifo_op(priv, 0xc, data_len);
++		err = airoha_snand_set_fifo_op(priv, cmd, data_len);
+ 		if (err)
+ 			return err;
+ 
+@@ -525,6 +565,38 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
+ 				  SPI_NFI_CUS_SEC_SIZE, val);
+ }
+ 
++static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
++{
++	if (op->addr.nbytes != 2)
++		return false;
++
++	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
++	    op->addr.buswidth != 4)
++		return false;
++
++	switch (op->data.dir) {
++	case SPI_MEM_DATA_IN:
++		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
++			return false;
++
++		/* quad in / quad out */
++		if (op->addr.buswidth == 4)
++			return op->data.buswidth == 4;
++
++		if (op->addr.buswidth == 2)
++			return op->data.buswidth == 2;
++
++		/* standard spi */
++		return op->data.buswidth == 4 || op->data.buswidth == 2 ||
++		       op->data.buswidth == 1;
++	case SPI_MEM_DATA_OUT:
++		return !op->dummy.nbytes && op->addr.buswidth == 1 &&
++		       (op->data.buswidth == 4 || op->data.buswidth == 1);
++	default:
++		return false;
++	}
++}
++
+ static bool airoha_snand_supports_op(struct spi_slave *slave,
+ 				     const struct spi_mem_op *op)
+ {
+@@ -534,6 +606,9 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
+ 	if (op->cmd.buswidth != 1)
+ 		return false;
+ 
++	if (airoha_snand_is_page_ops(op))
++		return true;
++
+ 	return (!op->addr.nbytes || op->addr.buswidth == 1) &&
+ 	       (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
+ 	       (!op->data.nbytes || op->data.buswidth == 1);
+@@ -542,13 +617,29 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
+ static int airoha_snand_exec_op(struct spi_slave *slave,
+ 				const struct spi_mem_op *op)
+ {
+-	u8 data[8], cmd, opcode = op->cmd.opcode;
+ 	struct udevice *bus = slave->dev->parent;
+ 	struct airoha_snand_priv *priv;
++	int op_len, addr_len, dummy_len;
++	u8 buf[20], *data;
+ 	int i, err;
+ 
+ 	priv = dev_get_priv(bus);
+ 
++	op_len = op->cmd.nbytes;
++	addr_len = op->addr.nbytes;
++	dummy_len = op->dummy.nbytes;
++
++	if (op_len + dummy_len + addr_len > sizeof(buf))
++		return -EIO;
++
++	data = buf;
++	for (i = 0; i < op_len; i++)
++		*data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
++	for (i = 0; i < addr_len; i++)
++		*data++ = op->addr.val >> (8 * (addr_len - i - 1));
++	for (i = 0; i < dummy_len; i++)
++		*data++ = 0xff;
++
+ 	/* switch to manual mode */
+ 	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
+ 	if (err < 0)
+@@ -559,40 +650,40 @@ static int airoha_snand_exec_op(struct spi_slave *slave,
+ 		return err;
+ 
+ 	/* opcode */
+-	err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode));
++	data = buf;
++	err = airoha_snand_write_data(priv, data, op_len,
++				      op->cmd.buswidth);
+ 	if (err)
+ 		return err;
+ 
+ 	/* addr part */
+-	cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
+-	put_unaligned_be64(op->addr.val, data);
+-
+-	for (i = ARRAY_SIZE(data) - op->addr.nbytes;
+-	     i < ARRAY_SIZE(data); i++) {
+-		err = airoha_snand_write_data(priv, cmd, &data[i],
+-					      sizeof(data[0]));
++	data += op_len;
++	if (addr_len) {
++		err = airoha_snand_write_data(priv, data, addr_len,
++					      op->addr.buswidth);
+ 		if (err)
+ 			return err;
+ 	}
+ 
+ 	/* dummy */
+-	data[0] = 0xff;
+-	for (i = 0; i < op->dummy.nbytes; i++) {
+-		err = airoha_snand_write_data(priv, 0x8, &data[0],
+-					      sizeof(data[0]));
++	data += addr_len;
++	if (dummy_len) {
++		err = airoha_snand_write_data(priv, data, dummy_len,
++					      op->dummy.buswidth);
+ 		if (err)
+ 			return err;
+ 	}
+ 
+ 	/* data */
+-	if (op->data.dir == SPI_MEM_DATA_IN) {
+-		err = airoha_snand_read_data(priv, op->data.buf.in,
+-					     op->data.nbytes);
+-		if (err)
+-			return err;
+-	} else {
+-		err = airoha_snand_write_data(priv, 0x8, op->data.buf.out,
+-					      op->data.nbytes);
++	if (op->data.nbytes) {
++		if (op->data.dir == SPI_MEM_DATA_IN)
++			err = airoha_snand_read_data(priv, op->data.buf.in,
++						     op->data.nbytes,
++						     op->data.buswidth);
++		else
++			err = airoha_snand_write_data(priv, op->data.buf.out,
++						      op->data.nbytes,
++						      op->data.buswidth);
+ 		if (err)
+ 			return err;
+ 	}

package/boot/uboot-airoha/patches/205-spi-airoha-add-dma-support.patch

@@ -0,0 +1,373 @@
+From f1fe2f174f26eb98af35862caea083439e08a344 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Sun, 8 Jun 2025 05:30:22 +0300
+Subject: [PATCH 4/5] spi: airoha: add dma support
+
+This patch speed up cache reading/writing/updating opearions.
+It was tested on en7523/an7581 and some other Airoha chips.
+
+It will speed up
+ * page reading/writing without oob
+ * page reading/writing with oob
+ * oob reading/writing (significant for UBI scanning)
+
+The only know issue appears in a very specific conditions for en7523 family
+chips only.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/spi/airoha_snfi_spi.c | 309 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 309 insertions(+)
+
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -141,12 +141,14 @@
+ #define SPI_NFI_CUS_SEC_SIZE_EN			BIT(16)
+ 
+ #define REG_SPI_NFI_RD_CTL2			0x0510
++
+ #define REG_SPI_NFI_RD_CTL3			0x0514
+ 
+ #define REG_SPI_NFI_PG_CTL1			0x0524
+ #define SPI_NFI_PG_LOAD_CMD			GENMASK(15, 8)
+ 
+ #define REG_SPI_NFI_PG_CTL2			0x0528
++
+ #define REG_SPI_NFI_NOR_PROG_ADDR		0x052c
+ #define REG_SPI_NFI_NOR_RD_ADDR			0x0534
+ 
+@@ -219,6 +221,8 @@ struct airoha_snand_priv {
+ 		u8 sec_num;
+ 		u8 spare_size;
+ 	} nfi_cfg;
++
++	u8 *txrx_buf;
+ };
+ 
+ static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv,
+@@ -614,6 +618,302 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
+ 	       (!op->data.nbytes || op->data.buswidth == 1);
+ }
+ 
++static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
++{
++	struct spi_slave *slave = desc->slave;
++	struct udevice *bus = slave->dev->parent;
++	struct airoha_snand_priv *priv = dev_get_priv(bus);
++
++	if (!priv->txrx_buf)
++		return -EINVAL;
++
++	if (desc->info.offset + desc->info.length > U32_MAX)
++		return -EINVAL;
++
++	if (!airoha_snand_supports_op(desc->slave, &desc->info.op_tmpl))
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
++					u64 offs, size_t len, void *buf)
++{
++	struct spi_mem_op *op = &desc->info.op_tmpl;
++	struct spi_slave *slave = desc->slave;
++	struct udevice *bus = slave->dev->parent;
++	struct airoha_snand_priv *priv = dev_get_priv(bus);
++	u8 *txrx_buf = priv->txrx_buf;
++	dma_addr_t dma_addr;
++	u32 val, rd_mode;
++	int err;
++
++	switch (op->cmd.opcode) {
++	case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
++		rd_mode = 1;
++		break;
++	case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
++		rd_mode = 2;
++		break;
++	default:
++		rd_mode = 0;
++		break;
++	}
++
++	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
++	if (err < 0)
++		return err;
++
++	err = airoha_snand_nfi_config(priv);
++	if (err)
++		goto error_dma_mode_off;
++
++	dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
++				  DMA_FROM_DEVICE);
++
++	/* set dma addr */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
++			   dma_addr);
++	if (err)
++		goto error_dma_unmap;
++
++	/* set cust sec size */
++	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
++	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
++	err = regmap_update_bits(priv->regmap_nfi,
++				 REG_SPI_NFI_SNF_MISC_CTL2,
++				 SPI_NFI_READ_DATA_BYTE_NUM, val);
++	if (err)
++		goto error_dma_unmap;
++
++	/* set read command */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
++			   op->cmd.opcode);
++	if (err)
++		goto error_dma_unmap;
++
++	/* set read mode */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
++			   FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
++	if (err)
++		goto error_dma_unmap;
++
++	/* set read addr: zero page offset + descriptor read offset */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL3,
++			   desc->info.offset);
++	if (err)
++		goto error_dma_unmap;
++
++	/* set nfi read */
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
++				 SPI_NFI_OPMODE,
++				 FIELD_PREP(SPI_NFI_OPMODE, 6));
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
++			      SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
++	if (err)
++		goto error_dma_unmap;
++
++	/* trigger dma reading */
++	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
++				SPI_NFI_RD_TRIG);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
++			      SPI_NFI_RD_TRIG);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_read_poll_timeout(priv->regmap_nfi,
++				       REG_SPI_NFI_SNF_STA_CTL1, val,
++				       (val & SPI_NFI_READ_FROM_CACHE_DONE),
++				       0, 1 * MSEC_PER_SEC);
++	if (err)
++		goto error_dma_unmap;
++
++	/*
++	 * SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
++	 * of dirmap_read operation even if it is already set.
++	 */
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
++				 SPI_NFI_READ_FROM_CACHE_DONE,
++				 SPI_NFI_READ_FROM_CACHE_DONE);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
++				       val, (val & SPI_NFI_AHB_DONE), 0,
++				       1 * MSEC_PER_SEC);
++	if (err)
++		goto error_dma_unmap;
++
++	/* DMA read need delay for data ready from controller to DRAM */
++	udelay(1);
++
++	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
++
++	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
++	if (err < 0)
++		return err;
++
++	memcpy(buf, txrx_buf + offs, len);
++
++	return len;
++
++error_dma_unmap:
++	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
++error_dma_mode_off:
++	airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
++	return err;
++}
++
++static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
++					 u64 offs, size_t len, const void *buf)
++{
++	struct spi_slave *slave = desc->slave;
++	struct udevice *bus = slave->dev->parent;
++	struct airoha_snand_priv *priv = dev_get_priv(bus);
++	u8 *txrx_buf = priv->txrx_buf;
++	dma_addr_t dma_addr;
++	u32 wr_mode, val, opcode;
++	int err;
++
++	opcode = desc->info.op_tmpl.cmd.opcode;
++	switch (opcode) {
++	case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
++	case SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE:
++		wr_mode = 0;
++		break;
++	case SPI_NAND_OP_PROGRAM_LOAD_QUAD:
++	case SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD:
++		wr_mode = 2;
++		break;
++	default:
++		/* unknown opcode */
++		return -EOPNOTSUPP;
++	}
++
++	memcpy(txrx_buf + offs, buf, len);
++
++	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
++	if (err < 0)
++		return err;
++
++	err = airoha_snand_nfi_config(priv);
++	if (err)
++		goto error_dma_mode_off;
++
++	dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
++				  DMA_TO_DEVICE);
++
++	/* set dma addr */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
++			   dma_addr);
++	if (err)
++		goto error_dma_unmap;
++
++	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
++			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
++	err = regmap_update_bits(priv->regmap_nfi,
++				 REG_SPI_NFI_SNF_MISC_CTL2,
++				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
++	if (err)
++		goto error_dma_unmap;
++
++	/* set write command */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL1,
++			   FIELD_PREP(SPI_NFI_PG_LOAD_CMD, opcode));
++	if (err)
++		goto error_dma_unmap;
++
++	/* set write mode */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
++			   FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
++	if (err)
++		goto error_dma_unmap;
++
++	/* set write addr: zero page offset + descriptor write offset */
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL2,
++			   desc->info.offset);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
++				SPI_NFI_READ_MODE);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
++				 SPI_NFI_OPMODE,
++				 FIELD_PREP(SPI_NFI_OPMODE, 3));
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
++			      SPI_NFI_DMA_MODE);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
++	if (err)
++		goto error_dma_unmap;
++
++	/* trigger dma writing */
++	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
++				SPI_NFI_WR_TRIG);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
++			      SPI_NFI_WR_TRIG);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
++				       val, (val & SPI_NFI_AHB_DONE), 0,
++				       1 * MSEC_PER_SEC);
++	if (err)
++		goto error_dma_unmap;
++
++	err = regmap_read_poll_timeout(priv->regmap_nfi,
++				       REG_SPI_NFI_SNF_STA_CTL1, val,
++				       (val & SPI_NFI_LOAD_TO_CACHE_DONE),
++				       0, 1 * MSEC_PER_SEC);
++	if (err)
++		goto error_dma_unmap;
++
++	/*
++	 * SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
++	 * of dirmap_write operation even if it is already set.
++	 */
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
++				 SPI_NFI_LOAD_TO_CACHE_DONE,
++				 SPI_NFI_LOAD_TO_CACHE_DONE);
++	if (err)
++		goto error_dma_unmap;
++
++	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
++
++	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
++	if (err < 0)
++		return err;
++
++	return len;
++
++error_dma_unmap:
++	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
++error_dma_mode_off:
++	airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
++	return err;
++}
++
+ static int airoha_snand_exec_op(struct spi_slave *slave,
+ 				const struct spi_mem_op *op)
+ {
+@@ -696,6 +996,12 @@ static int airoha_snand_probe(struct udevice *dev)
+ 	struct airoha_snand_priv *priv = dev_get_priv(dev);
+ 	int ret;
+ 
++	priv->txrx_buf = memalign(ARCH_DMA_MINALIGN, SPI_NAND_CACHE_SIZE);
++	if (!priv->txrx_buf) {
++		dev_err(dev, "failed to alloacate memory for dirmap\n");
++		return -ENOMEM;
++	}
++
+ 	ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0);
+ 	if (ret) {
+ 		dev_err(dev, "failed to init spi ctrl regmap\n");
+@@ -769,6 +1075,9 @@ static int airoha_snand_nfi_setup(struct spi_slave *slave,
+ static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ 	.supports_op = airoha_snand_supports_op,
+ 	.exec_op = airoha_snand_exec_op,
++	.dirmap_create = airoha_snand_dirmap_create,
++	.dirmap_read = airoha_snand_dirmap_read,
++	.dirmap_write = airoha_snand_dirmap_write,
+ };
+ 
+ static const struct dm_spi_ops airoha_snfi_spi_ops = {

package/boot/uboot-airoha/patches/206-spi-airoha-support-of-dualio-quadio-flash-reading-co.patch

@@ -1,7 +1,7 @@
-From 80b09137aeab27e59004383058f8cc696a9ee048 Mon Sep 17 00:00:00 2001
+From 2ebbccfa053993d0fe90bee523020a8f796e8988 Mon Sep 17 00:00:00 2001
 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 12 Oct 2025 15:16:59 +0300
-Subject: [PATCH 08/14] spi: airoha: support of dualio/quadio flash reading
+Date: Sun, 8 Jun 2025 05:30:22 +0300
+Subject: [PATCH 5/5] spi: airoha: support of dualio/quadio flash reading
  commands
 
 Airoha snfi spi controller supports acceleration of DUAL/QUAD
@@ -11,25 +11,21 @@ so we can issue corresponding DUAL/QUAD operation instead of
 DUAL_IO/QUAD_IO one.
 
 Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://patch.msgid.link/20251012121707.2296160-9-mikhail.kshevetskiy@iopsys.eu
-Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
- drivers/spi/spi-airoha-snfi.c | 28 ++++++++++++++++++++++------
- 1 file changed, 22 insertions(+), 6 deletions(-)
+ drivers/spi/airoha_snfi_spi.c | 27 +++++++++++++++++++++------
+ 1 file changed, 21 insertions(+), 6 deletions(-)
 
---- a/drivers/spi/spi-airoha-snfi.c
-+++ b/drivers/spi/spi-airoha-snfi.c
-@@ -147,6 +147,8 @@
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -141,6 +141,7 @@
  #define SPI_NFI_CUS_SEC_SIZE_EN			BIT(16)
  
  #define REG_SPI_NFI_RD_CTL2			0x0510
 +#define SPI_NFI_DATA_READ_CMD			GENMASK(7, 0)
-+
+ 
  #define REG_SPI_NFI_RD_CTL3			0x0514
  
- #define REG_SPI_NFI_PG_CTL1			0x0524
-@@ -179,7 +181,9 @@
+@@ -175,7 +176,9 @@
  #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE	0x03
  #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST	0x0b
  #define SPI_NAND_OP_READ_FROM_CACHE_DUAL	0x3b
@@ -39,21 +35,20 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  #define SPI_NAND_OP_WRITE_ENABLE		0x06
  #define SPI_NAND_OP_WRITE_DISABLE		0x04
  #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE		0x02
-@@ -664,26 +668,38 @@ static int airoha_snand_dirmap_create(st
+@@ -639,25 +642,37 @@ static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
  static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  					u64 offs, size_t len, void *buf)
  {
 -	struct spi_mem_op *op = &desc->info.op_tmpl;
- 	struct spi_device *spi = desc->mem->spi;
- 	struct airoha_snand_ctrl *as_ctrl;
- 	u8 *txrx_buf = spi_get_ctldata(spi);
+ 	struct spi_slave *slave = desc->slave;
+ 	struct udevice *bus = slave->dev->parent;
+ 	struct airoha_snand_priv *priv = dev_get_priv(bus);
+ 	u8 *txrx_buf = priv->txrx_buf;
  	dma_addr_t dma_addr;
 -	u32 val, rd_mode;
 +	u32 val, rd_mode, opcode;
  	int err;
  
- 	as_ctrl = spi_controller_get_devdata(spi->controller);
- 
 -	switch (op->cmd.opcode) {
 +	/*
 +	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
@@ -82,11 +77,11 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +		return -EOPNOTSUPP;
  	}
  
- 	err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
-@@ -717,7 +733,7 @@ static ssize_t airoha_snand_dirmap_read(
+ 	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
+@@ -688,7 +703,7 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  
  	/* set read command */
- 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
+ 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
 -			   op->cmd.opcode);
 +			   FIELD_PREP(SPI_NFI_DATA_READ_CMD, opcode));
  	if (err)

package/boot/uboot-airoha/patches/207-spi-airoha-avoid-setting-of-page-oob-sizes-in-REG_SP.patch

@@ -1,7 +1,7 @@
-From 70eec454f2d6cdfab547c262781acd38328e11a1 Mon Sep 17 00:00:00 2001
+From 073de6579cf8c7599d925852bb0fc7fa50378dd3 Mon Sep 17 00:00:00 2001
 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 12 Oct 2025 15:17:00 +0300
-Subject: [PATCH 09/14] spi: airoha: avoid setting of page/oob sizes in
+Date: Thu, 14 Aug 2025 18:00:32 +0300
+Subject: [PATCH 1/4] spi: airoha: avoid setting of page/oob sizes in
  REG_SPI_NFI_PAGEFMT
 
 spi-airoha-snfi uses custom sector size in REG_SPI_NFI_SECCUS_SIZE
@@ -9,20 +9,18 @@ register, so setting of page/oob sizes in REG_SPI_NFI_PAGEFMT is not
 required.
 
 Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Link: https://patch.msgid.link/20251012121707.2296160-10-mikhail.kshevetskiy@iopsys.eu
-Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
- drivers/spi/spi-airoha-snfi.c | 38 -----------------------------------
+ drivers/spi/airoha_snfi_spi.c | 38 -----------------------------------
  1 file changed, 38 deletions(-)
 
---- a/drivers/spi/spi-airoha-snfi.c
-+++ b/drivers/spi/spi-airoha-snfi.c
-@@ -518,44 +518,6 @@ static int airoha_snand_nfi_config(struc
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -514,44 +514,6 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
  	if (err)
  		return err;
  
 -	/* page format */
--	switch (as_ctrl->nfi_cfg.spare_size) {
+-	switch (priv->nfi_cfg.spare_size) {
 -	case 26:
 -		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
 -		break;
@@ -37,12 +35,12 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 -		break;
 -	}
 -
--	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
 -				 SPI_NFI_SPARE_SIZE, val);
 -	if (err)
 -		return err;
 -
--	switch (as_ctrl->nfi_cfg.page_size) {
+-	switch (priv->nfi_cfg.page_size) {
 -	case 2048:
 -		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
 -		break;
@@ -54,11 +52,11 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 -		break;
 -	}
 -
--	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_PAGEFMT,
+-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
 -				 SPI_NFI_PAGE_SIZE, val);
 -	if (err)
 -		return err;
 -
  	/* sec num */
- 	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ 	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,

package/boot/uboot-airoha/patches/208-spi-airoha-reduce-the-number-of-modification-of-REG_.patch

@@ -1,32 +1,29 @@
-From d1ff30df1d9a4eb4c067795abb5e2a66910fd108 Mon Sep 17 00:00:00 2001
+From 3bd6ca4ddaae4f0a667a9359c8092d2271006687 Mon Sep 17 00:00:00 2001
 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 12 Oct 2025 15:17:01 +0300
-Subject: [PATCH 10/14] spi: airoha: reduce the number of modification of
+Date: Thu, 14 Aug 2025 18:49:34 +0300
+Subject: [PATCH 2/4] spi: airoha: reduce the number of modification of
  REG_SPI_NFI_CNFG and REG_SPI_NFI_SECCUS_SIZE registers
 
 This just reduce the number of modification of REG_SPI_NFI_CNFG and
 REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation.
 
-This patch is a necessary step to avoid reading flash page settings
-from SNFI registers during driver startup.
+This patch is a necessary step to avoid usage of flash specific
+parameters.
 
 Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://patch.msgid.link/20251012121707.2296160-11-mikhail.kshevetskiy@iopsys.eu
-Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
- drivers/spi/spi-airoha-snfi.c | 135 +++++++++++++++++++++++++---------
- 1 file changed, 102 insertions(+), 33 deletions(-)
+ drivers/spi/airoha_snfi_spi.c | 134 +++++++++++++++++++++++++---------
+ 1 file changed, 101 insertions(+), 33 deletions(-)
 
---- a/drivers/spi/spi-airoha-snfi.c
-+++ b/drivers/spi/spi-airoha-snfi.c
-@@ -668,7 +668,48 @@ static ssize_t airoha_snand_dirmap_read(
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -641,7 +641,47 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  	if (err < 0)
  		return err;
  
--	err = airoha_snand_nfi_config(as_ctrl);
+-	err = airoha_snand_nfi_config(priv);
 +	/* NFI reset */
-+	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
 +			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
 +	if (err)
 +		goto error_dma_mode_off;
@@ -38,8 +35,9 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +	 *   - Setup for reading (SPI_NFI_READ_MODE)
 +	 *   - Setup reading command: FIELD_PREP(SPI_NFI_OPMODE, 6)
 +	 *   - Use DMA instead of PIO for data reading
++	 *   - Use AHB bus for DMA transfer
 +	 */
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 +				 SPI_NFI_DMA_MODE |
 +				 SPI_NFI_READ_MODE |
 +				 SPI_NFI_DMA_BURST_EN |
@@ -50,19 +48,17 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +				 SPI_NFI_READ_MODE |
 +				 SPI_NFI_DMA_BURST_EN |
 +				 FIELD_PREP(SPI_NFI_OPMODE, 6));
-+	if (err)
-+		goto error_dma_mode_off;
 +
 +	/* Set number of sector will be read */
-+	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
++	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
 +				 SPI_NFI_SEC_NUM, val);
 +	if (err)
 +		goto error_dma_mode_off;
 +
 +	/* Set custom sector size */
-+	val = as_ctrl->nfi_cfg.sec_size;
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
++	val = priv->nfi_cfg.sec_size;
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
 +				 SPI_NFI_CUS_SEC_SIZE |
 +				 SPI_NFI_CUS_SEC_SIZE_EN,
 +				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
@@ -70,7 +66,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  	if (err)
  		goto error_dma_mode_off;
  
-@@ -684,7 +725,14 @@ static ssize_t airoha_snand_dirmap_read(
+@@ -654,7 +694,14 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  	if (err)
  		goto error_dma_unmap;
  
@@ -83,35 +79,35 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +	 *        = NFI_SNF_MISC_CTL2.read_data_byte_number =
 +	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
 +	 */
- 	val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+ 	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
  	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi,
-@@ -711,18 +759,6 @@ static ssize_t airoha_snand_dirmap_read(
+ 	err = regmap_update_bits(priv->regmap_nfi,
+@@ -681,18 +728,6 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  	if (err)
  		goto error_dma_unmap;
  
 -	/* set nfi read */
--	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 -				 SPI_NFI_OPMODE,
 -				 FIELD_PREP(SPI_NFI_OPMODE, 6));
 -	if (err)
 -		goto error_dma_unmap;
 -
--	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 -			      SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
 -	if (err)
 -		goto error_dma_unmap;
 -
- 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
+ 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
  	if (err)
  		goto error_dma_unmap;
-@@ -815,7 +851,48 @@ static ssize_t airoha_snand_dirmap_write
+@@ -783,7 +818,48 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
  	if (err < 0)
  		return err;
  
--	err = airoha_snand_nfi_config(as_ctrl);
+-	err = airoha_snand_nfi_config(priv);
 +	/* NFI reset */
-+	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
++	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
 +			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
 +	if (err)
 +		goto error_dma_mode_off;
@@ -125,7 +121,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +	 *   - Setup writing command: FIELD_PREP(SPI_NFI_OPMODE, 3)
 +	 *   - Use DMA instead of PIO for data writing
 +	 */
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 +				 SPI_NFI_DMA_MODE |
 +				 SPI_NFI_READ_MODE |
 +				 SPI_NFI_DMA_BURST_EN |
@@ -139,15 +135,15 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +		goto error_dma_mode_off;
 +
 +	/* Set number of sector will be written */
-+	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
++	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
 +				 SPI_NFI_SEC_NUM, val);
 +	if (err)
 +		goto error_dma_mode_off;
 +
 +	/* Set custom sector size */
-+	val = as_ctrl->nfi_cfg.sec_size;
-+	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
++	val = priv->nfi_cfg.sec_size;
++	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
 +				 SPI_NFI_CUS_SEC_SIZE |
 +				 SPI_NFI_CUS_SEC_SIZE_EN,
 +				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
@@ -155,12 +151,12 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  	if (err)
  		goto error_dma_mode_off;
  
-@@ -831,8 +908,16 @@ static ssize_t airoha_snand_dirmap_write
+@@ -796,8 +872,16 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
  	if (err)
  		goto error_dma_unmap;
  
 -	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
--			 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
+-			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
 +	/*
 +	 * Setup transfer length
 +	 * ---------------------
@@ -169,31 +165,31 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
 +	 *        = NFI_SNF_MISC_CTL2.write_data_byte_number =
 +	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
 +	 */
-+	val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
++	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
 +	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi,
+ 	err = regmap_update_bits(priv->regmap_nfi,
  				 REG_SPI_NFI_SNF_MISC_CTL2,
  				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
-@@ -857,22 +942,6 @@ static ssize_t airoha_snand_dirmap_write
+@@ -822,22 +906,6 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
  	if (err)
  		goto error_dma_unmap;
  
--	err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 -				SPI_NFI_READ_MODE);
 -	if (err)
 -		goto error_dma_unmap;
 -
--	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 -				 SPI_NFI_OPMODE,
 -				 FIELD_PREP(SPI_NFI_OPMODE, 3));
 -	if (err)
 -		goto error_dma_unmap;
 -
--	err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
+-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
 -			      SPI_NFI_DMA_MODE);
 -	if (err)
 -		goto error_dma_unmap;
 -
- 	err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
+ 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
  	if (err)
  		goto error_dma_unmap;

package/boot/uboot-airoha/patches/209-spi-airoha-set-custom-sector-size-equal-to-flash-pag.patch

@@ -1,65 +1,60 @@
-From fb81b5cecb8553e3ca2b45288cf340d43c9c2991 Mon Sep 17 00:00:00 2001
+From 8e6cba428ce48005b5b8be64c2a08c98d04865e9 Mon Sep 17 00:00:00 2001
 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 12 Oct 2025 15:17:02 +0300
-Subject: [PATCH 11/14] spi: airoha: set custom sector size equal to flash page
+Date: Thu, 14 Aug 2025 22:47:17 +0300
+Subject: [PATCH 3/4] spi: airoha: set custom sector size equal to flash page
  size
 
 Set custom sector size equal to flash page size including oob. Thus we
 will always read a single sector. The maximum custom sector size is
 8187, so all possible flash sector sizes are supported.
 
-This patch is a necessary step to avoid reading flash page settings
-from SNFI registers during driver startup.
+This patch is a necessary step to avoid usage of flash specific
+parameters.
 
 Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Link: https://patch.msgid.link/20251012121707.2296160-12-mikhail.kshevetskiy@iopsys.eu
-Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
- drivers/spi/spi-airoha-snfi.c | 35 +++++++++++++++++++----------------
+ drivers/spi/airoha_snfi_spi.c | 35 +++++++++++++++++++----------------
  1 file changed, 19 insertions(+), 16 deletions(-)
 
---- a/drivers/spi/spi-airoha-snfi.c
-+++ b/drivers/spi/spi-airoha-snfi.c
-@@ -519,7 +519,7 @@ static int airoha_snand_nfi_config(struc
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -515,7 +515,7 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
  		return err;
  
  	/* sec num */
--	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
+-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
 +	val = FIELD_PREP(SPI_NFI_SEC_NUM, 1);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
  				 SPI_NFI_SEC_NUM, val);
  	if (err)
-@@ -532,7 +532,8 @@ static int airoha_snand_nfi_config(struc
+@@ -528,7 +528,8 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
  		return err;
  
  	/* set cust sec size */
--	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, as_ctrl->nfi_cfg.sec_size);
+-	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, priv->nfi_cfg.sec_size);
 +	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE,
-+			 as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
- 	return regmap_update_bits(as_ctrl->regmap_nfi,
++			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
+ 	return regmap_update_bits(priv->regmap_nfi,
  				  REG_SPI_NFI_SECCUS_SIZE,
  				  SPI_NFI_CUS_SEC_SIZE, val);
-@@ -635,10 +636,13 @@ static ssize_t airoha_snand_dirmap_read(
- 	u8 *txrx_buf = spi_get_ctldata(spi);
+@@ -610,8 +611,11 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ 	u8 *txrx_buf = priv->txrx_buf;
  	dma_addr_t dma_addr;
  	u32 val, rd_mode, opcode;
 +	size_t bytes;
  	int err;
  
- 	as_ctrl = spi_controller_get_devdata(spi->controller);
- 
-+	bytes = as_ctrl->nfi_cfg.sec_num * as_ctrl->nfi_cfg.sec_size;
++	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
 +
  	/*
  	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
  	 * replace them with supported opcodes.
-@@ -697,18 +701,17 @@ static ssize_t airoha_snand_dirmap_read(
- 		goto error_dma_mode_off;
+@@ -669,18 +673,17 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ 				 FIELD_PREP(SPI_NFI_OPMODE, 6));
  
  	/* Set number of sector will be read */
--	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
 -				 SPI_NFI_SEC_NUM, val);
 +				 SPI_NFI_SEC_NUM,
 +				 FIELD_PREP(SPI_NFI_SEC_NUM, 1));
@@ -67,8 +62,8 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  		goto error_dma_mode_off;
  
  	/* Set custom sector size */
--	val = as_ctrl->nfi_cfg.sec_size;
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+-	val = priv->nfi_cfg.sec_size;
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
  				 SPI_NFI_CUS_SEC_SIZE |
  				 SPI_NFI_CUS_SEC_SIZE_EN,
 -				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
@@ -76,13 +71,13 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  				 SPI_NFI_CUS_SEC_SIZE_EN);
  	if (err)
  		goto error_dma_mode_off;
-@@ -733,11 +736,10 @@ static ssize_t airoha_snand_dirmap_read(
+@@ -702,11 +705,10 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
  	 *        = NFI_SNF_MISC_CTL2.read_data_byte_number =
  	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
  	 */
--	val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+-	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
 -	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi,
+ 	err = regmap_update_bits(priv->regmap_nfi,
  				 REG_SPI_NFI_SNF_MISC_CTL2,
 -				 SPI_NFI_READ_DATA_BYTE_NUM, val);
 +				 SPI_NFI_READ_DATA_BYTE_NUM,
@@ -90,26 +85,24 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  	if (err)
  		goto error_dma_unmap;
  
-@@ -826,10 +828,13 @@ static ssize_t airoha_snand_dirmap_write
- 	struct airoha_snand_ctrl *as_ctrl;
+@@ -795,8 +797,11 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ 	u8 *txrx_buf = priv->txrx_buf;
  	dma_addr_t dma_addr;
  	u32 wr_mode, val, opcode;
 +	size_t bytes;
  	int err;
  
- 	as_ctrl = spi_controller_get_devdata(spi->controller);
- 
-+	bytes = as_ctrl->nfi_cfg.sec_num * as_ctrl->nfi_cfg.sec_size;
++	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
 +
  	opcode = desc->info.op_tmpl.cmd.opcode;
  	switch (opcode) {
  	case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
-@@ -880,18 +885,17 @@ static ssize_t airoha_snand_dirmap_write
+@@ -847,18 +852,17 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
  		goto error_dma_mode_off;
  
  	/* Set number of sector will be written */
--	val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
+-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
 -				 SPI_NFI_SEC_NUM, val);
 +				 SPI_NFI_SEC_NUM,
 +				 FIELD_PREP(SPI_NFI_SEC_NUM, 1));
@@ -117,8 +110,8 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  		goto error_dma_mode_off;
  
  	/* Set custom sector size */
--	val = as_ctrl->nfi_cfg.sec_size;
- 	err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+-	val = priv->nfi_cfg.sec_size;
+ 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
  				 SPI_NFI_CUS_SEC_SIZE |
  				 SPI_NFI_CUS_SEC_SIZE_EN,
 -				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
@@ -126,13 +119,13 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
  				 SPI_NFI_CUS_SEC_SIZE_EN);
  	if (err)
  		goto error_dma_mode_off;
-@@ -916,11 +920,10 @@ static ssize_t airoha_snand_dirmap_write
+@@ -880,11 +884,10 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
  	 *        = NFI_SNF_MISC_CTL2.write_data_byte_number =
  	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
  	 */
--	val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
+-	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
 -	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
- 	err = regmap_update_bits(as_ctrl->regmap_nfi,
+ 	err = regmap_update_bits(priv->regmap_nfi,
  				 REG_SPI_NFI_SNF_MISC_CTL2,
 -				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
 +				 SPI_NFI_PROG_LOAD_BYTE_NUM,

package/boot/uboot-airoha/patches/210-spi-airoha-avoid-usage-of-flash-specific-parameters.patch

@@ -0,0 +1,170 @@
+From f015b0211a36bf818023c82ab44644631987d23c Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Thu, 14 Aug 2025 23:56:24 +0300
+Subject: [PATCH 4/4] spi: airoha: avoid usage of flash specific parameters
+
+The spinand driver do 3 type of dirmap requests:
+ * read/write whole flash page without oob
+   (offs = 0, len = page_size)
+ * read/write whole flash page including oob
+   (offs = 0, len = page_size + oob_size)
+ * read/write oob area only
+   (offs = page_size, len = oob_size)
+
+The trick is:
+ * read/write a single "sector"
+ * set a custom sector size equal to offs + len. It's a bit safer to
+   round up "sector size" value 64.
+ * set the transfer length equal to custom sector size
+
+And it works!
+
+Thus we can find all data directly from dirmap request, so flash specific
+parameters is not needed anymore. Also
+ * airoha_snand_nfi_config(),
+ * airoha_snand_nfi_setup()
+functions becomes unnecessary.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/spi/airoha_snfi_spi.c | 94 ++---------------------------------
+ 1 file changed, 4 insertions(+), 90 deletions(-)
+
+--- a/drivers/spi/airoha_snfi_spi.c
++++ b/drivers/spi/airoha_snfi_spi.c
+@@ -218,13 +218,6 @@ struct airoha_snand_priv {
+ 	struct regmap *regmap_nfi;
+ 	struct clk *spi_clk;
+ 
+-	struct {
+-		size_t page_size;
+-		size_t sec_size;
+-		u8 sec_num;
+-		u8 spare_size;
+-	} nfi_cfg;
+-
+ 	u8 *txrx_buf;
+ };
+ 
+@@ -486,55 +479,6 @@ static int airoha_snand_nfi_init(struct airoha_snand_priv *priv)
+ 				  SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
+ }
+ 
+-static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
+-{
+-	int err;
+-	u32 val;
+-
+-	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
+-			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
+-	if (err)
+-		return err;
+-
+-	/* auto FDM */
+-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+-				SPI_NFI_AUTO_FDM_EN);
+-	if (err)
+-		return err;
+-
+-	/* HW ECC */
+-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+-				SPI_NFI_HW_ECC_EN);
+-	if (err)
+-		return err;
+-
+-	/* DMA Burst */
+-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
+-			      SPI_NFI_DMA_BURST_EN);
+-	if (err)
+-		return err;
+-
+-	/* sec num */
+-	val = FIELD_PREP(SPI_NFI_SEC_NUM, 1);
+-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
+-				 SPI_NFI_SEC_NUM, val);
+-	if (err)
+-		return err;
+-
+-	/* enable cust sec size */
+-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
+-			      SPI_NFI_CUS_SEC_SIZE_EN);
+-	if (err)
+-		return err;
+-
+-	/* set cust sec size */
+-	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE,
+-			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
+-	return regmap_update_bits(priv->regmap_nfi,
+-				  REG_SPI_NFI_SECCUS_SIZE,
+-				  SPI_NFI_CUS_SEC_SIZE, val);
+-}
+-
+ static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
+ {
+ 	if (op->addr.nbytes != 2)
+@@ -614,7 +558,8 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
+ 	size_t bytes;
+ 	int err;
+ 
+-	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
++	/* minimum oob size is 64 */
++	bytes = round_up(offs + len, 64);
+ 
+ 	/*
+ 	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
+@@ -800,7 +745,8 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
+ 	size_t bytes;
+ 	int err;
+ 
+-	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
++	/* minimum oob size is 64 */
++	bytes = round_up(offs + len, 64);
+ 
+ 	opcode = desc->info.op_tmpl.cmd.opcode;
+ 	switch (opcode) {
+@@ -1089,37 +1035,6 @@ static int airoha_snand_nfi_set_mode(struct udevice *bus, uint mode)
+ 	return 0;
+ }
+ 
+-static int airoha_snand_nfi_setup(struct spi_slave *slave,
+-				  const struct spinand_info *spinand_info)
+-{
+-	struct udevice *bus = slave->dev->parent;
+-	struct airoha_snand_priv *priv;
+-	u32 sec_size, sec_num;
+-	int pagesize, oobsize;
+-
+-	priv = dev_get_priv(bus);
+-
+-	pagesize = spinand_info->memorg.pagesize;
+-	oobsize = spinand_info->memorg.oobsize;
+-
+-	if (pagesize == 2 * 1024)
+-		sec_num = 4;
+-	else if (pagesize == 4 * 1024)
+-		sec_num = 8;
+-	else
+-		sec_num = 1;
+-
+-	sec_size = (pagesize + oobsize) / sec_num;
+-
+-	/* init default value */
+-	priv->nfi_cfg.sec_size = sec_size;
+-	priv->nfi_cfg.sec_num = sec_num;
+-	priv->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
+-	priv->nfi_cfg.spare_size = 16;
+-
+-	return airoha_snand_nfi_config(priv);
+-}
+-
+ static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
+ 	.supports_op = airoha_snand_supports_op,
+ 	.exec_op = airoha_snand_exec_op,
+@@ -1132,7 +1047,6 @@ static const struct dm_spi_ops airoha_snfi_spi_ops = {
+ 	.mem_ops = &airoha_snand_mem_ops,
+ 	.set_speed = airoha_snand_nfi_set_speed,
+ 	.set_mode = airoha_snand_nfi_set_mode,
+-	.setup_for_spinand = airoha_snand_nfi_setup,
+ };
+ 
+ static const struct udevice_id airoha_snand_ids[] = {

package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch

@@ -1,7 +1,7 @@
-From 4791e708e2976c3e8bf4e69c92ccd6f1103e8f1f Mon Sep 17 00:00:00 2001
+From 0ee8053a17e6f4d6dbde0828e775309cba38c171 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Tue, 29 Apr 2025 13:06:59 +0200
-Subject: [PATCH 01/24] airoha: add support for Airoha AN7583 SoC
+Subject: [PATCH 1/3] airoha: add support for Airoha AN7583 SoC
 
 Add support for Airoha AN7583 SoC. This adds the Kconfig and Makefile
 entry for the SoC, DTSI and initial config for it. Also add the code for
@@ -19,9 +19,9 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  board/airoha/an7583/MAINTAINERS      |   5 +
  board/airoha/an7583/Makefile         |   3 +
  board/airoha/an7583/an7583_rfb.c     |  16 ++
- configs/an7583_evb_defconfig         |  80 ++++++
+ configs/an7583_evb_defconfig         |  81 ++++++
  include/configs/an7583.h             |  19 ++
- 11 files changed, 642 insertions(+)
+ 11 files changed, 643 insertions(+)
  create mode 100644 arch/arm/dts/an7583-evb.dts
  create mode 100644 arch/arm/dts/an7583.dtsi
  create mode 100644 arch/arm/mach-airoha/an7583/Makefile
@@ -32,9 +32,6 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  create mode 100644 configs/an7583_evb_defconfig
  create mode 100644 include/configs/an7583.h
 
-diff --git a/arch/arm/dts/an7583-evb.dts b/arch/arm/dts/an7583-evb.dts
-new file mode 100644
-index 00000000000..d02cd194e8a
 --- /dev/null
 +++ b/arch/arm/dts/an7583-evb.dts
 @@ -0,0 +1,67 @@
@@ -105,9 +102,6 @@ index 00000000000..d02cd194e8a
 +&snfi {
 +	status = "okay";
 +};
-diff --git a/arch/arm/dts/an7583.dtsi b/arch/arm/dts/an7583.dtsi
-new file mode 100644
-index 00000000000..e1fda15ba37
 --- /dev/null
 +++ b/arch/arm/dts/an7583.dtsi
 @@ -0,0 +1,387 @@
@@ -248,7 +242,7 @@ index 00000000000..e1fda15ba37
 +			reg = <0x0 0x1fbe3400 0x0 0xff>;
 +		};
 +
-+		system-controller@1fb00000 {
++		system-controller@1fa20000 {
 +			compatible = "syscon", "simple-mfd";
 +			reg = <0x0 0x1fb00000 0x0 0x970>;
 +
@@ -498,11 +492,9 @@ index 00000000000..e1fda15ba37
 +		};
 +	};
 +};
-diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig
-index b9cd0a413e1..2d74e3ce902 100644
 --- a/arch/arm/mach-airoha/Kconfig
 +++ b/arch/arm/mach-airoha/Kconfig
-@@ -28,19 +28,33 @@ config TARGET_AN7581
+@@ -17,16 +17,30 @@ config TARGET_AN7581
  	  Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
  	  I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
  
@@ -520,43 +512,32 @@ index b9cd0a413e1..2d74e3ce902 100644
  endchoice
  
  config SYS_SOC
- 	default "en7523" if TARGET_EN7523
  	default "an7581" if TARGET_AN7581
 +	default "an7583" if TARGET_AN7583
  
  config SYS_BOARD
- 	default "en7523" if TARGET_EN7523
  	default "an7581" if TARGET_AN7581
 +	default "an7583" if TARGET_AN7583
  
  config SYS_CONFIG_NAME
- 	default "en7523" if TARGET_EN7523
  	default "an7581" if TARGET_AN7581
 +	default "an7583" if TARGET_AN7583
  
  endif
  
-diff --git a/arch/arm/mach-airoha/Makefile b/arch/arm/mach-airoha/Makefile
-index 91395b8a850..51d82ea3e21 100644
 --- a/arch/arm/mach-airoha/Makefile
 +++ b/arch/arm/mach-airoha/Makefile
-@@ -4,3 +4,4 @@ obj-y	+= cpu.o
+@@ -3,3 +3,4 @@
+ obj-y	+= cpu.o
  
- obj-$(CONFIG_TARGET_EN7523) += en7523/
  obj-$(CONFIG_TARGET_AN7581) += an7581/
 +obj-$(CONFIG_TARGET_AN7583) += an7583/
-diff --git a/arch/arm/mach-airoha/an7583/Makefile b/arch/arm/mach-airoha/an7583/Makefile
-new file mode 100644
-index 00000000000..886ab7e4eb9
 --- /dev/null
 +++ b/arch/arm/mach-airoha/an7583/Makefile
 @@ -0,0 +1,3 @@
 +# SPDX-License-Identifier:	GPL-2.0
 +
 +obj-y += init.o
-diff --git a/arch/arm/mach-airoha/an7583/init.c b/arch/arm/mach-airoha/an7583/init.c
-new file mode 100644
-index 00000000000..77c29290331
 --- /dev/null
 +++ b/arch/arm/mach-airoha/an7583/init.c
 @@ -0,0 +1,47 @@
@@ -607,9 +588,6 @@ index 00000000000..77c29290331
 +	}
 +};
 +struct mm_region *mem_map = an7583_mem_map;
-diff --git a/board/airoha/an7583/MAINTAINERS b/board/airoha/an7583/MAINTAINERS
-new file mode 100644
-index 00000000000..71ee542a8bc
 --- /dev/null
 +++ b/board/airoha/an7583/MAINTAINERS
 @@ -0,0 +1,5 @@
@@ -618,18 +596,12 @@ index 00000000000..71ee542a8bc
 +S:	Maintained
 +N:      airoha
 +N:      an7583
-diff --git a/board/airoha/an7583/Makefile b/board/airoha/an7583/Makefile
-new file mode 100644
-index 00000000000..d582684d1f7
 --- /dev/null
 +++ b/board/airoha/an7583/Makefile
 @@ -0,0 +1,3 @@
 +# SPDX-License-Identifier:	GPL-2.0
 +
 +obj-y	+= an7583_rfb.o
-diff --git a/board/airoha/an7583/an7583_rfb.c b/board/airoha/an7583/an7583_rfb.c
-new file mode 100644
-index 00000000000..aa73679d929
 --- /dev/null
 +++ b/board/airoha/an7583/an7583_rfb.c
 @@ -0,0 +1,16 @@
@@ -649,12 +621,9 @@ index 00000000000..aa73679d929
 +
 +	return 0;
 +}
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-new file mode 100644
-index 00000000000..d1893fff398
 --- /dev/null
 +++ b/configs/an7583_evb_defconfig
-@@ -0,0 +1,80 @@
+@@ -0,0 +1,81 @@
 +CONFIG_ARM=y
 +CONFIG_ARCH_AIROHA=y
 +CONFIG_TARGET_AN7583=y
@@ -665,6 +634,7 @@ index 00000000000..d1893fff398
 +CONFIG_ENV_OFFSET=0x7c000
 +CONFIG_DM_GPIO=y
 +CONFIG_DEFAULT_DEVICE_TREE="an7583-evb"
++CONFIG_DM_RESET=y
 +CONFIG_SYS_LOAD_ADDR=0x81800000
 +CONFIG_BUILD_TARGET="u-boot.bin"
 +# CONFIG_EFI_LOADER is not set
@@ -700,7 +670,6 @@ index 00000000000..d1893fff398
 +CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 +CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_SYS_RX_ETH_BUFFER=8
 +CONFIG_REGMAP=y
 +CONFIG_SYSCON=y
 +CONFIG_CLK=y
@@ -708,7 +677,6 @@ index 00000000000..d1893fff398
 +CONFIG_LED=y
 +CONFIG_LED_GPIO=y
 +CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MMC_MTK=y
 +CONFIG_MTD=y
 +CONFIG_DM_MTD=y
 +CONFIG_MTD_SPI_NAND=y
@@ -721,7 +689,7 @@ index 00000000000..d1893fff398
 +CONFIG_SPI_FLASH_STMICRO=y
 +CONFIG_SPI_FLASH_WINBOND=y
 +CONFIG_SPI_FLASH_MTD=y
-+CONFIG_AIROHA_ETH=y
++CONFIG_PHYLIB=y
 +CONFIG_PHY=y
 +CONFIG_PINCTRL=y
 +CONFIG_PINCONF=y
@@ -733,11 +701,10 @@ index 00000000000..d1893fff398
 +CONFIG_SYS_NS16550=y
 +CONFIG_SPI=y
 +CONFIG_DM_SPI=y
-+CONFIG_AIROHA_SNFI_SPI=y
 +CONFIG_SHA512=y
-diff --git a/include/configs/an7583.h b/include/configs/an7583.h
-new file mode 100644
-index 00000000000..c865afea1a2
++CONFIG_AIROHA_ETH=y
++CONFIG_MMC_MTK=y
++CONFIG_AIROHA_SNFI_SPI=y
 --- /dev/null
 +++ b/include/configs/an7583.h
 @@ -0,0 +1,19 @@
@@ -760,6 +727,3 @@ index 00000000000..c865afea1a2
 +#define CFG_SYS_SDRAM_BASE		0x80000000
 +
 +#endif
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/301-arm-an7583-sync-init-code-with-an7581.patch

@@ -1,83 +0,0 @@
-From 2ed022130bb42e3c419a4943115144259fa3b4b6 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Fri, 17 Oct 2025 02:53:28 +0300
-Subject: [PATCH 02/24] arm/an7583: sync init code with an7581
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- arch/arm/mach-airoha/an7583/init.c | 31 ++++++++++++++++++++++++------
- 1 file changed, 25 insertions(+), 6 deletions(-)
-
-diff --git a/arch/arm/mach-airoha/an7583/init.c b/arch/arm/mach-airoha/an7583/init.c
-index 77c29290331..4cf7f8caf85 100644
---- a/arch/arm/mach-airoha/an7583/init.c
-+++ b/arch/arm/mach-airoha/an7583/init.c
-@@ -2,9 +2,14 @@
- 
- #include <fdtdec.h>
- #include <init.h>
-+#include <linux/sizes.h>
-+#include <sysreset.h>
- #include <asm/armv8/mmu.h>
-+#include <asm/global_data.h>
- #include <asm/system.h>
- 
-+DECLARE_GLOBAL_DATA_PTR;
-+
- int print_cpuinfo(void)
- {
- 	printf("CPU:   Airoha AN7583\n");
-@@ -18,30 +23,44 @@ int dram_init(void)
- 
- int dram_init_banksize(void)
- {
--	return fdtdec_setup_memory_banksize();
-+	gd->bd->bi_dram[0].start = gd->ram_base;
-+	gd->bd->bi_dram[0].size = get_effective_memsize();
-+
-+	if (gd->ram_size > SZ_2G) {
-+		gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G;
-+		gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
-+	}
-+
-+	return 0;
- }
- 
--void reset_cpu(ulong addr)
-+void reset_cpu(void)
- {
- 	psci_system_reset();
- }
- 
- static struct mm_region an7583_mem_map[] = {
- 	{
--		/* DDR */
-+		/* DDR, 32-bit area */
- 		.virt = 0x80000000UL,
- 		.phys = 0x80000000UL,
--		.size = 0x80000000UL,
-+		.size = SZ_2G,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+	}, {
-+		/* DDR, 64-bit area */
-+		.virt = 0x100000000UL,
-+		.phys = 0x100000000UL,
-+		.size = SZ_4G + SZ_2G,
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
- 	}, {
- 		.virt = 0x00000000UL,
- 		.phys = 0x00000000UL,
--		.size = 0x20000000UL,
-+		.size = 0x40000000UL,
- 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- 			 PTE_BLOCK_NON_SHARE |
- 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
- 	}, {
--		0,
-+		/* List terminator */
- 	}
- };
- struct mm_region *mem_map = an7583_mem_map;
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/301-clk-airoha-add-support-for-Airoha-AN7583-SoC-clock.patch

@@ -1,29 +1,19 @@
-From c2bc25eaebdaf865c52418ff89ece3eb6aded616 Mon Sep 17 00:00:00 2001
+From 62ab067847b30d73d4f661bdc99e9f32ff03f338 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Tue, 29 Apr 2025 13:19:11 +0200
-Subject: [PATCH 05/24] clk: airoha: add support for Airoha AN7583 SoC clock
+Subject: [PATCH] clk: airoha: add support for Airoha AN7583 SoC clock
 
 Add support for Airoha AN7583 SoC clock that implement more base values
 for clocks compared to AN7581.
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
- drivers/clk/airoha/clk-airoha.c | 158 ++++++++++++++++++++++++++++++++
- 1 file changed, 158 insertions(+)
+ drivers/clk/airoha/clk-airoha.c | 131 ++++++++++++++++++++++++++++++++
+ 1 file changed, 131 insertions(+)
 
-diff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c
-index 49dbca82135..68dca6ab202 100644
 --- a/drivers/clk/airoha/clk-airoha.c
 +++ b/drivers/clk/airoha/clk-airoha.c
-@@ -36,6 +36,7 @@
- 
- #define EN7523_MAX_CLKS			8
- #define EN7581_MAX_CLKS			9
-+#define EN7583_MAX_CLKS			11
- 
- struct airoha_clk_desc {
- 	int id;
-@@ -78,6 +79,14 @@ static const u32 bus7581_base[] = { 600000000, 540000000 };
+@@ -73,6 +73,14 @@ static const u32 bus7581_base[] = { 6000
  static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
  static const u32 crypto_base[] = { 540000000, 480000000 };
  static const u32 emmc7581_base[] = { 200000000, 150000000 };
@@ -31,18 +21,18 @@ index 49dbca82135..68dca6ab202 100644
 +static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
 +static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
 +static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
-+static const u32 spi7583_base[] = { 400000000, 12500000 };
++static const u32 spi7583_base[] = { 100000000, 12500000 };
 +static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
 +static const u32 crypto7583_base[] = { 540672000, 400000000 };
 +static const u32 emmc7583_base[] = { 150000000, 200000000 };
  
- static const struct airoha_clk_desc en7523_base_clks[EN7523_MAX_CLKS] = {
+ static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = {
  	[EN7523_CLK_GSW] = {
-@@ -293,6 +302,147 @@ static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = {
+@@ -186,6 +194,121 @@ static const struct airoha_clk_desc en75
  	}
  };
  
-+static const struct airoha_clk_desc an7583_base_clks[EN7583_MAX_CLKS] = {
++static const struct airoha_clk_desc an7583_base_clks[EN7581_MAX_CLKS] = {
 +	[EN7523_CLK_GSW] = {
 +		.id = EN7523_CLK_GSW,
 +		.name = "gsw",
@@ -94,7 +84,7 @@ index 49dbca82135..68dca6ab202 100644
 +
 +		.base_reg = REG_SPI_CLK_FREQ_SEL,
 +		.base_bits = 1,
-+		.base_shift = 1,
++		.base_shift = 0,
 +		.base_values = slic_base,
 +		.n_base_values = ARRAY_SIZE(slic_base),
 +
@@ -110,7 +100,7 @@ index 49dbca82135..68dca6ab202 100644
 +
 +		.base_reg = REG_SPI_CLK_FREQ_SEL,
 +		.base_bits = 1,
-+		.base_shift = 0,
++		.base_shift = 1,
 +		.base_values = spi7583_base,
 +		.n_base_values = ARRAY_SIZE(spi7583_base),
 +
@@ -154,39 +144,13 @@ index 49dbca82135..68dca6ab202 100644
 +		.base_shift = 13,
 +		.base_values = emmc7583_base,
 +		.n_base_values = ARRAY_SIZE(emmc7583_base),
-+	},
-+	[AN7583_CLK_MDIO0] = {
-+		.id = AN7583_CLK_MDIO0,
-+		.name = "mdio0",
-+
-+		.base_reg = REG_CRYPTO_CLKSRC2,
-+
-+		.base_value = 25000000,
-+
-+		.div_bits = 4,
-+		.div_shift = 15,
-+		.div_step = 1,
-+		.div_offset = 1,
-+	},
-+	[AN7583_CLK_MDIO1] = {
-+		.id = AN7583_CLK_MDIO1,
-+		.name = "mdio1",
-+
-+		.base_reg = REG_CRYPTO_CLKSRC2,
-+
-+		.base_value = 25000000,
-+
-+		.div_bits = 4,
-+		.div_shift = 19,
-+		.div_step = 1,
-+		.div_offset = 1,
 +	}
 +};
 +
  static u32 airoha_clk_get_base_rate(const struct airoha_clk_desc *desc, u32 val)
  {
  	if (!desc->base_bits)
-@@ -542,6 +692,11 @@ static const struct airoha_clk_soc_data en7581_data = {
+@@ -436,10 +559,18 @@ static const struct airoha_clk_soc_data
  	.descs = en7581_base_clks,
  };
  
@@ -196,9 +160,6 @@ index 49dbca82135..68dca6ab202 100644
 +};
 +
  static const struct udevice_id airoha_clk_ids[] = {
- 	{ .compatible = "airoha,en7523-scu",
- 	  .data = (ulong)&en7523_data,
-@@ -549,6 +704,9 @@ static const struct udevice_id airoha_clk_ids[] = {
  	{ .compatible = "airoha,en7581-scu",
  	  .data = (ulong)&en7581_data,
  	},
@@ -208,6 +169,3 @@ index 49dbca82135..68dca6ab202 100644
  	{ }
  };
  
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/302-reset-airoha-convert-to-regmap-API.patch

@@ -0,0 +1,90 @@
+From 7daf0565460e548eb766a0bcc171c34e02dd6eba Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 19 May 2025 14:22:55 +0200
+Subject: [PATCH 3/6] reset: airoha: convert to regmap API
+
+In preparation for support for Airoha AN7583, convert the driver to
+regmap API. This is needed as Airoha AN7583 will use syscon to access
+reset registers.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/reset/reset-airoha.c | 35 ++++++++++++++++++-----------------
+ 1 file changed, 18 insertions(+), 17 deletions(-)
+
+--- a/drivers/reset/reset-airoha.c
++++ b/drivers/reset/reset-airoha.c
+@@ -10,6 +10,7 @@
+ #include <dm.h>
+ #include <linux/io.h>
+ #include <reset-uclass.h>
++#include <regmap.h>
+ 
+ #include <dt-bindings/reset/airoha,en7581-reset.h>
+ 
+@@ -21,7 +22,7 @@
+ struct airoha_reset_priv {
+ 	const u16 *bank_ofs;
+ 	const u16 *idx_map;
+-	void __iomem *base;
++	struct regmap *map;
+ };
+ 
+ static const u16 en7581_rst_ofs[] = {
+@@ -90,17 +91,11 @@ static const u16 en7581_rst_map[] = {
+ static int airoha_reset_update(struct airoha_reset_priv *priv,
+ 			       unsigned long id, bool assert)
+ {
+-	void __iomem *addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
+-	u32 val;
+-
+-	val = readl(addr);
+-	if (assert)
+-		val |= BIT(id % RST_NR_PER_BANK);
+-	else
+-		val &= ~BIT(id % RST_NR_PER_BANK);
+-	writel(val, addr);
++	u16 offset = priv->bank_ofs[id / RST_NR_PER_BANK];
+ 
+-	return 0;
++	return regmap_update_bits(priv->map, offset,
++				  BIT(id % RST_NR_PER_BANK),
++				  assert ? BIT(id % RST_NR_PER_BANK) : 0);
+ }
+ 
+ static int airoha_reset_assert(struct reset_ctl *reset_ctl)
+@@ -123,11 +118,16 @@ static int airoha_reset_status(struct re
+ {
+ 	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ 	int id = reset_ctl->id;
+-	void __iomem *addr;
++	u16 offset;
++	u32 val;
++	int ret;
+ 
+-	addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
++	offset = priv->bank_ofs[id / RST_NR_PER_BANK];
++	ret = regmap_read(priv->map, offset, &val);
++	if (ret)
++		return ret;
+ 
+-	return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
++	return !!(val & BIT(id % RST_NR_PER_BANK));
+ }
+ 
+ static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
+@@ -153,10 +153,11 @@ static struct reset_ops airoha_reset_ops
+ static int airoha_reset_probe(struct udevice *dev)
+ {
+ 	struct airoha_reset_priv *priv = dev_get_priv(dev);
++	int ret;
+ 
+-	priv->base = dev_remap_addr(dev);
+-	if (!priv->base)
+-		return -ENOMEM;
++	ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
++	if (ret)
++		return ret;
+ 
+ 	priv->bank_ofs = en7581_rst_ofs;
+ 	priv->idx_map = en7581_rst_map;

package/boot/uboot-airoha/patches/303-arm-airoha-introduce-AN7583-helpers-to-get-SCU-and-C.patch

@@ -1,83 +0,0 @@
-From 59e3fa0d74fd36ba61a2b4e63eb6faf31b4e2396 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Fri, 31 Oct 2025 00:42:08 +0300
-Subject: [PATCH 03/24] arm: airoha: introduce AN7583 helpers to get SCU and
- CHIP_SCU regmaps
-
-We need access SCU and CHIP_SCU regmaps in several places (clk-airoha,
-reset-airoha, airoha_eth). Unfortunately these regmaps can't be easily
-retrieved with a common code, because of different Airoha SoCs uses
-a different dts structure.
-
-To make life easy we can write a commonly named SoC specific helpers
-for these tasks. This patch implements helpers for Airoha AN7583 SoC.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- arch/arm/include/asm/arch-an7583         |  1 +
- arch/arm/mach-airoha/an7583/Makefile     |  1 +
- arch/arm/mach-airoha/an7583/scu-regmap.c | 34 ++++++++++++++++++++++++
- 3 files changed, 36 insertions(+)
- create mode 120000 arch/arm/include/asm/arch-an7583
- create mode 100644 arch/arm/mach-airoha/an7583/scu-regmap.c
-
-diff --git a/arch/arm/include/asm/arch-an7583 b/arch/arm/include/asm/arch-an7583
-new file mode 120000
-index 00000000000..d2317ed3bc3
---- /dev/null
-+++ b/arch/arm/include/asm/arch-an7583
-@@ -0,0 +1 @@
-+arch-airoha
-\ No newline at end of file
-diff --git a/arch/arm/mach-airoha/an7583/Makefile b/arch/arm/mach-airoha/an7583/Makefile
-index 886ab7e4eb9..51f978aa101 100644
---- a/arch/arm/mach-airoha/an7583/Makefile
-+++ b/arch/arm/mach-airoha/an7583/Makefile
-@@ -1,3 +1,4 @@
- # SPDX-License-Identifier:	GPL-2.0
- 
- obj-y += init.o
-+obj-y += scu-regmap.o
-diff --git a/arch/arm/mach-airoha/an7583/scu-regmap.c b/arch/arm/mach-airoha/an7583/scu-regmap.c
-new file mode 100644
-index 00000000000..96f3564eec0
---- /dev/null
-+++ b/arch/arm/mach-airoha/an7583/scu-regmap.c
-@@ -0,0 +1,34 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-+ */
-+
-+#include <syscon.h>
-+#include <linux/err.h>
-+#include <asm/arch/scu-regmap.h>
-+
-+struct regmap *airoha_get_scu_regmap(void)
-+{
-+	ofnode node;
-+
-+	node = ofnode_by_compatible(ofnode_null(), "airoha,an7583-scu");
-+	if (!ofnode_valid(node))
-+		return ERR_PTR(-EINVAL);
-+
-+	node = ofnode_get_parent(node);
-+	if (!ofnode_valid(node))
-+		return ERR_PTR(-EINVAL);
-+
-+	return syscon_node_to_regmap(node);
-+}
-+
-+struct regmap *airoha_get_chip_scu_regmap(void)
-+{
-+	ofnode node;
-+
-+	node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-chip-scu");
-+	if (!ofnode_valid(node))
-+		return ERR_PTR(-EINVAL);
-+
-+	return syscon_node_to_regmap(node);
-+}
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/303-reset-airoha-Add-support-for-Airoha-AN7583-reset.patch

@@ -1,7 +1,7 @@
-From 6b54d65d6b247d06d94c28c6df92ed5b45d7468a Mon Sep 17 00:00:00 2001
+From 23031ad51d55361be507b83307f55995e0204188 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Tue, 29 Apr 2025 13:33:35 +0200
-Subject: [PATCH 06/24] reset: airoha: Add support for Airoha AN7583 reset
+Subject: [PATCH 4/6] reset: airoha: Add support for Airoha AN7583 reset
 
 Adapt the Airoha reset driver to support Airoha AN7583 node structure.
 In AN7583 the register is exposed by the parent syscon hence a different
@@ -10,24 +10,33 @@ a dedicated table is needed.
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
- drivers/reset/reset-airoha.c                  | 60 ++++++++++++++++++
- .../dt-bindings/reset/airoha,an7583-reset.h   | 62 +++++++++++++++++++
- 2 files changed, 122 insertions(+)
+ drivers/reset/reset-airoha.c                  | 94 ++++++++++++++++++-
+ .../dt-bindings/reset/airoha,an7583-reset.h   | 61 ++++++++++++
+ 2 files changed, 153 insertions(+), 2 deletions(-)
  create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
 
-diff --git a/drivers/reset/reset-airoha.c b/drivers/reset/reset-airoha.c
-index ef8c47a067b..071f29b6f22 100644
 --- a/drivers/reset/reset-airoha.c
 +++ b/drivers/reset/reset-airoha.c
-@@ -15,6 +15,7 @@
+@@ -11,8 +11,10 @@
+ #include <linux/io.h>
+ #include <reset-uclass.h>
+ #include <regmap.h>
++#include <syscon.h>
  
- #include <dt-bindings/reset/airoha,en7523-reset.h>
  #include <dt-bindings/reset/airoha,en7581-reset.h>
 +#include <dt-bindings/reset/airoha,an7583-reset.h>
  
  #define RST_NR_PER_BANK			32
  
-@@ -138,6 +139,60 @@ static const u16 en7581_rst_map[] = {
+@@ -22,6 +24,7 @@
+ struct airoha_reset_priv {
+ 	const u16 *bank_ofs;
+ 	const u16 *idx_map;
++	int num_rsts;
+ 	struct regmap *map;
+ };
+ 
+@@ -88,6 +91,59 @@ static const u16 en7581_rst_map[] = {
  	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
  };
  
@@ -48,7 +57,6 @@ index ef8c47a067b..071f29b6f22 100644
 +	[AN7583_DUAL_HSI1_RST]		= 14,
 +	[AN7583_DUAL_HSI0_MAC_RST]	= 16,
 +	[AN7583_DUAL_HSI1_MAC_RST]	= 17,
-+	[AN7583_XPON_XFI_RST]		= 18,
 +	[AN7583_WDMA_RST]		= 19,
 +	[AN7583_WOE0_RST]		= 20,
 +	[AN7583_HSDMA_RST]		= 22,
@@ -88,25 +96,73 @@ index ef8c47a067b..071f29b6f22 100644
  static int airoha_reset_update(struct airoha_reset_priv *priv,
  			       unsigned long id, bool assert)
  {
-@@ -227,6 +282,11 @@ static int airoha_reset_probe(struct udevice *dev)
- 		return reset_init(dev, en7581_rst_map,
- 				  ARRAY_SIZE(en7581_rst_map));
+@@ -135,7 +191,7 @@ static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
+ {
+ 	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
  
-+	if (ofnode_device_is_compatible(dev_ofnode(dev),
-+					"airoha,an7583-scu"))
-+		return reset_init(dev, an7583_rst_map,
-+				 ARRAY_SIZE(an7583_rst_map));
+-	if (args->args[0] >= ARRAY_SIZE(en7581_rst_map))
++	if (args->args[0] >= priv->num_rsts)
+ 		return -EINVAL;
+ 
+ 	reset_ctl->id = priv->idx_map[args->args[0]];
+@@ -150,7 +206,7 @@ static struct reset_ops airoha_reset_ops = {
+ 	.rst_status = airoha_reset_status,
+ };
+ 
+-static int airoha_reset_probe(struct udevice *dev)
++static int an7581_reset_probe(struct udevice *dev)
+ {
+ 	struct airoha_reset_priv *priv = dev_get_priv(dev);
+ 	int ret;
+@@ -161,10 +217,44 @@ static int airoha_reset_probe(struct udevice *dev)
+ 
+ 	priv->bank_ofs = en7581_rst_ofs;
+ 	priv->idx_map = en7581_rst_map;
++	priv->num_rsts = ARRAY_SIZE(en7581_rst_map);
 +
- 	return -ENODEV;
++	return 0;
++}
++
++static int an7583_reset_probe(struct udevice *dev)
++{
++	struct airoha_reset_priv *priv = dev_get_priv(dev);
++	ofnode pnode, scu_node = dev_ofnode(dev);
++
++	pnode = ofnode_get_parent(scu_node);
++	if (!ofnode_valid(pnode))
++		return -EINVAL;
++
++	priv->map = syscon_node_to_regmap(pnode);
++	if (IS_ERR(priv->map))
++		return PTR_ERR(priv->map);
++
++	priv->bank_ofs = en7581_rst_ofs;
++	priv->idx_map = an7583_rst_map;
++	priv->num_rsts = ARRAY_SIZE(an7583_rst_map);
+ 
+ 	return 0;
  }
  
-diff --git a/include/dt-bindings/reset/airoha,an7583-reset.h b/include/dt-bindings/reset/airoha,an7583-reset.h
-new file mode 100644
-index 00000000000..be80d0e0bf5
++static int airoha_reset_probe(struct udevice *dev)
++{
++	if (ofnode_device_is_compatible(dev_ofnode(dev),
++					"airoha,en7581-scu"))
++		return an7581_reset_probe(dev);
++
++	if (ofnode_device_is_compatible(dev_ofnode(dev),
++					"airoha,an7583-scu"))
++		return an7583_reset_probe(dev);
++
++	return -ENODEV;
++}
++
+ U_BOOT_DRIVER(airoha_reset) = {
+ 	.name = "airoha-reset",
+ 	.id = UCLASS_RESET,
 --- /dev/null
 +++ b/include/dt-bindings/reset/airoha,an7583-reset.h
-@@ -0,0 +1,62 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+@@ -0,0 +1,61 @@
++// SPDX-License-Identifier: GPL-2.0-only
 +/*
 + * Copyright (c) 2024 AIROHA Inc
 + * Author: Christian Marangi <ansuelsmth@gmail.com>
@@ -131,43 +187,40 @@ index 00000000000..be80d0e0bf5
 +#define AN7583_DUAL_HSI1_RST		12
 +#define AN7583_DUAL_HSI0_MAC_RST	13
 +#define AN7583_DUAL_HSI1_MAC_RST	14
-+#define AN7583_XPON_XFI_RST     	15
-+#define AN7583_WDMA_RST			16
-+#define AN7583_WOE0_RST			17
-+#define AN7583_HSDMA_RST		18
-+#define AN7583_TDMA_RST			19
-+#define AN7583_EMMC_RST			20
-+#define AN7583_SOE_RST			21
-+#define AN7583_XFP_MAC_RST		22
-+#define AN7583_MDIO0                    23
-+#define AN7583_MDIO1                    24
++#define AN7583_WDMA_RST			15
++#define AN7583_WOE0_RST			16
++#define AN7583_HSDMA_RST		17
++#define AN7583_TDMA_RST			18
++#define AN7583_EMMC_RST			19
++#define AN7583_SOE_RST			20
++#define AN7583_XFP_MAC_RST		21
++#define AN7583_MDIO0    		22
++#define AN7583_MDIO1            	23
 +/* RST_CTRL1 */
-+#define AN7583_PCM1_ZSI_ISI_RST		25
-+#define AN7583_FE_PDMA_RST		26
-+#define AN7583_FE_QDMA_RST		27
-+#define AN7583_PCM_SPIWP_RST		28
-+#define AN7583_CRYPTO_RST		29
-+#define AN7583_TIMER_RST		30
-+#define AN7583_PCM1_RST			31
-+#define AN7583_UART_RST			32
-+#define AN7583_GPIO_RST			33
-+#define AN7583_GDMA_RST			34
-+#define AN7583_I2C_MASTER_RST		35
-+#define AN7583_PCM2_ZSI_ISI_RST		36
-+#define AN7583_SFC_RST			37
-+#define AN7583_UART2_RST		38
-+#define AN7583_GDMP_RST			39
-+#define AN7583_FE_RST			40
-+#define AN7583_USB_HOST_P0_RST		41
-+#define AN7583_GSW_RST			42
-+#define AN7583_SFC2_PCM_RST		43
-+#define AN7583_PCIE0_RST		44
-+#define AN7583_PCIE1_RST		45
-+#define AN7583_CPU_TIMER_RST		46
-+#define AN7583_PCIE_HB_RST		47
-+#define AN7583_XPON_MAC_RST		48
++#define AN7583_PCM1_ZSI_ISI_RST		24
++#define AN7583_FE_PDMA_RST		25
++#define AN7583_FE_QDMA_RST		26
++#define AN7583_PCM_SPIWP_RST		27
++#define AN7583_CRYPTO_RST		28
++#define AN7583_TIMER_RST		29
++#define AN7583_PCM1_RST			30
++#define AN7583_UART_RST			31
++#define AN7583_GPIO_RST			32
++#define AN7583_GDMA_RST			33
++#define AN7583_I2C_MASTER_RST		34
++#define AN7583_PCM2_ZSI_ISI_RST		35
++#define AN7583_SFC_RST			36
++#define AN7583_UART2_RST		37
++#define AN7583_GDMP_RST			38
++#define AN7583_FE_RST			39
++#define AN7583_USB_HOST_P0_RST		40
++#define AN7583_GSW_RST			41
++#define AN7583_SFC2_PCM_RST		42
++#define AN7583_PCIE0_RST		43
++#define AN7583_PCIE1_RST		44
++#define AN7583_CPU_TIMER_RST		45
++#define AN7583_PCIE_HB_RST		46
++#define AN7583_XPON_MAC_RST		47
 +
 +#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */
--- 
-2.51.0
 

package/boot/uboot-airoha/patches/304-dt-bindings-clock-airoha-Document-support-for-AN7583.patch

@@ -1,32 +0,0 @@
-From 0faf0f239a145129063a1a2c798fc97c362cc98d Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 30 Sep 2025 22:15:15 +0200
-Subject: [PATCH 04/24] dt-bindings: clock: airoha: Document support for AN7583
- clock
-
-Document support for Airoha AN7583 clock. This is based on the EN7523
-clock schema with the new requirement of the "airoha,chip-scu"
-(previously optional for EN7581).
-
-Add additional binding for additional clock and reset lines.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- dts/upstream/include/dt-bindings/clock/en7523-clk.h | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/dts/upstream/include/dt-bindings/clock/en7523-clk.h b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
-index edfa64045f5..0fbbcb7b1b2 100644
---- a/dts/upstream/include/dt-bindings/clock/en7523-clk.h
-+++ b/dts/upstream/include/dt-bindings/clock/en7523-clk.h
-@@ -14,4 +14,7 @@
- 
- #define EN7581_CLK_EMMC		8
- 
-+#define AN7583_CLK_MDIO0	9
-+#define AN7583_CLK_MDIO1	10
-+
- #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/304-net-airoha-add-support-for-Airoha-AN7583.patch

@@ -1,7 +1,7 @@
-From fca7240fd0ea0b30d8b6eda68eec67d84d48f15d Mon Sep 17 00:00:00 2001
+From dfdc7309ba22f6a6b6c581acfe95a222108bd760 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Mon, 19 May 2025 14:29:53 +0200
-Subject: [PATCH 07/24] net: airoha: add support for Airoha AN7583
+Subject: [PATCH] net: airoha: add support for Airoha AN7583
 
 Add support for Ethernet controller present in Airoha AN7583. This
 follow the same implementation of Airoha AN7581 with the only difference
@@ -16,11 +16,9 @@ enable BMCR_PDOWN by default and tweak to GEPHY_CONN_CFG is also needed.
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
- drivers/net/airoha_eth.c | 91 ++++++++++++++++++++++++++++++++++++++++
- 1 file changed, 91 insertions(+)
+ drivers/net/airoha_eth.c | 168 ++++++++++++++++++++++++++++++++++-----
+ 1 file changed, 147 insertions(+), 21 deletions(-)
 
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index 3234d875887..75af93f182d 100644
 --- a/drivers/net/airoha_eth.c
 +++ b/drivers/net/airoha_eth.c
 @@ -20,6 +20,7 @@
@@ -29,9 +27,9 @@ index 3234d875887..75af93f182d 100644
  #include <linux/iopoll.h>
 +#include <linux/mii.h>
  #include <linux/time.h>
- #include <asm/arch/scu-regmap.h>
  
-@@ -28,6 +29,11 @@
+ #define AIROHA_MAX_NUM_GDM_PORTS	1
+@@ -27,6 +28,11 @@
  #define AIROHA_MAX_NUM_RSTS		3
  #define AIROHA_MAX_NUM_XSI_RSTS		4
  
@@ -43,7 +41,7 @@ index 3234d875887..75af93f182d 100644
  #define AIROHA_MAX_PACKET_SIZE		2048
  #define AIROHA_NUM_TX_RING		1
  #define AIROHA_NUM_RX_RING		1
-@@ -78,6 +84,19 @@
+@@ -77,6 +83,19 @@
  #define   SWITCH_PHY_PRE_EN		BIT(15)
  #define   SWITCH_PHY_END_ADDR		GENMASK(12, 8)
  #define   SWITCH_PHY_ST_ADDR		GENMASK(4, 0)
@@ -63,10 +61,24 @@ index 3234d875887..75af93f182d 100644
  
  /* FE */
  #define PSE_BASE			0x0100
-@@ -332,6 +351,12 @@ static const char * const en7581_xsi_rsts_names[] = {
- 	"xfp-mac",
+@@ -312,6 +331,26 @@ struct airoha_eth {
+ 	struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
  };
  
++struct airoha_eth_soc_data {
++	int num_xsi_rsts;
++	const char * const *xsi_rsts_names;
++	ofnode (*get_scu_node)(struct udevice *dev);
++	const char *switch_compatible;
++};
++
++static const char * const en7581_xsi_rsts_names[] = {
++	"hsi0-mac",
++	"hsi1-mac",
++	"hsi-mac",
++	"xfp-mac",
++};
++
 +static const char * const an7583_xsi_rsts_names[] = {
 +	"hsi0-mac",
 +	"hsi1-mac",
@@ -76,7 +88,7 @@ index 3234d875887..75af93f182d 100644
  static u32 airoha_rr(void __iomem *base, u32 offset)
  {
  	return readl(base + offset);
-@@ -372,8 +397,12 @@ static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
+@@ -352,8 +391,12 @@ static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
  #define airoha_qdma_clear(qdma, offset, val)			\
  	airoha_rmw((qdma)->regs, (offset), (val), 0)
  
@@ -89,7 +101,21 @@ index 3234d875887..75af93f182d 100644
  
  static inline dma_addr_t dma_map_unaligned(void *vaddr, size_t len,
  					   enum dma_data_direction dir)
-@@ -735,6 +764,59 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth)
+@@ -682,10 +725,12 @@ static int airoha_hw_init(struct udevice *dev,
+ 
+ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth)
+ {
++	struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev);
+ 	ofnode switch_node;
+ 	fdt_addr_t addr;
+ 
+-	switch_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-switch");
++	switch_node = ofnode_by_compatible(ofnode_null(),
++					   data->switch_compatible);
+ 	if (!ofnode_valid(switch_node))
+ 		return -EINVAL;
+ 
+@@ -717,17 +762,71 @@ static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth)
  			 FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) |
  			 FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8));
  
@@ -149,29 +175,104 @@ index 3234d875887..75af93f182d 100644
  	return 0;
  }
  
-@@ -994,6 +1076,12 @@ static const struct airoha_eth_soc_data en7581_data = {
- 	.switch_compatible = "airoha,en7581-switch",
- };
+ static int airoha_eth_probe(struct udevice *dev)
+ {
++	struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev);
+ 	struct airoha_eth *eth = dev_get_priv(dev);
+ 	struct regmap *scu_regmap;
+ 	ofnode scu_node;
+-	int ret;
++	int i, ret;
  
+-	scu_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu");
++	scu_node = data->get_scu_node(dev);
+ 	if (!ofnode_valid(scu_node))
+ 		return -EINVAL;
+ 
+@@ -751,11 +850,11 @@ static int airoha_eth_probe(struct udevice *dev)
+ 		return -ENOMEM;
+ 	eth->rsts.count = AIROHA_MAX_NUM_RSTS;
+ 
+-	eth->xsi_rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_XSI_RSTS,
++	eth->xsi_rsts.resets = devm_kcalloc(dev, data->num_xsi_rsts,
+ 					    sizeof(struct reset_ctl), GFP_KERNEL);
+ 	if (!eth->xsi_rsts.resets)
+ 		return -ENOMEM;
+-	eth->xsi_rsts.count = AIROHA_MAX_NUM_XSI_RSTS;
++	eth->xsi_rsts.count = data->num_xsi_rsts;
+ 
+ 	ret = reset_get_by_name(dev, "fe", &eth->rsts.resets[0]);
+ 	if (ret)
+@@ -769,21 +868,12 @@ static int airoha_eth_probe(struct udevice *dev)
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = reset_get_by_name(dev, "hsi0-mac", &eth->xsi_rsts.resets[0]);
+-	if (ret)
+-		return ret;
+-
+-	ret = reset_get_by_name(dev, "hsi1-mac", &eth->xsi_rsts.resets[1]);
+-	if (ret)
+-		return ret;
+-
+-	ret = reset_get_by_name(dev, "hsi-mac", &eth->xsi_rsts.resets[2]);
+-	if (ret)
+-		return ret;
+-
+-	ret = reset_get_by_name(dev, "xfp-mac", &eth->xsi_rsts.resets[3]);
+-	if (ret)
+-		return ret;
++	for (i = 0; i < data->num_xsi_rsts; i++) {
++		ret = reset_get_by_name(dev, data->xsi_rsts_names[i],
++					&eth->xsi_rsts.resets[i]);
++		if (ret)
++			return ret;
++	}
+ 
+ 	ret = airoha_hw_init(dev, eth);
+ 	if (ret)
+@@ -971,8 +1061,43 @@ static int arht_eth_write_hwaddr(struct udevice *dev)
+ 	return 0;
+ }
+ 
++static ofnode en7581_get_scu_node(struct udevice *dev)
++{
++	return ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu");
++}
++
++static ofnode an7583_get_scu_node(struct udevice *dev)
++{
++	ofnode scu_node;
++
++	scu_node = ofnode_by_compatible(ofnode_null(), "airoha,an7583-scu");
++	if (!ofnode_valid(scu_node))
++		return scu_node;
++
++	return ofnode_get_parent(scu_node);
++}
++
++static const struct airoha_eth_soc_data en7581_data = {
++	.xsi_rsts_names = en7581_xsi_rsts_names,
++	.num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names),
++	.get_scu_node = en7581_get_scu_node,
++	.switch_compatible = "airoha,en7581-switch",
++};
++
 +static const struct airoha_eth_soc_data an7583_data = {
 +	.xsi_rsts_names = an7583_xsi_rsts_names,
 +	.num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names),
++	.get_scu_node = an7583_get_scu_node,
 +	.switch_compatible = "airoha,an7583-switch",
 +};
 +
  static const struct udevice_id airoha_eth_ids[] = {
- 	{ .compatible = "airoha,en7523-eth",
- 	  .data = (ulong)&en7523_data,
-@@ -1001,6 +1089,9 @@ static const struct udevice_id airoha_eth_ids[] = {
- 	{ .compatible = "airoha,en7581-eth",
- 	  .data = (ulong)&en7581_data,
- 	},
+-	{ .compatible = "airoha,en7581-eth" },
++	{ .compatible = "airoha,en7581-eth",
++	  .data = (ulong)&en7581_data,
++	},
 +	{ .compatible = "airoha,an7583-eth",
 +	  .data = (ulong)&an7583_data,
 +	},
  	{ }
  };
  
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/305-airoha-add-Ethernet-node-in-AN7583-dtsi.patch

@@ -1,7 +1,7 @@
-From e3acb9cf6e3e08e72e3549788a4cb35eb88ce206 Mon Sep 17 00:00:00 2001
+From 613d695d0939cbbe6b66933267e3a4be263e1c7b Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Mon, 19 May 2025 14:31:59 +0200
-Subject: [PATCH 08/24] airoha: add Ethernet node in AN7583 dtsi
+Subject: [PATCH 2/4] airoha: add Ethernet node in AN7583 dtsi
 
 Add Ethernet node in AN7583 dtsi to add support for the integrated
 Ethernet Controller.
@@ -11,8 +11,6 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  arch/arm/dts/an7583.dtsi | 23 +++++++++++++++++++++++
  1 file changed, 23 insertions(+)
 
-diff --git a/arch/arm/dts/an7583.dtsi b/arch/arm/dts/an7583.dtsi
-index e1fda15ba37..daf9886af64 100644
 --- a/arch/arm/dts/an7583.dtsi
 +++ b/arch/arm/dts/an7583.dtsi
 @@ -130,6 +130,29 @@
@@ -45,6 +43,3 @@ index e1fda15ba37..daf9886af64 100644
  		syscon@1fbe3400 {
  			compatible = "airoha,en7581-pbus-csr", "syscon";
  			reg = <0x0 0x1fbe3400 0x0 0xff>;
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/306-airoha-add-MMC-node-for-Airoha-AN7583.patch

@@ -1,7 +1,7 @@
-From a982b2b81c8c73213915ff7ff655461fe2fe0cef Mon Sep 17 00:00:00 2001
+From 1a3039c1e3a194b3f1e72b4506f8bdcd5b10fbbf Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Mon, 19 May 2025 14:52:26 +0200
-Subject: [PATCH 09/24] airoha: add MMC node for Airoha AN7583
+Subject: [PATCH] airoha: add MMC node for Airoha AN7583
 
 Add MMC node for Airoha AN7583. These follow the same node of Airoha
 AN7581.
@@ -14,8 +14,6 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  arch/arm/dts/an7583.dtsi | 33 +++++++++++++++++++++++++++++++++
  1 file changed, 33 insertions(+)
 
-diff --git a/arch/arm/dts/an7583.dtsi b/arch/arm/dts/an7583.dtsi
-index daf9886af64..95c9d9a9507 100644
 --- a/arch/arm/dts/an7583.dtsi
 +++ b/arch/arm/dts/an7583.dtsi
 @@ -105,6 +105,21 @@
@@ -65,6 +63,3 @@ index daf9886af64..95c9d9a9507 100644
  		uart1: serial@1fbf0000 {
  			compatible = "ns16550";
  			reg = <0x0 0x1fbf0000 0x0 0x30>;
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/500-net-airoha-bind-MDIO-controller-on-Ethernet-load.patch

@@ -1,89 +0,0 @@
-From 1357636b826cadf15e410b64f1c98bde930dfb4e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 23 Oct 2025 19:07:45 +0200
-Subject: [PATCH 10/24] net: airoha: bind MDIO controller on Ethernet load
-
-Bind MDIO controller on Ethernet Controller load. The Airoha AN7581 SoC
-have an integrated Switch based on MT7531 (or more saying MT7988).
-
-Attach it to the mdio node in the switch node to support scanning for
-MDIO devices on the BUS with DM API.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/Kconfig      |  1 +
- drivers/net/airoha_eth.c | 32 ++++++++++++++++++++++++++++++++
- 2 files changed, 33 insertions(+)
-
-diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
-index 544e302d600..f382a7752d5 100644
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -126,6 +126,7 @@ config AIROHA_ETH
- 	depends on ARCH_AIROHA
- 	select PHYLIB
- 	select DM_RESET
-+	select MDIO_MT7531
- 	help
- 	  This Driver support Airoha Ethernet QDMA Driver
- 	  Say Y to enable support for the Airoha Ethernet QDMA.
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index 75af93f182d..661b6ac19f0 100644
---- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -10,6 +10,7 @@
- 
- #include <dm.h>
- #include <dm/devres.h>
-+#include <dm/lists.h>
- #include <mapmem.h>
- #include <net.h>
- #include <regmap.h>
-@@ -1064,6 +1065,36 @@ static int arht_eth_write_hwaddr(struct udevice *dev)
- 	return 0;
- }
- 
-+static int airoha_eth_bind(struct udevice *dev)
-+{
-+	ofnode switch_node, mdio_node;
-+	struct udevice *mdio_dev;
-+	int ret = 0;
-+
-+	if (!CONFIG_IS_ENABLED(MDIO_MT7531))
-+		return 0;
-+
-+	switch_node = ofnode_by_compatible(ofnode_null(),
-+					   "airoha,en7581-switch");
-+	if (!ofnode_valid(switch_node)) {
-+		debug("Warning: missing switch node\n");
-+		return 0;
-+	}
-+
-+	mdio_node = ofnode_find_subnode(switch_node, "mdio");
-+	if (!ofnode_valid(mdio_node)) {
-+		debug("Warning: missing mdio node\n");
-+		return 0;
-+	}
-+
-+	ret = device_bind_driver_to_node(dev, "mt7531-mdio", "mdio",
-+					 mdio_node, &mdio_dev);
-+	if (ret)
-+		debug("Warning: failed to bind mdio controller\n");
-+
-+	return 0;
-+}
-+
- static const struct airoha_eth_soc_data en7523_data = {
- 	.xsi_rsts_names = en7523_xsi_rsts_names,
- 	.num_xsi_rsts = ARRAY_SIZE(en7523_xsi_rsts_names),
-@@ -1109,6 +1140,7 @@ U_BOOT_DRIVER(airoha_eth) = {
- 	.id = UCLASS_ETH,
- 	.of_match = airoha_eth_ids,
- 	.probe = airoha_eth_probe,
-+	.bind = airoha_eth_bind,
- 	.ops = &airoha_eth_ops,
- 	.priv_auto = sizeof(struct airoha_eth),
- 	.plat_auto = sizeof(struct eth_pdata),
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/500-net-airoha-simplify-rx-free-packet-logic-a-bit.patch

@@ -0,0 +1,93 @@
+From e7b7bd119b68fe9106a1c9a45a7eba811fc40ce0 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Fri, 3 Oct 2025 20:12:06 +0300
+Subject: [PATCH v2 1/2] net: airoha: simplify rx/free packet logic a bit
+
+The commit 997786bbf473 ("drivers/net/airoha_eth: fix stalling in package
+receiving") can be improved. Instead of returning previous descriptor
+it's possible:
+ * do nothing in even descriptor case
+ * return 2 descriptor to the queue (current and previous) in the odd
+   descriptor case.
+
+This patch:
+ * implements above approach
+ * remove logic not required within new approach
+ * adds note that PKTBUFSRX must be even and larger than 7
+   for reliable driver operations
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/net/airoha_eth.c | 40 +++++++++++++++++++++-------------------
+ 1 file changed, 21 insertions(+), 19 deletions(-)
+
+--- a/drivers/net/airoha_eth.c
++++ b/drivers/net/airoha_eth.c
+@@ -492,14 +492,10 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
+ 			RX_RING_SIZE_MASK,
+ 			FIELD_PREP(RX_RING_SIZE_MASK, ndesc));
+ 
+-	/*
+-	 * See arht_eth_free_pkt() for the reasons used to fill
+-	 * REG_RX_CPU_IDX(qid) register.
+-	 */
+ 	airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK,
+ 			FIELD_PREP(RX_RING_THR_MASK, 0));
+ 	airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
+-			FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 3));
++			FIELD_PREP(RX_RING_CPU_IDX_MASK, q->ndesc - 1));
+ 	airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK,
+ 			FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head));
+ 
+@@ -1010,7 +1006,6 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+ 	struct airoha_qdma *qdma = &eth->qdma[0];
+ 	struct airoha_queue *q;
+ 	int qid;
+-	u16 prev, pprev;
+ 
+ 	if (!packet)
+ 		return 0;
+@@ -1020,22 +1015,29 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+ 
+ 	/*
+ 	 * Due to cpu cache issue the airoha_qdma_reset_rx_desc() function
+-	 * will always touch 2 descriptors:
+-	 *   - if current descriptor is even, then the previous and the one
+-	 *     before previous descriptors will be touched (previous cacheline)
+-	 *   - if current descriptor is odd, then only current and previous
+-	 *     descriptors will be touched (current cacheline)
++	 * will always touch 2 descriptors placed on the same cacheline:
++	 *   - if current descriptor is even, then current and next
++	 *     descriptors will be touched
++	 *   - if current descriptor is odd, then current and previous
++	 *     descriptors will be touched
+ 	 *
+-	 * Thus, to prevent possible destroying of rx queue, only (q->ndesc - 2)
+-	 * descriptors might be used for packet receiving.
++	 * Thus, to prevent possible destroying of rx queue, we should:
++	 *   - do nothing in the even descriptor case,
++	 *   - utilize 2 descriptors (current and previous one) in the
++	 *     odd descriptor case.
++	 *
++	 * WARNING: Observations shows that PKTBUFSRX must be even and
++	 *          larger than 7 for reliable driver operations.
+ 	 */
+-	prev  = (q->head + q->ndesc - 1) % q->ndesc;
+-	pprev = (q->head + q->ndesc - 2) % q->ndesc;
+-	q->head = (q->head + 1) % q->ndesc;
++	if (q->head & 0x01) {
++		airoha_qdma_reset_rx_desc(q, q->head - 1);
++		airoha_qdma_reset_rx_desc(q, q->head);
+ 
+-	airoha_qdma_reset_rx_desc(q, prev);
+-	airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
+-			FIELD_PREP(RX_RING_CPU_IDX_MASK, pprev));
++		airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
++				FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
++	}
++
++	q->head = (q->head + 1) % q->ndesc;
+ 
+ 	return 0;
+ }
+

package/boot/uboot-airoha/patches/501-net-airoha_eth-fix-mdio-binding-to-switch-device.patch

@@ -1,55 +0,0 @@
-From 967084a19cf6aef3a5f2a43d758e93ae1fadebbf Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:23 +0300
-Subject: [PATCH 11/24] net: airoha_eth: fix mdio binding to switch device
-
-Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
-refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio"
-driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio"
-instead.
-
-Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- drivers/net/Kconfig      | 2 +-
- drivers/net/airoha_eth.c | 4 ++--
- 2 files changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
-index f382a7752d5..51663580bdc 100644
---- a/drivers/net/Kconfig
-+++ b/drivers/net/Kconfig
-@@ -126,7 +126,7 @@ config AIROHA_ETH
- 	depends on ARCH_AIROHA
- 	select PHYLIB
- 	select DM_RESET
--	select MDIO_MT7531
-+	select MDIO_MT7531_MMIO
- 	help
- 	  This Driver support Airoha Ethernet QDMA Driver
- 	  Say Y to enable support for the Airoha Ethernet QDMA.
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index 661b6ac19f0..7be4f3c074f 100644
---- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -1071,7 +1071,7 @@ static int airoha_eth_bind(struct udevice *dev)
- 	struct udevice *mdio_dev;
- 	int ret = 0;
- 
--	if (!CONFIG_IS_ENABLED(MDIO_MT7531))
-+	if (!CONFIG_IS_ENABLED(MDIO_MT7531_MMIO))
- 		return 0;
- 
- 	switch_node = ofnode_by_compatible(ofnode_null(),
-@@ -1087,7 +1087,7 @@ static int airoha_eth_bind(struct udevice *dev)
- 		return 0;
- 	}
- 
--	ret = device_bind_driver_to_node(dev, "mt7531-mdio", "mdio",
-+	ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mdio",
- 					 mdio_node, &mdio_dev);
- 	if (ret)
- 		debug("Warning: failed to bind mdio controller\n");
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/502-net-airoha_eth-use-proper-switch-node-for-en7523-cas.patch

@@ -1,39 +0,0 @@
-From 54e56dd99f1c00eae7be5ca8c37149b8671f25d8 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:24 +0300
-Subject: [PATCH 12/24] net: airoha_eth: use proper switch node for en7523 case
-
-Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
-uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong
-for EN7523 SoC. The correct node name should be used instead.
-
-Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- drivers/net/airoha_eth.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index 7be4f3c074f..f8d7235146d 100644
---- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -1067,6 +1067,7 @@ static int arht_eth_write_hwaddr(struct udevice *dev)
- 
- static int airoha_eth_bind(struct udevice *dev)
- {
-+	struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev);
- 	ofnode switch_node, mdio_node;
- 	struct udevice *mdio_dev;
- 	int ret = 0;
-@@ -1075,7 +1076,7 @@ static int airoha_eth_bind(struct udevice *dev)
- 		return 0;
- 
- 	switch_node = ofnode_by_compatible(ofnode_null(),
--					   "airoha,en7581-switch");
-+					   data->switch_compatible);
- 	if (!ofnode_valid(switch_node)) {
- 		debug("Warning: missing switch node\n");
- 		return 0;
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/503-net-mdio-mt7531-mmio-fix-switch-regs-initialization.patch

@@ -1,35 +0,0 @@
-From 9317668aa6e37152d799d7cbaf8b3ce7926b526a Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:25 +0300
-Subject: [PATCH 13/24] net: mdio-mt7531-mmio: fix switch regs initialization
-
-mdio is a child node of the switch, so to get switch base address
-we need to lookup for a parent node
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- drivers/net/mdio-mt7531-mmio.c | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/net/mdio-mt7531-mmio.c b/drivers/net/mdio-mt7531-mmio.c
-index 3e325ca58da..5a0725010f2 100644
---- a/drivers/net/mdio-mt7531-mmio.c
-+++ b/drivers/net/mdio-mt7531-mmio.c
-@@ -151,8 +151,13 @@ static const struct mdio_ops mt7531_mdio_ops = {
- static int mt7531_mdio_probe(struct udevice *dev)
- {
- 	struct mt7531_mdio_priv *priv = dev_get_priv(dev);
-+	ofnode switch_node;
- 
--	priv->switch_regs = dev_read_addr(dev);
-+	switch_node = ofnode_get_parent(dev_ofnode(dev));
-+	if (!ofnode_valid(switch_node))
-+		return -EINVAL;
-+
-+	priv->switch_regs = ofnode_get_addr(switch_node);
- 	if (priv->switch_regs == FDT_ADDR_T_NONE)
- 		return -EINVAL;
- 
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/504-net-airoha-increase-the-number-of-rx-network-buffers.patch

@@ -0,0 +1,35 @@
+From 75d82c8878b2ffff489fbc7a5c0381f8f6484ec2 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Fri, 3 Oct 2025 05:28:41 +0300
+Subject: [PATCH 5/5] net: airoha: increase the number of rx network buffers
+
+According to commit 997786bbf473 ("drivers/net/airoha_eth: fix stalling
+in package receiving") the minimal possible value of SYS_RX_ETH_BUFFER
+is 4. Unfortunately it's too small for reliable ping.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ configs/an7581_evb_defconfig | 1 +
+ configs/an7583_evb_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/configs/an7581_evb_defconfig
++++ b/configs/an7581_evb_defconfig
+@@ -43,6 +43,7 @@ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+ CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_SYS_RX_ETH_BUFFER=8
+ CONFIG_REGMAP=y
+ CONFIG_SYSCON=y
+ CONFIG_CLK=y
+--- a/configs/an7583_evb_defconfig
++++ b/configs/an7583_evb_defconfig
+@@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+ CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_SYS_RX_ETH_BUFFER=8
+ CONFIG_REGMAP=y
+ CONFIG_SYSCON=y
+ CONFIG_CLK=y

package/boot/uboot-airoha/patches/504-net-mdio-mt7531-mmio-use-common-header-priv-struct.patch

@@ -1,114 +0,0 @@
-From 1a853053a3e44cae45f16b1b30da70da2629c590 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 9 Feb 2026 12:20:33 +0100
-Subject: [PATCH 14/24] net: mdio-mt7531-mmio: use common header priv struct
-
-Instead of having duplicate priv struct for mdio-mt7531-mmio driver in
-both driver and header, use the one exposed by the header directly.
-
-This make sure we have consistent priv struct if the driver will be
-updated in the future.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/mdio-mt7531-mmio.c | 24 +++++++++++-------------
- 1 file changed, 11 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/net/mdio-mt7531-mmio.c b/drivers/net/mdio-mt7531-mmio.c
-index 5a0725010f2..930454a9b0e 100644
---- a/drivers/net/mdio-mt7531-mmio.c
-+++ b/drivers/net/mdio-mt7531-mmio.c
-@@ -6,6 +6,8 @@
- #include <linux/iopoll.h>
- #include <miiphy.h>
- 
-+#include "mdio-mt7531-mmio.h"
-+
- #define MT7531_PHY_IAC			0x701c
- #define   MT7531_PHY_ACS_ST		BIT(31)
- #define   MT7531_MDIO_REG_ADDR_CL22	GENMASK(29, 25)
-@@ -25,11 +27,7 @@
- #define MT7531_MDIO_TIMEOUT		100000
- #define MT7531_MDIO_SLEEP		20
- 
--struct mt7531_mdio_priv {
--	phys_addr_t switch_regs;
--};
--
--static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv)
-+static int mt7531_mdio_wait_busy(struct mt7531_mdio_mmio_priv *priv)
- {
- 	unsigned int busy;
- 
-@@ -38,7 +36,7 @@ static int mt7531_mdio_wait_busy(struct mt7531_mdio_priv *priv)
- 					MT7531_MDIO_SLEEP, MT7531_MDIO_TIMEOUT);
- }
- 
--static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad, int reg)
-+static int mt7531_mdio_read(struct mt7531_mdio_mmio_priv *priv, int addr, int devad, int reg)
- {
- 	u32 val;
- 
-@@ -75,7 +73,7 @@ static int mt7531_mdio_read(struct mt7531_mdio_priv *priv, int addr, int devad,
- 	return val & MT7531_MDIO_RW_DATA;
- }
- 
--static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad,
-+static int mt7531_mdio_write(struct mt7531_mdio_mmio_priv *priv, int addr, int devad,
- 			     int reg, u16 value)
- {
- 	u32 val;
-@@ -115,7 +113,7 @@ static int mt7531_mdio_write(struct mt7531_mdio_priv *priv, int addr, int devad,
- 
- int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg)
- {
--	struct mt7531_mdio_priv *priv = bus->priv;
-+	struct mt7531_mdio_mmio_priv *priv = bus->priv;
- 
- 	return mt7531_mdio_read(priv, addr, devad, reg);
- }
-@@ -123,14 +121,14 @@ int mt7531_mdio_mmio_read(struct mii_dev *bus, int addr, int devad, int reg)
- int mt7531_mdio_mmio_write(struct mii_dev *bus, int addr, int devad,
- 			   int reg, u16 value)
- {
--	struct mt7531_mdio_priv *priv = bus->priv;
-+	struct mt7531_mdio_mmio_priv *priv = bus->priv;
- 
- 	return mt7531_mdio_write(priv, addr, devad, reg, value);
- }
- 
- static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg)
- {
--	struct mt7531_mdio_priv *priv = dev_get_priv(dev);
-+	struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev);
- 
- 	return mt7531_mdio_read(priv, addr, devad, reg);
- }
-@@ -138,7 +136,7 @@ static int dm_mt7531_mdio_read(struct udevice *dev, int addr, int devad, int reg
- static int dm_mt7531_mdio_write(struct udevice *dev, int addr, int devad,
- 				int reg, u16 value)
- {
--	struct mt7531_mdio_priv *priv = dev_get_priv(dev);
-+	struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev);
- 
- 	return mt7531_mdio_write(priv, addr, devad, reg, value);
- }
-@@ -150,7 +148,7 @@ static const struct mdio_ops mt7531_mdio_ops = {
- 
- static int mt7531_mdio_probe(struct udevice *dev)
- {
--	struct mt7531_mdio_priv *priv = dev_get_priv(dev);
-+	struct mt7531_mdio_mmio_priv *priv = dev_get_priv(dev);
- 	ofnode switch_node;
- 
- 	switch_node = ofnode_get_parent(dev_ofnode(dev));
-@@ -169,5 +167,5 @@ U_BOOT_DRIVER(mt7531_mdio) = {
- 	.id             = UCLASS_MDIO,
- 	.probe          = mt7531_mdio_probe,
- 	.ops            = &mt7531_mdio_ops,
--	.priv_auto	  = sizeof(struct mt7531_mdio_priv),
-+	.priv_auto	  = sizeof(struct mt7531_mdio_mmio_priv),
- };
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/505-configs-an7581-add-mii-mdio-support.patch

@@ -1,29 +0,0 @@
-From 25125e98275aa43023c1d311433e0dca1c12e069 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:26 +0300
-Subject: [PATCH 15/24] configs: an7581: add mii/mdio support
-
-This enables mdio/mii command support.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- configs/an7581_evb_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index 73af30cd693..8e2c694dbbb 100644
---- a/configs/an7581_evb_defconfig
-+++ b/configs/an7581_evb_defconfig
-@@ -66,6 +66,9 @@ CONFIG_SPI_FLASH_STMICRO=y
- CONFIG_SPI_FLASH_WINBOND=y
- CONFIG_SPI_FLASH_MTD=y
- CONFIG_AIROHA_ETH=y
-+CONFIG_DM_MDIO=y
-+CONFIG_CMD_MII=y
-+CONFIG_CMD_MDIO=y
- CONFIG_PHY=y
- CONFIG_PINCTRL=y
- CONFIG_PINCONF=y
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/506-arm-dts-an7581-add-mdio-child-node-to-switch-node.patch

@@ -1,31 +0,0 @@
-From 3236c124261ca9da41632762c36b86aface13b05 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:27 +0300
-Subject: [PATCH 16/24] arm: dts: an7581: add mdio child node to switch node
-
-add mdio node to be able see switch port states
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- arch/arm/dts/an7581-u-boot.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/dts/an7581-u-boot.dtsi b/arch/arm/dts/an7581-u-boot.dtsi
-index a9297ca6503..c5e24c76457 100644
---- a/arch/arm/dts/an7581-u-boot.dtsi
-+++ b/arch/arm/dts/an7581-u-boot.dtsi
-@@ -57,6 +57,11 @@
- 		switch: switch@1fb58000 {
- 			compatible = "airoha,en7581-switch";
- 			reg = <0 0x1fb58000 0 0x8000>;
-+
-+			mdio: mdio {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
- 		};
- 
- 		snfi: spi@1fa10000 {
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/507-configs-en7523-add-mii-mdio-support.patch

@@ -1,29 +0,0 @@
-From 6efbdacd79d253507e62ae93358953fff6fb3173 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:28 +0300
-Subject: [PATCH 17/24] configs: en7523: add mii/mdio support
-
-This enables mdio/mii command support.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- configs/en7523_evb_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/configs/en7523_evb_defconfig b/configs/en7523_evb_defconfig
-index 113ddb46a7f..ebd99d133c9 100644
---- a/configs/en7523_evb_defconfig
-+++ b/configs/en7523_evb_defconfig
-@@ -51,6 +51,9 @@ CONFIG_MTD=y
- CONFIG_DM_MTD=y
- CONFIG_MTD_SPI_NAND=y
- CONFIG_AIROHA_ETH=y
-+CONFIG_DM_MDIO=y
-+CONFIG_CMD_MII=y
-+CONFIG_CMD_MDIO=y
- CONFIG_PHY=y
- CONFIG_PINCTRL=y
- CONFIG_PINCONF=y
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/508-arm-dts-en7523-add-mdio-child-node-to-switch-node.patch

@@ -1,31 +0,0 @@
-From 3ad8d165ce15559d5cab0df0cad9559e81c995f4 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 31 Jan 2026 01:06:29 +0300
-Subject: [PATCH 18/24] arm: dts: en7523: add mdio child node to switch node
-
-add mdio node to be able see switch port states
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- arch/arm/dts/en7523-u-boot.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi
-index f031f81515a..9eadaccc500 100644
---- a/arch/arm/dts/en7523-u-boot.dtsi
-+++ b/arch/arm/dts/en7523-u-boot.dtsi
-@@ -42,6 +42,11 @@
- 	switch: switch@1fb58000 {
- 		compatible = "airoha,en7523-switch";
- 		reg = <0x1fb58000 0x8000>;
-+
-+		mdio: mdio {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+		};
- 	};
- 
- 	snfi: spi@1fa10000 {
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/509-configs-an7583-add-mii-mdio-support.patch

@@ -1,29 +0,0 @@
-From c8d2c4c3beb5fd27a041744f0f9a6b6d5c4e1ebe Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 11 Feb 2026 03:26:13 +0300
-Subject: [PATCH 19/24] configs: an7583: add mii/mdio support
-
-This enables mdio/mii command support.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu
----
- configs/an7583_evb_defconfig | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index d1893fff398..41d98bab5de 100644
---- a/configs/an7583_evb_defconfig
-+++ b/configs/an7583_evb_defconfig
-@@ -65,6 +65,9 @@ CONFIG_SPI_FLASH_STMICRO=y
- CONFIG_SPI_FLASH_WINBOND=y
- CONFIG_SPI_FLASH_MTD=y
- CONFIG_AIROHA_ETH=y
-+CONFIG_DM_MDIO=y
-+CONFIG_CMD_MII=y
-+CONFIG_CMD_MDIO=y
- CONFIG_PHY=y
- CONFIG_PINCTRL=y
- CONFIG_PINCONF=y
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/510-arm-dts-an7583-add-mdio-child-node-to-switch-node.patch

@@ -1,31 +0,0 @@
-From 7f9bbd9ed8d2e3b7dae0fbc7d2bd2b0c08a115d0 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 11 Feb 2026 03:29:23 +0300
-Subject: [PATCH 20/24] arm: dts: an7583: add mdio child node to switch node
-
-add mdio node to be able see switch port states
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- arch/arm/dts/an7583.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/arm/dts/an7583.dtsi b/arch/arm/dts/an7583.dtsi
-index 95c9d9a9507..d84ccf27f2c 100644
---- a/arch/arm/dts/an7583.dtsi
-+++ b/arch/arm/dts/an7583.dtsi
-@@ -166,6 +166,11 @@
- 		switch: switch@1fb58000 {
- 			compatible = "airoha,an7583-switch";
- 			reg = <0 0x1fb58000 0 0x8000>;
-+
-+			mdio: mdio {
-+				#address-cells = <1>;
-+				#size-cells = <0>;
-+			};
- 		};
- 
- 		syscon@1fbe3400 {
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/900-airoha-enable-UBI-support-and-define-default-partiti.patch

@@ -1,30 +1,47 @@
-From 06a44c562647bedd0705cac8bec862877371ff1f Mon Sep 17 00:00:00 2001
+From 28a72d957b897e7f7212c11f99052a32b0f6abc4 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Wed, 28 May 2025 03:10:53 +0200
-Subject: [PATCH 21/24] airoha: enable UBI support and define default partition
+Subject: [PATCH 1/2] airoha: enable UBI support and define default partition
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
- arch/arm/dts/an7583-evb.dts         | 22 ++++++++++++++++++++++
- arch/arm/dts/en7523-evb-u-boot.dtsi | 22 ++++++++++++++++++++++
- arch/arm/dts/en7581-evb-u-boot.dtsi | 22 ++++++++++++++++++++++
- configs/an7581_evb_defconfig        | 17 +++++++++++++++++
- configs/an7583_evb_defconfig        | 17 +++++++++++++++++
- configs/en7523_evb_defconfig        | 20 ++++++++++++++++++--
- 6 files changed, 118 insertions(+), 2 deletions(-)
+ arch/arm/dts/an7581-u-boot.dtsi | 16 ++++++++++++++++
+ arch/arm/dts/an7583-evb.dts     | 22 ++++++++++++++++++++++
+ configs/an7581_evb_defconfig    | 16 ++++++++++++++++
+ configs/an7583_evb_defconfig    | 16 ++++++++++++++++
+ 4 files changed, 70 insertions(+)
 
-diff --git a/arch/arm/dts/an7583-evb.dts b/arch/arm/dts/an7583-evb.dts
-index d02cd194e8a..b3045e6e7d0 100644
+--- a/arch/arm/dts/an7581-u-boot.dtsi
++++ b/arch/arm/dts/an7581-u-boot.dtsi
+@@ -76,6 +76,22 @@
+ 				spi-max-frequency = <50000000>;
+ 				spi-tx-bus-width = <1>;
+ 				spi-rx-bus-width = <2>;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <1>;
++					#size-cells = <1>;
++
++					bl2@0 {
++						label = "bl2";
++						reg = <0x0 0x20000>;
++					};
++
++					ubi@20000 {
++						label = "ubi";
++						reg = <0x20000 0x0>;
++					};
++				};
+ 			};
+ 		};
+ 
 --- a/arch/arm/dts/an7583-evb.dts
 +++ b/arch/arm/dts/an7583-evb.dts
-@@ -46,6 +46,28 @@
+@@ -46,6 +46,24 @@
  	};
  };
  
-+&snfi {
-+	status = "okay";
-+};
-+
 +&spi_nand {
 +	partitions {
 +		compatible = "fixed-partitions";
@@ -46,79 +63,16 @@ index d02cd194e8a..b3045e6e7d0 100644
  &pcie0 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pcie0_rst_pins>;
-diff --git a/arch/arm/dts/en7523-evb-u-boot.dtsi b/arch/arm/dts/en7523-evb-u-boot.dtsi
-index c109d6794fb..b74bfe2d707 100644
---- a/arch/arm/dts/en7523-evb-u-boot.dtsi
-+++ b/arch/arm/dts/en7523-evb-u-boot.dtsi
-@@ -9,3 +9,25 @@
- };
- 
- #include "en7523-u-boot.dtsi"
-+
-+&snfi {
-+	status = "okay";
-+};
-+
-+&spi_nand {
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		bl2@0 {
-+			label = "bl2";
-+			reg = <0x0 0x20000>;
-+		};
-+
-+		ubi@20000 {
-+			label = "ubi";
-+			reg = <0x20000 0x0>;
-+		};
-+	};
-+};
-diff --git a/arch/arm/dts/en7581-evb-u-boot.dtsi b/arch/arm/dts/en7581-evb-u-boot.dtsi
-index ebd3b8b4958..b9a9382e254 100644
---- a/arch/arm/dts/en7581-evb-u-boot.dtsi
-+++ b/arch/arm/dts/en7581-evb-u-boot.dtsi
-@@ -9,3 +9,25 @@
- };
- 
- #include "an7581-u-boot.dtsi"
-+
-+&snfi {
-+	status = "okay";
-+};
-+
-+&spi_nand {
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		bl2@0 {
-+			label = "bl2";
-+			reg = <0x0 0x20000>;
-+		};
-+
-+		ubi@20000 {
-+			label = "ubi";
-+			reg = <0x20000 0x0>;
-+		};
-+	};
-+};
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index 8e2c694dbbb..05e37d04681 100644
 --- a/configs/an7581_evb_defconfig
 +++ b/configs/an7581_evb_defconfig
-@@ -81,4 +81,21 @@ CONFIG_SYS_NS16550=y
- CONFIG_SPI=y
+@@ -78,3 +78,19 @@ CONFIG_SPI=y
  CONFIG_DM_SPI=y
  CONFIG_AIROHA_SNFI_SPI=y
+ CONFIG_SHA512=y
 +CONFIG_CMD_UBI=y
 +# CONFIG_CMD_UBI_RENAME is not set
 +CONFIG_CMD_UBIFS=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
 +CONFIG_ENV_UBI_PART="ubi"
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
@@ -131,20 +85,16 @@ index 8e2c694dbbb..05e37d04681 100644
 +CONFIG_UBI_BLOCK=y
 +# CONFIG_UBIFS_SILENCE_MSG is not set
 +# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
- CONFIG_SHA512=y
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index 41d98bab5de..663d1ec52ae 100644
 --- a/configs/an7583_evb_defconfig
 +++ b/configs/an7583_evb_defconfig
-@@ -80,4 +80,21 @@ CONFIG_SYS_NS16550=y
- CONFIG_SPI=y
- CONFIG_DM_SPI=y
+@@ -80,3 +80,19 @@ CONFIG_SHA512=y
+ CONFIG_AIROHA_ETH=y
+ CONFIG_MMC_MTK=y
  CONFIG_AIROHA_SNFI_SPI=y
 +CONFIG_CMD_UBI=y
 +# CONFIG_CMD_UBI_RENAME is not set
 +CONFIG_CMD_UBIFS=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
 +CONFIG_ENV_UBI_PART="ubi"
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
@@ -157,51 +107,3 @@ index 41d98bab5de..663d1ec52ae 100644
 +CONFIG_UBI_BLOCK=y
 +# CONFIG_UBIFS_SILENCE_MSG is not set
 +# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
- CONFIG_SHA512=y
-diff --git a/configs/en7523_evb_defconfig b/configs/en7523_evb_defconfig
-index ebd99d133c9..4d01e3f54fe 100644
---- a/configs/en7523_evb_defconfig
-+++ b/configs/en7523_evb_defconfig
-@@ -5,7 +5,6 @@ CONFIG_TEXT_BASE=0x81E00000
- CONFIG_SYS_MALLOC_F_LEN=0x4000
- CONFIG_NR_DRAM_BANKS=1
- CONFIG_ENV_SIZE=0x4000
--CONFIG_ENV_OFFSET=0x7c000
- CONFIG_DM_GPIO=y
- CONFIG_DEFAULT_DEVICE_TREE="airoha/en7523-evb"
- CONFIG_SYS_LOAD_ADDR=0x81800000
-@@ -36,8 +35,8 @@ CONFIG_CMD_MTDPARTS=y
- CONFIG_CMD_LOG=y
- CONFIG_OF_UPSTREAM=y
- CONFIG_ENV_OVERWRITE=y
-+# CONFIG_ENV_IS_IN_MTD is not set
- CONFIG_ENV_RELOC_GD_ENV_ADDR=y
--CONFIG_ENV_MTD_DEV="spi-nand0"
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
- CONFIG_NET_RANDOM_ETHADDR=y
- CONFIG_SYS_RX_ETH_BUFFER=8
-@@ -63,4 +62,21 @@ CONFIG_SYS_NS16550=y
- CONFIG_SPI=y
- CONFIG_DM_SPI=y
- CONFIG_AIROHA_SNFI_SPI=y
-+CONFIG_CMD_UBI=y
-+# CONFIG_CMD_UBI_RENAME is not set
-+CONFIG_CMD_UBIFS=y
-+CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
-+CONFIG_ENV_UBI_PART="ubi"
-+CONFIG_ENV_UBI_VOLUME="ubootenv"
-+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_UBI_VID_OFFSET=0
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_MODULE=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_LIMIT=20
-+# CONFIG_MTD_UBI_FASTMAP is not set
-+CONFIG_UBI_BLOCK=y
-+# CONFIG_UBIFS_SILENCE_MSG is not set
-+# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
- CONFIG_SHA512=y
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/901-airoha-add-default-configuration.patch

@@ -1,57 +1,34 @@
-From 2bd435e8b2da2047ea0c5bb9b9af96bc6af2f8cd Mon Sep 17 00:00:00 2001
+From f85e675d7be222d88246bfdb42a1faac92f1eb63 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Wed, 28 May 2025 03:18:32 +0200
-Subject: [PATCH 22/24] airoha: add default configuration
+Subject: [PATCH 2/2] airoha: add default configuration
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
  configs/an7581_evb_defconfig | 2 ++
  configs/an7583_evb_defconfig | 2 ++
- configs/en7523_evb_defconfig | 2 ++
  defenvs/an7581_rfb_env       | 4 ++++
  defenvs/an7583_rfb_env       | 4 ++++
- defenvs/en7523_rfb_env       | 4 ++++
- 6 files changed, 18 insertions(+)
+ 4 files changed, 12 insertions(+)
  create mode 100644 defenvs/an7581_rfb_env
  create mode 100644 defenvs/an7583_rfb_env
- create mode 100644 defenvs/en7523_rfb_env
 
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index 05e37d04681..7633cb7ac96 100644
 --- a/configs/an7581_evb_defconfig
 +++ b/configs/an7581_evb_defconfig
-@@ -98,4 +98,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
+@@ -94,3 +94,5 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
  CONFIG_UBI_BLOCK=y
  # CONFIG_UBIFS_SILENCE_MSG is not set
  # CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
 +CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE=y
 +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="defenvs/an7581_rfb_env"
- CONFIG_SHA512=y
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index 663d1ec52ae..c69cf353ffa 100644
 --- a/configs/an7583_evb_defconfig
 +++ b/configs/an7583_evb_defconfig
-@@ -97,4 +97,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
+@@ -96,3 +96,5 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
  CONFIG_UBI_BLOCK=y
  # CONFIG_UBIFS_SILENCE_MSG is not set
  # CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
 +CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE=y
 +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="defenvs/an7583_rfb_env"
- CONFIG_SHA512=y
-diff --git a/configs/en7523_evb_defconfig b/configs/en7523_evb_defconfig
-index 4d01e3f54fe..8febb6cabdd 100644
---- a/configs/en7523_evb_defconfig
-+++ b/configs/en7523_evb_defconfig
-@@ -79,4 +79,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
- CONFIG_UBI_BLOCK=y
- # CONFIG_UBIFS_SILENCE_MSG is not set
- # CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
-+CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE=y
-+CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="defenvs/en7523_rfb_env"
- CONFIG_SHA512=y
-diff --git a/defenvs/an7581_rfb_env b/defenvs/an7581_rfb_env
-new file mode 100644
-index 00000000000..716ddc321e2
 --- /dev/null
 +++ b/defenvs/an7581_rfb_env
 @@ -0,0 +1,4 @@
@@ -59,9 +36,6 @@ index 00000000000..716ddc321e2
 +ipaddr=192.168.1.1
 +serverip=192.168.1.10
 +bootargs=ubi.mtd=ubi root=/dev/ubiblock0_5 rootwait
-diff --git a/defenvs/an7583_rfb_env b/defenvs/an7583_rfb_env
-new file mode 100644
-index 00000000000..716ddc321e2
 --- /dev/null
 +++ b/defenvs/an7583_rfb_env
 @@ -0,0 +1,4 @@
@@ -69,16 +43,3 @@ index 00000000000..716ddc321e2
 +ipaddr=192.168.1.1
 +serverip=192.168.1.10
 +bootargs=ubi.mtd=ubi root=/dev/ubiblock0_5 rootwait
-diff --git a/defenvs/en7523_rfb_env b/defenvs/en7523_rfb_env
-new file mode 100644
-index 00000000000..716ddc321e2
---- /dev/null
-+++ b/defenvs/en7523_rfb_env
-@@ -0,0 +1,4 @@
-+loadaddr=0x81800000
-+ipaddr=192.168.1.1
-+serverip=192.168.1.10
-+bootargs=ubi.mtd=ubi root=/dev/ubiblock0_5 rootwait
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/902-arm-airoha-disable-environment-inside-mtd-partition.patch

@@ -1,7 +1,7 @@
-From c89b8f1baa9bf4e32b9f146f5fece6f2151e2dd0 Mon Sep 17 00:00:00 2001
+From 10bd131a6a365965ce868419933fd7936e91c635 Mon Sep 17 00:00:00 2001
 From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
 Date: Mon, 13 Oct 2025 20:48:00 +0300
-Subject: [PATCH 23/24] arm: airoha: disable environment inside mtd partition
+Subject: [PATCH 2/3] arm: airoha: disable environment inside mtd partition
 
 When booting on en7581_evb board equipped with spinand flash, a u-boot
 panic occurs. The panic is caused by the absence any available mtd
@@ -17,11 +17,9 @@ Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
  configs/an7583_evb_defconfig | 1 +
  2 files changed, 2 insertions(+)
 
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index 7633cb7ac96..afdb0cd8586 100644
 --- a/configs/an7581_evb_defconfig
 +++ b/configs/an7581_evb_defconfig
-@@ -41,6 +41,7 @@ CONFIG_CMD_LOG=y
+@@ -40,6 +40,7 @@ CONFIG_CMD_LOG=y
  CONFIG_OF_UPSTREAM=y
  CONFIG_ENV_OVERWRITE=y
  CONFIG_ENV_IS_IN_MMC=y
@@ -29,11 +27,9 @@ index 7633cb7ac96..afdb0cd8586 100644
  CONFIG_ENV_RELOC_GD_ENV_ADDR=y
  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  CONFIG_NET_RANDOM_ETHADDR=y
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index c69cf353ffa..c3d47c411ba 100644
 --- a/configs/an7583_evb_defconfig
 +++ b/configs/an7583_evb_defconfig
-@@ -40,6 +40,7 @@ CONFIG_CMD_MTDPARTS=y
+@@ -41,6 +41,7 @@ CONFIG_CMD_MTDPARTS=y
  CONFIG_CMD_LOG=y
  CONFIG_ENV_OVERWRITE=y
  CONFIG_ENV_IS_IN_MMC=y
@@ -41,6 +37,4 @@ index c69cf353ffa..c3d47c411ba 100644
  CONFIG_ENV_RELOC_GD_ENV_ADDR=y
  CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  CONFIG_NET_RANDOM_ETHADDR=y
--- 
-2.51.0
 

package/boot/uboot-airoha/patches/903-arm-airoha-dts-enable-spi-support-for-en7581_evb-boa.patch

@@ -0,0 +1,23 @@
+From 6c4a07ecf211b56eb28fe2dbd8e324b2fdecb84a Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 13 Oct 2025 20:44:24 +0300
+Subject: [PATCH 1/3] arm: airoha: dts: enable spi support for en7581_evb board
+
+spinand flashes are inaccessible without this patch
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ arch/arm/dts/en7581-evb-u-boot.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm/dts/en7581-evb-u-boot.dtsi
++++ b/arch/arm/dts/en7581-evb-u-boot.dtsi
+@@ -9,3 +9,7 @@
+ };
+ 
+ #include "an7581-u-boot.dtsi"
++
++&snfi {
++	status = "okay";
++};
+

package/boot/uboot-airoha/patches/903-arm-airoha-enable-position-independent-code.patch

@@ -1,51 +0,0 @@
-From 78a01bfa242139ae6b7ac487c0e857457d8ff416 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Mon, 13 Oct 2025 20:56:31 +0300
-Subject: [PATCH 24/24] arm: airoha: enable position independent code
-
-This slightly increase the code, but makes debugging a bit easy
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
----
- configs/an7581_evb_defconfig | 1 +
- configs/an7583_evb_defconfig | 1 +
- configs/en7523_evb_defconfig | 1 +
- 3 files changed, 3 insertions(+)
-
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index afdb0cd8586..be076ec7723 100644
---- a/configs/an7581_evb_defconfig
-+++ b/configs/an7581_evb_defconfig
-@@ -1,5 +1,6 @@
- CONFIG_ARM=y
- CONFIG_ARCH_AIROHA=y
-+CONFIG_POSITION_INDEPENDENT=y
- CONFIG_TARGET_AN7581=y
- CONFIG_TEXT_BASE=0x81E00000
- CONFIG_SYS_MALLOC_F_LEN=0x4000
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index c3d47c411ba..7ef2d6feeba 100644
---- a/configs/an7583_evb_defconfig
-+++ b/configs/an7583_evb_defconfig
-@@ -1,5 +1,6 @@
- CONFIG_ARM=y
- CONFIG_ARCH_AIROHA=y
-+CONFIG_POSITION_INDEPENDENT=y
- CONFIG_TARGET_AN7583=y
- CONFIG_TEXT_BASE=0x81E00000
- CONFIG_SYS_MALLOC_F_LEN=0x4000
-diff --git a/configs/en7523_evb_defconfig b/configs/en7523_evb_defconfig
-index 8febb6cabdd..53011e47f55 100644
---- a/configs/en7523_evb_defconfig
-+++ b/configs/en7523_evb_defconfig
-@@ -1,6 +1,7 @@
- CONFIG_ARM=y
- CONFIG_SYS_ARCH_TIMER=y
- CONFIG_ARCH_AIROHA=y
-+CONFIG_POSITION_INDEPENDENT=y
- CONFIG_TEXT_BASE=0x81E00000
- CONFIG_SYS_MALLOC_F_LEN=0x4000
- CONFIG_NR_DRAM_BANKS=1
--- 
-2.51.0
-

package/boot/uboot-airoha/patches/904-arm-airoha-enable-position-independent-code.patch

@@ -0,0 +1,32 @@
+From bee36b6f42792556e123f331ece80f8d5a40e8cd Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 13 Oct 2025 20:56:31 +0300
+Subject: [PATCH 3/3] arm: airoha: enable position independent code
+
+This slightly increase the code, but makes debugging a bit easy
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ configs/an7581_evb_defconfig | 1 +
+ configs/an7583_evb_defconfig | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/configs/an7581_evb_defconfig
++++ b/configs/an7581_evb_defconfig
+@@ -1,5 +1,6 @@
+ CONFIG_ARM=y
+ CONFIG_ARCH_AIROHA=y
++CONFIG_POSITION_INDEPENDENT=y
+ CONFIG_TEXT_BASE=0x81E00000
+ CONFIG_SYS_MALLOC_F_LEN=0x4000
+ CONFIG_NR_DRAM_BANKS=1
+--- a/configs/an7583_evb_defconfig
++++ b/configs/an7583_evb_defconfig
+@@ -1,5 +1,6 @@
+ CONFIG_ARM=y
+ CONFIG_ARCH_AIROHA=y
++CONFIG_POSITION_INDEPENDENT=y
+ CONFIG_TARGET_AN7583=y
+ CONFIG_TEXT_BASE=0x81E00000
+ CONFIG_SYS_MALLOC_F_LEN=0x4000
+

package/boot/uboot-bcm53xx/Makefile

@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 
-PKG_VERSION:=2025.10
-PKG_HASH:=b4f032848e56cc8f213ad59f9132c084dbbb632bc29176d024e58220e0efdf4a
-PKG_RELEASE:=1
+PKG_VERSION:=2024.01
+PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
+PKG_RELEASE:=2
 
 include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk

package/boot/uboot-d1/Makefile

@@ -6,10 +6,13 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
-PKG_VERSION:=2024.01
+PKG_VERSION:=2023.01
 PKG_RELEASE:=1
 
-PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
+PKG_HASH:=69423bad380f89a0916636e89e6dcbd2e4512d584308d922d1039d1e4331950f
+
+include $(INCLUDE_DIR)/u-boot.mk
+include $(INCLUDE_DIR)/package.mk
 
 include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk

package/boot/uboot-d1/patches/0001-ARM-dts-sun8i-A33-Add-iNet-U70B-REV01.patch

@@ -0,0 +1,197 @@
+From d45e64aad18e5e324425b9efbe6a0ec9e1a343da Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 20 Nov 2021 13:19:13 -0600
+Subject: [PATCH 01/90] ARM: dts: sun8i: A33: Add iNet U70B REV01
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/Makefile                     |   1 +
+ arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 172 ++++++++++++++++++++++
+ 2 files changed, 173 insertions(+)
+ create mode 100644 arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -644,6 +644,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
+ 	sun8i-a33-et-q8-v1.6.dtb \
+ 	sun8i-a33-ga10h-v1.1.dtb \
+ 	sun8i-a33-inet-d978-rev2.dtb \
++	sun8i-a33-inet-u70b-rev1.dtb \
+ 	sun8i-a33-ippo-q8h-v1.2.dtb \
+ 	sun8i-a33-olinuxino.dtb \
+ 	sun8i-a33-q8-tablet.dtb \
+--- /dev/null
++++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+@@ -0,0 +1,172 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++
++/dts-v1/;
++
++#include "sun8i-a33.dtsi"
++#include "sun8i-reference-design-tablet.dtsi"
++
++/ {
++	model = "iNet U70B REV01";
++	compatible = "inet-tek,inet-u70b-rev01", "allwinner,sun8i-a33";
++
++	aliases {
++		ethernet0 = &rtl8723cs;
++	};
++
++	panel: panel {
++		compatible = "panel-dpi";
++		backlight = <&backlight>;
++		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		power-supply = <&reg_dc1sw>;
++
++		panel-timing {
++			clock-frequency = <51000000>;
++			hactive = <1024>;
++			vactive = <600>;
++			hfront-porch = <162>;
++			hback-porch = <158>;
++			hsync-len = <20>;
++			vback-porch = <25>;
++			vfront-porch = <10>;
++			vsync-len = <3>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++		};
++
++		port {
++			panel_in_tcon0: endpoint {
++				remote-endpoint = <&tcon0_out_panel>;
++			};
++		};
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&dai {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++
++	accelerometer@18 {
++		compatible = "bosch,bma250";
++		reg = <0x18>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
++	};
++};
++
++&mmc1 {
++	pinctrl-0 = <&mmc1_pg_pins>;
++	pinctrl-names = "default";
++	bus-width = <4>;
++	non-removable;
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_dldo2>;
++	status = "okay";
++
++	rtl8723cs: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
++	};
++};
++
++&nfc {
++	status = "okay";
++
++	nand@0 {
++		reg = <0>;
++		allwinner,rb = <0>;
++		nand-ecc-maximize;
++	};
++};
++
++&r_uart {
++	status = "disabled";
++};
++
++&reg_dldo2 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi-io";
++};
++
++&simplefb_lcd {
++	status = "okay";
++};
++
++&sound {
++	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,widgets = "Headphone", "Headphone Jack",
++				    "Microphone", "Internal Microphone",
++				    "Speaker", "Internal Speaker";
++	simple-audio-card,routing = "Headphone Jack", "HP",
++				    "Internal Speaker", "Speaker Amp OUTL",
++				    "Internal Speaker", "Speaker Amp OUTR",
++				    "Speaker Amp INL", "HP", /* PHONEOUT ??? */
++				    "Speaker Amp INR", "HP", /* PHONEOUT ??? */
++				    "Left DAC", "DACL",
++				    "Right DAC", "DACR",
++				    "ADCL", "Left ADC",
++				    "ADCR", "Right ADC",
++				    "MIC1", "Internal Microphone",
++				    "MIC2", "Headset Microphone",
++				    "Headset Microphone", "HBIAS",
++				    "Internal Microphone", "MBIAS";
++	status = "okay";
++};
++
++&tcon0 {
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
++&tcon0_out {
++	tcon0_out_panel: endpoint {
++		remote-endpoint = <&panel_in_tcon0>;
++	};
++};
++
++&touchscreen {
++	reg = <0x40>;
++	compatible = "silead,gsl1680";
++	avdd-supply = <&reg_ldo_io1>;
++	touchscreen-size-x = <1024>;
++	touchscreen-size-y = <600>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723cs-bt";
++		device-wake-gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		host-wake-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++	};
++};

package/boot/uboot-d1/patches/0002-riscv-cpu-Add-skeleton-for-T-HEAD-CPUs.patch

@@ -1,74 +0,0 @@
-From ddbe65963dec1e261c23d027602b89d18d90ae63 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 4 Feb 2023 13:58:20 -0600
-Subject: [PATCH 02/68] riscv: cpu: Add skeleton for T-HEAD CPUs
-
-This is a direct copy of the existing generic CPU code.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/cpu/thead/Makefile |  4 ++++
- arch/riscv/cpu/thead/cpu.c    | 22 ++++++++++++++++++++++
- arch/riscv/cpu/thead/dram.c   | 22 ++++++++++++++++++++++
- 3 files changed, 48 insertions(+)
- create mode 100644 arch/riscv/cpu/thead/Makefile
- create mode 100644 arch/riscv/cpu/thead/cpu.c
- create mode 100644 arch/riscv/cpu/thead/dram.c
-
---- /dev/null
-+++ b/arch/riscv/cpu/thead/Makefile
-@@ -0,0 +1,4 @@
-+# SPDX-License-Identifier: GPL-2.0+
-+
-+obj-y += cpu.o
-+obj-y += dram.o
---- /dev/null
-+++ b/arch/riscv/cpu/thead/cpu.c
-@@ -0,0 +1,22 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-+ */
-+
-+#include <irq_func.h>
-+#include <asm/cache.h>
-+
-+/*
-+ * cleanup_before_linux() is called just before we call linux
-+ * it prepares the processor for linux
-+ *
-+ * we disable interrupt and caches.
-+ */
-+int cleanup_before_linux(void)
-+{
-+	disable_interrupts();
-+
-+	cache_flush();
-+
-+	return 0;
-+}
---- /dev/null
-+++ b/arch/riscv/cpu/thead/dram.c
-@@ -0,0 +1,22 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-+ */
-+
-+#include <common.h>
-+#include <fdtdec.h>
-+#include <init.h>
-+#include <asm/global_data.h>
-+#include <linux/sizes.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int dram_init(void)
-+{
-+	return fdtdec_setup_mem_size_base();
-+}
-+
-+int dram_init_banksize(void)
-+{
-+	return fdtdec_setup_memory_banksize();
-+}

package/boot/uboot-d1/patches/0002-sunxi-Add-iNet_U70B_rev1_defconfig.patch

@@ -0,0 +1,46 @@
+From ddb1f06d1c7758c538e286c0c7a9c8545d2af6b1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 20 Nov 2021 13:26:36 -0600
+Subject: [PATCH 02/90] sunxi: Add iNet_U70B_rev1_defconfig
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ configs/iNet_U70B_rev1_defconfig | 32 ++++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 configs/iNet_U70B_rev1_defconfig
+
+--- /dev/null
++++ b/configs/iNet_U70B_rev1_defconfig
+@@ -0,0 +1,32 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
++# CONFIG_SPL_SERIAL is not set
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_A33=y
++CONFIG_DRAM_CLK=480
++CONFIG_DRAM_ZQ=31675
++CONFIG_DRAM_ODT_EN=y
++CONFIG_MMC0_CD_PIN="PB4"
++CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
++CONFIG_VIDEO_LCD_DCLK_PHASE=0
++CONFIG_VIDEO_LCD_POWER="PH7"
++CONFIG_VIDEO_LCD_BL_EN="PH6"
++CONFIG_VIDEO_LCD_BL_PWM="PH0"
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_CMD_BIND=y
++CONFIG_CMD_CLK=y
++CONFIG_CMD_PWM=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_WDT=y
++CONFIG_CMD_PMIC=y
++CONFIG_CMD_REGULATOR=y
++# CONFIG_NET is not set
++CONFIG_AXP_GPIO=y
++CONFIG_REGULATOR_AXP=y
++CONFIG_REGULATOR_AXP_USB_POWER=y
++CONFIG_AXP_DLDO1_VOLT=3300
++CONFIG_DM_PWM=y
++CONFIG_PWM_SUNXI=y
++# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
++CONFIG_USB_MUSB_HOST=y

package/boot/uboot-d1/patches/0003-Adapt-iNet-U70B-REV01-for-development-FEL-serial.patch

@@ -0,0 +1,85 @@
+From ef808412055d1ef6fe77ff130d3f5a9432fef2d7 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 3 May 2022 22:35:12 -0500
+Subject: [PATCH 03/90] Adapt iNet U70B REV01 for development (FEL + serial)
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts | 11 +++++++++++
+ configs/iNet_U70B_rev1_defconfig          | 14 +++++---------
+ 2 files changed, 16 insertions(+), 9 deletions(-)
+
+--- a/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
++++ b/arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts
+@@ -11,6 +11,7 @@
+ 
+ 	aliases {
+ 		ethernet0 = &rtl8723cs;
++		serial0 = &uart0;
+ 	};
+ 
+ 	panel: panel {
+@@ -76,6 +77,10 @@
+ 	};
+ };
+ 
++&mmc0 {
++	status = "disabled";
++};
++
+ &mmc1 {
+ 	pinctrl-0 = <&mmc1_pg_pins>;
+ 	pinctrl-names = "default";
+@@ -158,6 +163,12 @@
+ 	status = "okay";
+ };
+ 
++&uart0 {
++	pinctrl-0 = <&uart0_pf_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+ 	pinctrl-names = "default";
+--- a/configs/iNet_U70B_rev1_defconfig
++++ b/configs/iNet_U70B_rev1_defconfig
+@@ -1,12 +1,12 @@
+ CONFIG_ARM=y
+ CONFIG_ARCH_SUNXI=y
+ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-inet-u70b-rev1"
+-# CONFIG_SPL_SERIAL is not set
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=480
+ CONFIG_DRAM_ZQ=31675
+ CONFIG_DRAM_ODT_EN=y
++CONFIG_UART0_PORT_F=y
+ CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:158,ri:162,up:25,lo:10,hs:20,vs:3,sync:3,vmode:0"
+ CONFIG_VIDEO_LCD_DCLK_PHASE=0
+@@ -14,19 +14,15 @@ CONFIG_VIDEO_LCD_POWER="PH7"
+ CONFIG_VIDEO_LCD_BL_EN="PH6"
+ CONFIG_VIDEO_LCD_BL_PWM="PH0"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+-CONFIG_CMD_BIND=y
+-CONFIG_CMD_CLK=y
+-CONFIG_CMD_PWM=y
+-CONFIG_CMD_I2C=y
+-CONFIG_CMD_WDT=y
++CONFIG_PREBOOT="fastboot usb 0"
+ CONFIG_CMD_PMIC=y
+ CONFIG_CMD_REGULATOR=y
+-# CONFIG_NET is not set
+ CONFIG_AXP_GPIO=y
+ CONFIG_REGULATOR_AXP=y
+ CONFIG_REGULATOR_AXP_USB_POWER=y
+ CONFIG_AXP_DLDO1_VOLT=3300
+ CONFIG_DM_PWM=y
+ CONFIG_PWM_SUNXI=y
+-# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
+-CONFIG_USB_MUSB_HOST=y
++CONFIG_REMOTEPROC_SUN6I_AR100=y
++CONFIG_USB_MUSB_GADGET=y
++CONFIG_WATCHDOG_AUTOSTART=y

package/boot/uboot-d1/patches/0003-riscv-cpu-thead-Add-extension-CSR-definitions.patch

@@ -1,53 +0,0 @@
-From 63ba3ddfaddeb963a959e709aac249d61f51bb3f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 5 Feb 2023 09:56:34 -0600
-Subject: [PATCH 03/68] riscv: cpu: thead: Add extension CSR definitions
-
-T-HEAD C9xx and E9xx CPUs contain some extra CSRs which control the
-branch predictor and cache-related functionality.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/cpu/thead/thead_csr.h | 36 ++++++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
- create mode 100644 arch/riscv/cpu/thead/thead_csr.h
-
---- /dev/null
-+++ b/arch/riscv/cpu/thead/thead_csr.h
-@@ -0,0 +1,36 @@
-+/* SPDX-License-Identifier: GPL-2.0+ */
-+
-+#ifndef _THEAD_CSR_H_
-+#define _THEAD_CSR_H_
-+
-+#define CSR_MXSTATUS		0x7c0
-+#define CSR_MHCR		0x7c1
-+#define CSR_MHINT		0x7c5
-+
-+#define MXSTATUS_THEADISAEE	BIT(22) /* T-HEAD ISA extensions enable */
-+#define MXSTATUS_MM		BIT(15) /* misaligned access enable */
-+
-+#define MHCR_IE			BIT(0)	/* icache enable */
-+#define MHCR_DE			BIT(1)	/* dcache enable */
-+#define MHCR_WA			BIT(2)	/* dcache write allocate */
-+#define MHCR_WB			BIT(3)	/* dcache write back */
-+#define MHCR_RS			BIT(4)	/* return stack enable */
-+#define MHCR_BPE		BIT(5)	/* branch prediction enable */
-+#define MHCR_BTB_C906		BIT(6)	/* branch target prediction enable */
-+#define MHCR_WBR		BIT(8)	/* write burst enable */
-+#define MHCR_BTB_E906		BIT(12) /* branch target prediction enable */
-+
-+#define MHINT_DPLD		BIT(2)	/* dcache prefetch enable */
-+#define MHINT_AMR_PAGE		(0x0 << 3)
-+#define MHINT_AMR_LIMIT_3	(0x1 << 3)
-+#define MHINT_AMR_LIMIT_64	(0x2 << 3)
-+#define MHINT_AMR_LIMIT_128	(0x3 << 3)
-+#define MHINT_IPLD		BIT(8)	/* icache prefetch enable */
-+#define MHINT_IWPE		BIT(9)	/* icache way prediction enable */
-+#define MHINT_D_DIS_PREFETCH_2	(0x0 << 13)
-+#define MHINT_D_DIS_PREFETCH_4	(0x1 << 13)
-+#define MHINT_D_DIS_PREFETCH_8	(0x2 << 13)
-+#define MHINT_D_DIS_PREFETCH_16	(0x3 << 13)
-+#define MHINT_AEE		BIT(20) /* accurate exception enable */
-+
-+#endif /* _THEAD_CSR_H_ */

package/boot/uboot-d1/patches/0004-ARM-dts-sun6i-mixtile-loftq-Add-USB1-VBUS-regulator.patch

@@ -0,0 +1,54 @@
+From 40a0ec0fdb6a110d69151de5480148772877f267 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 20:39:33 -0500
+Subject: [PATCH 04/90] ARM: dts: sun6i: mixtile-loftq: Add USB1 VBUS regulator
+
+This board is configured with CONFIG_USB1_VBUS_PIN="PH24", but no
+regulator exists in its device tree. Add the regulator, so USB will
+continue to work when the PHY driver switches to using the regulator
+uclass instead of a GPIO.
+
+Update the device tree here because it does not exist in Linux.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
++++ b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
+@@ -6,6 +6,9 @@
+  */
+ 
+ /dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++
+ #include "sun6i-a31.dtsi"
+ 
+ / {
+@@ -19,6 +22,15 @@
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
++	};
+ };
+ 
+ &ehci0 {
+@@ -56,3 +68,8 @@
+ 	pinctrl-0 = <&uart0_ph_pins>;
+ 	status = "okay";
+ };
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};

package/boot/uboot-d1/patches/0004-riscv-cpu-thead-Initialize-extension-CSRs.patch

@@ -1,72 +0,0 @@
-From 5159250118c6f58a469fc9185ea4227f852e51d0 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 5 Feb 2023 09:44:05 -0600
-Subject: [PATCH 04/68] riscv: cpu: thead: Initialize extension CSRs
-
-Enable the T-HEAD ISA extensions, as these are required to use the cache
-maintenance instructions. Enable the branch predictor and BTB to improve
-performance. Some bits are only available on specific CPU models, so
-provide Kconfig symbols for selecting the right model.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/Kconfig           |  1 +
- arch/riscv/cpu/thead/Kconfig |  7 +++++++
- arch/riscv/cpu/thead/cpu.c   | 21 +++++++++++++++++++++
- 3 files changed, 29 insertions(+)
- create mode 100644 arch/riscv/cpu/thead/Kconfig
-
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -89,6 +89,7 @@ source "arch/riscv/cpu/fu540/Kconfig"
- source "arch/riscv/cpu/fu740/Kconfig"
- source "arch/riscv/cpu/generic/Kconfig"
- source "arch/riscv/cpu/jh7110/Kconfig"
-+source "arch/riscv/cpu/thead/Kconfig"
- 
- # architecture-specific options below
- 
---- /dev/null
-+++ b/arch/riscv/cpu/thead/Kconfig
-@@ -0,0 +1,7 @@
-+# SPDX-License-Identifier: GPL-2.0+
-+
-+config THEAD_C906
-+	bool
-+
-+config THEAD_E906
-+	bool
---- a/arch/riscv/cpu/thead/cpu.c
-+++ b/arch/riscv/cpu/thead/cpu.c
-@@ -5,6 +5,10 @@
- 
- #include <irq_func.h>
- #include <asm/cache.h>
-+#include <asm/csr.h>
-+#include <linux/bitops.h>
-+
-+#include "thead_csr.h"
- 
- /*
-  * cleanup_before_linux() is called just before we call linux
-@@ -20,3 +24,20 @@ int cleanup_before_linux(void)
- 
- 	return 0;
- }
-+
-+void harts_early_init(void)
-+{
-+	if (!CONFIG_IS_ENABLED(RISCV_MMODE))
-+		return;
-+
-+	csr_set(CSR_MXSTATUS, MXSTATUS_THEADISAEE | MXSTATUS_MM);
-+	if (IS_ENABLED(THEAD_C906)) {
-+		csr_set(CSR_MHCR,
-+			MHCR_BTB_C906 | MHCR_BPE | MHCR_RS | MHCR_WB | MHCR_WA);
-+		csr_set(CSR_MHINT, MHINT_IWPE | MHINT_IPLD | MHINT_IPLD);
-+	}
-+	if (IS_ENABLED(THEAD_E906)) {
-+		csr_set(CSR_MHCR,
-+			MHCR_BTB_E906 | MHCR_BPE | MHCR_RS | MHCR_WB | MHCR_WA);
-+	}
-+}

package/boot/uboot-d1/patches/0005-power-regulator-Add-a-driver-for-the-AXP-USB-power-s.patch

@@ -0,0 +1,97 @@
+From e07c1d516c1a7842510d22a7cf88666d500a9a9a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 22 Aug 2021 21:35:45 -0500
+Subject: [PATCH 05/90] power: regulator: Add a driver for the AXP USB power
+ supply
+
+This driver reports the presence/absence of voltage on the PMIC's USB
+VBUS pin. This information is used by the USB PHY driver. The
+corresponding Linux driver uses the power supply class, which does not
+exist in U-Boot. UCLASS_REGULATOR seems to be the closest match.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/regulator/Kconfig         |  7 ++++
+ drivers/power/regulator/Makefile        |  1 +
+ drivers/power/regulator/axp_usb_power.c | 49 +++++++++++++++++++++++++
+ 3 files changed, 57 insertions(+)
+ create mode 100644 drivers/power/regulator/axp_usb_power.c
+
+--- a/drivers/power/regulator/Kconfig
++++ b/drivers/power/regulator/Kconfig
+@@ -43,6 +43,13 @@ config REGULATOR_AS3722
+ 	  but does not yet support change voltages. Currently this must be
+ 	  done using direct register writes to the PMIC.
+ 
++config REGULATOR_AXP_USB_POWER
++	bool "Enable driver for X-Powers AXP PMIC USB power supply"
++	depends on DM_REGULATOR && PMIC_AXP
++	help
++	  Enable support for reading the USB power supply status from
++	  X-Powers AXP2xx and AXP8xx PMICs.
++
+ config DM_REGULATOR_BD71837
+ 	bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
+ 	depends on DM_REGULATOR && DM_PMIC_BD71837
+--- a/drivers/power/regulator/Makefile
++++ b/drivers/power/regulator/Makefile
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
+ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
+ obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
++obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
+ obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
+ obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
+--- /dev/null
++++ b/drivers/power/regulator/axp_usb_power.c
+@@ -0,0 +1,49 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <dm/device.h>
++#include <errno.h>
++#include <power/pmic.h>
++#include <power/regulator.h>
++
++#define AXP_POWER_STATUS		0x00
++#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
++
++static int axp_usb_power_get_enable(struct udevice *dev)
++{
++	int ret;
++
++	ret = pmic_reg_read(dev->parent, AXP_POWER_STATUS);
++	if (ret < 0)
++		return ret;
++
++	return !!(ret & AXP_POWER_STATUS_VBUS_PRESENT);
++}
++
++static const struct dm_regulator_ops axp_usb_power_ops = {
++	.get_enable		= axp_usb_power_get_enable,
++};
++
++static int axp_usb_power_probe(struct udevice *dev)
++{
++	struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev);
++
++	uc_plat->type = REGULATOR_TYPE_FIXED;
++
++	return 0;
++}
++
++static const struct udevice_id axp_usb_power_ids[] = {
++	{ .compatible = "x-powers,axp202-usb-power-supply" },
++	{ .compatible = "x-powers,axp221-usb-power-supply" },
++	{ .compatible = "x-powers,axp223-usb-power-supply" },
++	{ .compatible = "x-powers,axp813-usb-power-supply" },
++	{ }
++};
++
++U_BOOT_DRIVER(axp_usb_power) = {
++	.name		= "axp_usb_power",
++	.id		= UCLASS_REGULATOR,
++	.of_match	= axp_usb_power_ids,
++	.probe		= axp_usb_power_probe,
++	.ops		= &axp_usb_power_ops,
++};

package/boot/uboot-d1/patches/0005-riscv-cpu-thead-Add-CPU-specific-cache-operations.patch

@@ -1,134 +0,0 @@
-From a2615b3b161929df1ae151585d4638cc4ab09bf9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 4 Feb 2023 14:29:20 -0600
-Subject: [PATCH 05/68] riscv: cpu: thead: Add CPU-specific cache operations
-
-Use the vendor CSRs for enabling/disabling the caches, and the ISA
-extension for cache maintenance.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/cpu/thead/Kconfig  |  2 +
- arch/riscv/cpu/thead/Makefile |  1 +
- arch/riscv/cpu/thead/cache.c  | 96 +++++++++++++++++++++++++++++++++++
- 3 files changed, 99 insertions(+)
- create mode 100644 arch/riscv/cpu/thead/cache.c
-
---- a/arch/riscv/cpu/thead/Kconfig
-+++ b/arch/riscv/cpu/thead/Kconfig
-@@ -2,6 +2,8 @@
- 
- config THEAD_C906
- 	bool
-+	select SYS_CACHE_SHIFT_6
- 
- config THEAD_E906
- 	bool
-+	select SYS_CACHE_SHIFT_5
---- a/arch/riscv/cpu/thead/Makefile
-+++ b/arch/riscv/cpu/thead/Makefile
-@@ -1,4 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0+
- 
-+obj-y += cache.o
- obj-y += cpu.o
- obj-y += dram.o
---- /dev/null
-+++ b/arch/riscv/cpu/thead/cache.c
-@@ -0,0 +1,96 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <cpu_func.h>
-+#include <asm/cache.h>
-+#include <asm/csr.h>
-+#include <linux/bitops.h>
-+
-+#include "thead_csr.h"
-+
-+#define THEAD_SYNC_I		".long 0x01a0000b"
-+#define THEAD_DCACHE_CIALL	".long 0x0030000b"
-+#define THEAD_DCACHE_CIPA_A0	".long 0x02b5000b"
-+#define THEAD_DCACHE_IALL	".long 0x0020000b"
-+#define THEAD_DCACHE_IPA_A0	".long 0x02a5000b"
-+#define THEAD_ICACHE_IPA_A0	".long 0x0385000b"
-+
-+static inline void sync_i(void)
-+{
-+	asm volatile (THEAD_SYNC_I ::: "memory");
-+}
-+
-+void flush_dcache_all(void)
-+{
-+	asm volatile (THEAD_DCACHE_CIALL ::: "memory");
-+	sync_i();
-+}
-+
-+void flush_dcache_range(unsigned long start, unsigned long end)
-+{
-+	register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
-+
-+	for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
-+		asm volatile (THEAD_DCACHE_CIPA_A0 :: "r" (addr) : "memory");
-+	sync_i();
-+}
-+
-+void invalidate_dcache_all(void)
-+{
-+	asm volatile (THEAD_DCACHE_IALL ::: "memory");
-+	sync_i();
-+}
-+
-+void invalidate_dcache_range(unsigned long start, unsigned long end)
-+{
-+	register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
-+
-+	for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
-+		asm volatile (THEAD_DCACHE_IPA_A0 :: "r" (addr) : "memory");
-+	sync_i();
-+}
-+
-+void invalidate_icache_range(unsigned long start, unsigned long end)
-+{
-+	register ulong addr asm ("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
-+
-+	for (; addr < end; addr += CONFIG_SYS_CACHELINE_SIZE)
-+		asm volatile (THEAD_ICACHE_IPA_A0 :: "r" (addr) : "memory");
-+	sync_i();
-+}
-+
-+#if CONFIG_IS_ENABLED(RISCV_MMODE)
-+
-+void icache_enable(void)
-+{
-+	invalidate_icache_all();
-+	csr_set(CSR_MHCR, MHCR_IE);
-+}
-+
-+void icache_disable(void)
-+{
-+	csr_clear(CSR_MHCR, MHCR_IE);
-+}
-+
-+int icache_status(void)
-+{
-+	return csr_read(CSR_MHCR) & MHCR_IE;
-+}
-+
-+void dcache_enable(void)
-+{
-+	invalidate_dcache_all();
-+	csr_set(CSR_MHCR, MHCR_DE);
-+}
-+
-+void dcache_disable(void)
-+{
-+	flush_dcache_all();
-+	csr_clear(CSR_MHCR, MHCR_DE);
-+}
-+
-+int dcache_status(void)
-+{
-+	return csr_read(CSR_MHCR) & MHCR_DE;
-+}
-+
-+#endif

package/boot/uboot-d1/patches/0006-gpio-axp-sunxi-Remove-virtual-VBUS-detection-GPIO.patch

@@ -0,0 +1,122 @@
+From c750151e1107a8d46ca0f9bd30c1da276b142ec1 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 18:02:54 -0500
+Subject: [PATCH 06/90] gpio: axp/sunxi: Remove virtual VBUS detection GPIO
+
+Now that this functionality is modeled using the device tree and
+regulator uclass, the named GPIO is not referenced anywhere. Remove it.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/gpio.h |  1 -
+ drivers/gpio/axp_gpio.c                | 21 ++++-----------------
+ drivers/gpio/sunxi_gpio.c              |  6 +-----
+ include/axp209.h                       |  1 -
+ include/axp221.h                       |  1 -
+ include/axp809.h                       |  1 -
+ include/axp818.h                       |  1 -
+ 7 files changed, 5 insertions(+), 27 deletions(-)
+
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -209,7 +209,6 @@ enum sunxi_gpio_number {
+ 
+ /* Virtual AXP0 GPIOs */
+ #define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+-#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
+ #define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+ #define SUNXI_GPIO_AXP0_GPIO_COUNT	6
+ 
+--- a/drivers/gpio/axp_gpio.c
++++ b/drivers/gpio/axp_gpio.c
+@@ -36,18 +36,11 @@ static int axp_gpio_direction_input(stru
+ {
+ 	u8 reg;
+ 
+-	switch (pin) {
+-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
+-		return 0;
+-#endif
+-	default:
+-		reg = axp_get_gpio_ctrl_reg(pin);
+-		if (reg == 0)
+-			return -EINVAL;
++	reg = axp_get_gpio_ctrl_reg(pin);
++	if (reg == 0)
++		return -EINVAL;
+ 
+-		return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
+-	}
++	return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
+ }
+ 
+ static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+@@ -83,12 +76,6 @@ static int axp_gpio_get_value(struct ude
+ 	int ret;
+ 
+ 	switch (pin) {
+-#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+-	case SUNXI_GPIO_AXP0_VBUS_DETECT:
+-		ret = pmic_bus_read(AXP_POWER_STATUS, &val);
+-		mask = AXP_POWER_STATUS_VBUS_PRESENT;
+-		break;
+-#endif
+ #ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC
+ 	/* Only available on later PMICs */
+ 	case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+--- a/drivers/gpio/sunxi_gpio.c
++++ b/drivers/gpio/sunxi_gpio.c
+@@ -117,11 +117,7 @@ int sunxi_name_to_gpio(const char *name)
+ #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+ 	char lookup[8];
+ 
+-	if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
+-		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+-			SUNXI_GPIO_AXP0_VBUS_DETECT);
+-		name = lookup;
+-	} else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
++	if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+ 		sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+ 			SUNXI_GPIO_AXP0_VBUS_ENABLE);
+ 		name = lookup;
+--- a/include/axp209.h
++++ b/include/axp209.h
+@@ -77,7 +77,6 @@ enum axp209_reg {
+ #ifdef CONFIG_AXP209_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_GPIO0_CTRL			0x90
+ #define AXP_GPIO1_CTRL			0x92
+ #define AXP_GPIO2_CTRL			0x93
+--- a/include/axp221.h
++++ b/include/axp221.h
+@@ -53,7 +53,6 @@
+ #ifdef CONFIG_AXP221_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f
+--- a/include/axp809.h
++++ b/include/axp809.h
+@@ -47,7 +47,6 @@
+ #ifdef CONFIG_AXP809_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f
+--- a/include/axp818.h
++++ b/include/axp818.h
+@@ -61,7 +61,6 @@
+ #ifdef CONFIG_AXP818_POWER
+ #define AXP_POWER_STATUS		0x00
+ #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
+-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
+ #define AXP_VBUS_IPSOUT			0x30
+ #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+ #define AXP_MISC_CTRL			0x8f

package/boot/uboot-d1/patches/0007-power-regulator-Add-a-driver-for-the-AXP-PMIC-drivev.patch

@@ -1,65 +1,60 @@
-From 967499870f79fb2f0cfa006186d44ba1330eb2e2 Mon Sep 17 00:00:00 2001
+From 25434a394705d2de92c50981e31347db4074204a Mon Sep 17 00:00:00 2001
 From: Samuel Holland <samuel@sholland.org>
 Date: Thu, 26 Aug 2021 21:32:15 -0500
-Subject: [PATCH 43/68] power: regulator: Add a driver for the AXP PMIC
+Subject: [PATCH 07/90] power: regulator: Add a driver for the AXP PMIC
  drivevbus
 
-AXP PMICs have a pin which can either report the USB VBUS state, or
-driving a regulator that supplies USB VBUS. Add a regulator driver for
-controlling this pin. The selection between input and output is done via
-the x-powers,drive-vbus-en pin on the PMIC (parent) node.
+The first AXP regulator converted to use the regulator uclass is the
+drivevbus switch, since it is used by the USB PHY driver.
 
 Signed-off-by: Samuel Holland <samuel@sholland.org>
 ---
- drivers/power/pmic/axp.c                |  1 +
- drivers/power/regulator/Kconfig         |  7 +++
+ drivers/power/regulator/Kconfig         | 14 ++++++
  drivers/power/regulator/Makefile        |  1 +
- drivers/power/regulator/axp_drivevbus.c | 57 +++++++++++++++++++++++++
- 4 files changed, 66 insertions(+)
- create mode 100644 drivers/power/regulator/axp_drivevbus.c
+ drivers/power/regulator/axp_regulator.c | 58 +++++++++++++++++++++++++
+ 3 files changed, 73 insertions(+)
+ create mode 100644 drivers/power/regulator/axp_regulator.c
 
---- a/drivers/power/pmic/axp.c
-+++ b/drivers/power/pmic/axp.c
-@@ -51,6 +51,7 @@ static const struct pmic_child_info axp_
- 	{ "cldo",	"axp_regulator" },
- 	{ "dc",		"axp_regulator" },
- 	{ "dldo",	"axp_regulator" },
-+	{ "drivevbus",	"axp_drivevbus" },
- 	{ "eldo",	"axp_regulator" },
- 	{ "fldo",	"axp_regulator" },
- 	{ "ldo",	"axp_regulator" },
 --- a/drivers/power/regulator/Kconfig
 +++ b/drivers/power/regulator/Kconfig
-@@ -57,6 +57,13 @@ config SPL_REGULATOR_AXP
- 	  Enable support in SPL for the regulators (DCDCs, LDOs) in the
- 	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
+@@ -43,6 +43,20 @@ config REGULATOR_AS3722
+ 	  but does not yet support change voltages. Currently this must be
+ 	  done using direct register writes to the PMIC.
  
-+config REGULATOR_AXP_DRIVEVBUS
-+	bool "Enable driver for X-Powers AXP PMIC drivevbus"
++config REGULATOR_AXP
++	bool "Enable driver for X-Powers AXP PMIC regulators"
 +	depends on DM_REGULATOR && PMIC_AXP
 +	help
-+	  Enable support for sensing or driving the USB VBUS on
-+	  X-Powers AXP2xx and AXP8xx PMICs.
++	  Enable support for the regulators (DCDCs, LDOs) in the
++	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
++
++config SPL_REGULATOR_AXP
++	bool "Enable driver for X-Powers AXP PMIC regulators in SPL"
++	depends on SPL_DM_REGULATOR && SPL_PMIC_AXP
++	help
++	  Enable support in SPL for the regulators (DCDCs, LDOs) in the
++	  X-Powers AXP152, AXP2xx, and AXP8xx PMICs.
 +
  config REGULATOR_AXP_USB_POWER
  	bool "Enable driver for X-Powers AXP PMIC USB power supply"
  	depends on DM_REGULATOR && PMIC_AXP
 --- a/drivers/power/regulator/Makefile
 +++ b/drivers/power/regulator/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += reg
+@@ -7,6 +7,7 @@
+ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
  obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
  obj-$(CONFIG_REGULATOR_AS3722)	+= as3722_regulator.o
- obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
-+obj-$(CONFIG_$(SPL_)REGULATOR_AXP_DRIVEVBUS) += axp_drivevbus.o
++obj-$(CONFIG_$(SPL_)REGULATOR_AXP) += axp_regulator.o
  obj-$(CONFIG_$(SPL_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
  obj-$(CONFIG_$(SPL_)DM_REGULATOR_DA9063) += da9063.o
- obj-$(CONFIG_$(SPL_)DM_REGULATOR_MAX77663) += max77663_regulator.o
+ obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 --- /dev/null
-+++ b/drivers/power/regulator/axp_drivevbus.c
-@@ -0,0 +1,57 @@
++++ b/drivers/power/regulator/axp_regulator.c
+@@ -0,0 +1,58 @@
 +// SPDX-License-Identifier: GPL-2.0+
 +
 +#include <dm.h>
++#include <errno.h>
 +#include <power/pmic.h>
 +#include <power/regulator.h>
 +

package/boot/uboot-d1/patches/0008-fdt-Use-correct-parent-in-devfdt_get_addr_index.patch

@@ -1,21 +0,0 @@
-From 1c5558f39481911fdb730fd686e710c7f696f17f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 17 Nov 2022 22:08:39 -0600
-Subject: [PATCH 08/68] fdt: Use correct parent in devfdt_get_addr_index
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/core/fdtaddr.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/core/fdtaddr.c
-+++ b/drivers/core/fdtaddr.c
-@@ -23,7 +23,7 @@ fdt_addr_t devfdt_get_addr_index(const s
- {
- #if CONFIG_IS_ENABLED(OF_REAL)
- 	int offset = dev_of_offset(dev);
--	int parent = dev_of_offset(dev->parent);
-+	int parent = fdt_parent_offset(gd->fdt_blob, offset);
- 	fdt_addr_t addr;
- 
- 	if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {

package/boot/uboot-d1/patches/0008-power-pmic-axp-Probe-the-drivevbus-regulator-from-th.patch

@@ -0,0 +1,41 @@
+From a588c97f146b67bae47099bc419cf10c02eca169 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 21:34:33 -0500
+Subject: [PATCH 08/90] power: pmic: axp: Probe the drivevbus regulator from
+ the DT
+
+Now that some regulator driver exists for this PMIC, add support for
+probing regulator drivers from the device tree subnodes.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/pmic/axp.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/power/pmic/axp.c
++++ b/drivers/power/pmic/axp.c
+@@ -45,14 +45,24 @@ static struct dm_pmic_ops axp_pmic_ops =
+ 	.write		= dm_i2c_write,
+ };
+ 
++static const struct pmic_child_info axp_pmic_child_info[] = {
++	{ "drivevbus",	"axp_drivevbus"	},
++	{ }
++};
++
+ static int axp_pmic_bind(struct udevice *dev)
+ {
++	ofnode regulators_node;
+ 	int ret;
+ 
+ 	ret = dm_scan_fdt_dev(dev);
+ 	if (ret)
+ 		return ret;
+ 
++	regulators_node = dev_read_subnode(dev, "regulators");
++	if (ofnode_valid(regulators_node))
++		pmic_bind_children(dev, regulators_node, axp_pmic_child_info);
++
+ 	if (CONFIG_IS_ENABLED(SYSRESET)) {
+ 		ret = device_bind_driver_to_node(dev, "axp_sysreset", "axp_sysreset",
+ 						 dev_ofnode(dev), NULL);

package/boot/uboot-d1/patches/0009-phy-sun4i-usb-Control-USB-supplies-via-regulator-ucl.patch

@@ -1,7 +1,7 @@
-From 5ea3e3e37ec14a1d90a6764879c38d80f4ffe008 Mon Sep 17 00:00:00 2001
+From e8fb34342dfb79cd2059431dd1a0f03202a244ca Mon Sep 17 00:00:00 2001
 From: Samuel Holland <samuel@sholland.org>
 Date: Thu, 26 Aug 2021 22:11:37 -0500
-Subject: [PATCH 45/68] phy: sun4i-usb: Control supplies via the regulator
+Subject: [PATCH 09/90] phy: sun4i-usb: Control USB supplies via regulator
  uclass
 
 The device tree binding for the PHY provides VBUS supplies as regulator
@@ -53,7 +53,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
 
 --- a/drivers/phy/allwinner/phy-sun4i-usb.c
 +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
-@@ -87,27 +87,22 @@ struct sun4i_usb_phy_cfg {
+@@ -97,27 +97,22 @@ struct sun4i_usb_phy_cfg {
  };
  
  struct sun4i_usb_phy_info {
@@ -81,7 +81,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  		.gpio_vbus_det = NULL,
  		.gpio_id_det = NULL,
  	},
-@@ -115,12 +110,12 @@ struct sun4i_usb_phy_info {
+@@ -125,11 +120,11 @@ struct sun4i_usb_phy_info {
  
  struct sun4i_usb_phy_plat {
  	void __iomem *pmu;
@@ -89,13 +89,12 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  	struct gpio_desc gpio_vbus_det;
  	struct gpio_desc gpio_id_det;
  	struct clk clocks;
- 	struct clk clk2;
  	struct reset_ctl resets;
 +	struct udevice *vbus;
  	int id;
  };
  
-@@ -209,6 +204,7 @@ static int sun4i_usb_phy_power_on(struct
+@@ -218,14 +213,18 @@ static int sun4i_usb_phy_power_on(struct
  {
  	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
@@ -103,8 +102,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  
  	if (initial_usb_scan_delay) {
  		mdelay(initial_usb_scan_delay);
-@@ -221,8 +217,11 @@ static int sun4i_usb_phy_power_on(struct
- 		return 0;
+ 		initial_usb_scan_delay = 0;
  	}
  
 -	if (dm_gpio_is_valid(&usb_phy->gpio_vbus))
@@ -117,7 +115,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  
  	return 0;
  }
-@@ -231,9 +230,13 @@ static int sun4i_usb_phy_power_off(struc
+@@ -234,9 +233,13 @@ static int sun4i_usb_phy_power_off(struc
  {
  	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
@@ -133,12 +131,12 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  
  	return 0;
  }
-@@ -483,22 +486,16 @@ static int sun4i_usb_phy_probe(struct ud
+@@ -450,22 +453,16 @@ static int sun4i_usb_phy_probe(struct ud
  	for (i = 0; i < data->cfg->num_phys; i++) {
  		struct sun4i_usb_phy_plat *phy = &plat[i];
  		struct sun4i_usb_phy_info *info = &phy_info[i];
 -		char name[16];
-+		char name[32];
++		char name[20];
  
  		if (data->cfg->missing_phys & BIT(i))
  			continue;

package/boot/uboot-d1/patches/0010-sunxi-Remove-obsolete-USBx_VBUS_PIN-Kconfig-symbols.patch

@@ -0,0 +1,58 @@
+From 649bb7845e30805c66f62fc5725c4dbf350f21cb Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 26 Aug 2021 22:26:40 -0500
+Subject: [PATCH 10/90] sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols
+
+Now that the USB PHY driver uses the device tree to get VBUS supply
+regulators, these Kconfig symbols are unused. Remove them.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/mach-sunxi/Kconfig | 29 -----------------------------
+ 1 file changed, 29 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -693,13 +693,6 @@ config MMC_SUNXI_SLOT_EXTRA
+ 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
+ 	support for this.
+ 
+-config USB0_VBUS_PIN
+-	string "Vbus enable pin for usb0 (otg)"
+-	default ""
+-	---help---
+-	Set the Vbus enable pin for usb0 (otg). This takes a string in the
+-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+-
+ config USB0_VBUS_DET
+ 	string "Vbus detect pin for usb0 (otg)"
+ 	default ""
+@@ -714,28 +707,6 @@ config USB0_ID_DET
+ 	Set the ID detect pin for usb0 (otg). This takes a string in the
+ 	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+ 
+-config USB1_VBUS_PIN
+-	string "Vbus enable pin for usb1 (ehci0)"
+-	default "PH6" if MACH_SUN4I || MACH_SUN7I
+-	default "PH27" if MACH_SUN6I
+-	---help---
+-	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+-	a string in the format understood by sunxi_name_to_gpio, e.g.
+-	PH1 for pin 1 of port H.
+-
+-config USB2_VBUS_PIN
+-	string "Vbus enable pin for usb2 (ehci1)"
+-	default "PH3" if MACH_SUN4I || MACH_SUN7I
+-	default "PH24" if MACH_SUN6I
+-	---help---
+-	See USB1_VBUS_PIN help text.
+-
+-config USB3_VBUS_PIN
+-	string "Vbus enable pin for usb3 (ehci2)"
+-	default ""
+-	---help---
+-	See USB1_VBUS_PIN help text.
+-
+ config I2C0_ENABLE
+ 	bool "Enable I2C/TWI controller 0"
+ 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40

package/boot/uboot-d1/patches/0011-clk-sunxi-Add-support-for-the-D1-CCU.patch

@@ -0,0 +1,393 @@
+From 73d6c82e34e89cfde880d1948b3e0dc714adead8 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 30 Apr 2022 22:34:19 -0500
+Subject: [PATCH 11/90] clk: sunxi: Add support for the D1 CCU
+
+Since the D1 CCU binding is defined, we can add support for its
+gates/resets, following the pattern of the existing drivers.
+
+Series-to: sunxi
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/Kconfig                 |   6 +
+ drivers/clk/sunxi/Makefile                |   1 +
+ drivers/clk/sunxi/clk_d1.c                |  82 ++++++++++++
+ drivers/clk/sunxi/clk_sunxi.c             |   5 +
+ include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
+ include/dt-bindings/reset/sun20i-d1-ccu.h |  77 +++++++++++
+ 6 files changed, 327 insertions(+)
+ create mode 100644 drivers/clk/sunxi/clk_d1.c
+ create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
+ create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
+
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -87,6 +87,12 @@ config CLK_SUN8I_H3
+ 	  This enables common clock driver support for platforms based
+ 	  on Allwinner H3/H5 SoC.
+ 
++config CLK_SUN20I_D1
++	bool "Clock driver for Allwinner D1"
++	help
++	  This enables common clock driver support for platforms based
++	  on Allwinner D1 SoC.
++
+ config CLK_SUN50I_H6
+ 	bool "Clock driver for Allwinner H6"
+ 	default MACH_SUN50I_H6
+--- a/drivers/clk/sunxi/Makefile
++++ b/drivers/clk/sunxi/Makefile
+@@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
+ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
+ obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
+ obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
++obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
+ obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+ obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
+ obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
+--- /dev/null
++++ b/drivers/clk/sunxi/clk_d1.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#include <common.h>
++#include <clk-uclass.h>
++#include <dm.h>
++#include <errno.h>
++#include <clk/sunxi.h>
++#include <dt-bindings/clock/sun20i-d1-ccu.h>
++#include <dt-bindings/reset/sun20i-d1-ccu.h>
++#include <linux/bitops.h>
++
++static struct ccu_clk_gate d1_gates[] = {
++	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
++	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
++	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
++	[CLK_BUS_UART0]		= GATE(0x90c, BIT(0)),
++	[CLK_BUS_UART1]		= GATE(0x90c, BIT(1)),
++	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
++	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
++	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
++	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
++	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
++	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
++	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
++	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
++	[CLK_SPI0]		= GATE(0x940, BIT(31)),
++	[CLK_SPI1]		= GATE(0x944, BIT(31)),
++	[CLK_BUS_SPI0]		= GATE(0x96c, BIT(0)),
++	[CLK_BUS_SPI1]		= GATE(0x96c, BIT(1)),
++
++	[CLK_BUS_EMAC]		= GATE(0x97c, BIT(0)),
++
++	[CLK_USB_OHCI0]		= GATE(0xa70, BIT(31)),
++	[CLK_USB_OHCI1]		= GATE(0xa74, BIT(31)),
++	[CLK_BUS_OHCI0]		= GATE(0xa8c, BIT(0)),
++	[CLK_BUS_OHCI1]		= GATE(0xa8c, BIT(1)),
++	[CLK_BUS_EHCI0]		= GATE(0xa8c, BIT(4)),
++	[CLK_BUS_EHCI1]		= GATE(0xa8c, BIT(5)),
++	[CLK_BUS_OTG]		= GATE(0xa8c, BIT(8)),
++	[CLK_BUS_LRADC]		= GATE(0xa9c, BIT(0)),
++
++	[CLK_RISCV]		= GATE(0xd04, BIT(31)),
++};
++
++static struct ccu_reset d1_resets[] = {
++	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
++	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
++	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
++	[RST_BUS_UART0]		= RESET(0x90c, BIT(16)),
++	[RST_BUS_UART1]		= RESET(0x90c, BIT(17)),
++	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
++	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
++	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
++	[RST_BUS_UART5]		= RESET(0x90c, BIT(21)),
++	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
++	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
++	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
++	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
++	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
++	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
++
++	[RST_BUS_EMAC]		= RESET(0x97c, BIT(16)),
++
++	[RST_USB_PHY0]		= RESET(0xa70, BIT(30)),
++	[RST_USB_PHY1]		= RESET(0xa74, BIT(30)),
++	[RST_BUS_OHCI0]		= RESET(0xa8c, BIT(16)),
++	[RST_BUS_OHCI1]		= RESET(0xa8c, BIT(17)),
++	[RST_BUS_EHCI0]		= RESET(0xa8c, BIT(20)),
++	[RST_BUS_EHCI1]		= RESET(0xa8c, BIT(21)),
++	[RST_BUS_OTG]		= RESET(0xa8c, BIT(24)),
++	[RST_BUS_LRADC]		= RESET(0xa9c, BIT(16)),
++};
++
++const struct ccu_desc d1_ccu_desc = {
++	.gates	= d1_gates,
++	.resets	= d1_resets,
++	.num_gates = ARRAY_SIZE(d1_gates),
++	.num_resets = ARRAY_SIZE(d1_resets),
++};
+--- a/drivers/clk/sunxi/clk_sunxi.c
++++ b/drivers/clk/sunxi/clk_sunxi.c
+@@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_des
+ extern const struct ccu_desc a80_ccu_desc;
+ extern const struct ccu_desc a80_mmc_clk_desc;
+ extern const struct ccu_desc a83t_ccu_desc;
++extern const struct ccu_desc d1_ccu_desc;
+ extern const struct ccu_desc f1c100s_ccu_desc;
+ extern const struct ccu_desc h3_ccu_desc;
+ extern const struct ccu_desc h6_ccu_desc;
+@@ -183,6 +184,10 @@ static const struct udevice_id sunxi_clk
+ 	{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
+ 	  .data = (ulong)&a80_mmc_clk_desc },
+ #endif
++#ifdef CONFIG_CLK_SUN20I_D1
++	{ .compatible = "allwinner,sun20i-d1-ccu",
++	  .data = (ulong)&d1_ccu_desc },
++#endif
+ #ifdef CONFIG_CLK_SUN50I_A64
+ 	{ .compatible = "allwinner,sun50i-a64-ccu",
+ 	  .data = (ulong)&a64_ccu_desc },
+--- /dev/null
++++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
+@@ -0,0 +1,156 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (C) 2020 huangzhenwei@allwinnertech.com
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
++#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
++
++#define CLK_PLL_CPUX		0
++#define CLK_PLL_DDR0		1
++#define CLK_PLL_PERIPH0_4X	2
++#define CLK_PLL_PERIPH0_2X	3
++#define CLK_PLL_PERIPH0_800M	4
++#define CLK_PLL_PERIPH0		5
++#define CLK_PLL_PERIPH0_DIV3	6
++#define CLK_PLL_VIDEO0_4X	7
++#define CLK_PLL_VIDEO0_2X	8
++#define CLK_PLL_VIDEO0		9
++#define CLK_PLL_VIDEO1_4X	10
++#define CLK_PLL_VIDEO1_2X	11
++#define CLK_PLL_VIDEO1		12
++#define CLK_PLL_VE		13
++#define CLK_PLL_AUDIO0_4X	14
++#define CLK_PLL_AUDIO0_2X	15
++#define CLK_PLL_AUDIO0		16
++#define CLK_PLL_AUDIO1		17
++#define CLK_PLL_AUDIO1_DIV2	18
++#define CLK_PLL_AUDIO1_DIV5	19
++#define CLK_CPUX		20
++#define CLK_CPUX_AXI		21
++#define CLK_CPUX_APB		22
++#define CLK_PSI_AHB		23
++#define CLK_APB0		24
++#define CLK_APB1		25
++#define CLK_MBUS		26
++#define CLK_DE			27
++#define CLK_BUS_DE		28
++#define CLK_DI			29
++#define CLK_BUS_DI		30
++#define CLK_G2D			31
++#define CLK_BUS_G2D		32
++#define CLK_CE			33
++#define CLK_BUS_CE		34
++#define CLK_VE			35
++#define CLK_BUS_VE		36
++#define CLK_BUS_DMA		37
++#define CLK_BUS_MSGBOX0		38
++#define CLK_BUS_MSGBOX1		39
++#define CLK_BUS_MSGBOX2		40
++#define CLK_BUS_SPINLOCK	41
++#define CLK_BUS_HSTIMER		42
++#define CLK_AVS			43
++#define CLK_BUS_DBG		44
++#define CLK_BUS_PWM		45
++#define CLK_BUS_IOMMU		46
++#define CLK_DRAM		47
++#define CLK_MBUS_DMA		48
++#define CLK_MBUS_VE		49
++#define CLK_MBUS_CE		50
++#define CLK_MBUS_TVIN		51
++#define CLK_MBUS_CSI		52
++#define CLK_MBUS_G2D		53
++#define CLK_MBUS_RISCV		54
++#define CLK_BUS_DRAM		55
++#define CLK_MMC0		56
++#define CLK_MMC1		57
++#define CLK_MMC2		58
++#define CLK_BUS_MMC0		59
++#define CLK_BUS_MMC1		60
++#define CLK_BUS_MMC2		61
++#define CLK_BUS_UART0		62
++#define CLK_BUS_UART1		63
++#define CLK_BUS_UART2		64
++#define CLK_BUS_UART3		65
++#define CLK_BUS_UART4		66
++#define CLK_BUS_UART5		67
++#define CLK_BUS_I2C0		68
++#define CLK_BUS_I2C1		69
++#define CLK_BUS_I2C2		70
++#define CLK_BUS_I2C3		71
++#define CLK_SPI0		72
++#define CLK_SPI1		73
++#define CLK_BUS_SPI0		74
++#define CLK_BUS_SPI1		75
++#define CLK_EMAC_25M		76
++#define CLK_BUS_EMAC		77
++#define CLK_IR_TX		78
++#define CLK_BUS_IR_TX		79
++#define CLK_BUS_GPADC		80
++#define CLK_BUS_THS		81
++#define CLK_I2S0		82
++#define CLK_I2S1		83
++#define CLK_I2S2		84
++#define CLK_I2S2_ASRC		85
++#define CLK_BUS_I2S0		86
++#define CLK_BUS_I2S1		87
++#define CLK_BUS_I2S2		88
++#define CLK_SPDIF_TX		89
++#define CLK_SPDIF_RX		90
++#define CLK_BUS_SPDIF		91
++#define CLK_DMIC		92
++#define CLK_BUS_DMIC		93
++#define CLK_AUDIO_DAC		94
++#define CLK_AUDIO_ADC		95
++#define CLK_BUS_AUDIO		96
++#define CLK_USB_OHCI0		97
++#define CLK_USB_OHCI1		98
++#define CLK_BUS_OHCI0		99
++#define CLK_BUS_OHCI1		100
++#define CLK_BUS_EHCI0		101
++#define CLK_BUS_EHCI1		102
++#define CLK_BUS_OTG		103
++#define CLK_BUS_LRADC		104
++#define CLK_BUS_DPSS_TOP	105
++#define CLK_HDMI_24M		106
++#define CLK_HDMI_CEC_32K	107
++#define CLK_HDMI_CEC		108
++#define CLK_BUS_HDMI		109
++#define CLK_MIPI_DSI		110
++#define CLK_BUS_MIPI_DSI	111
++#define CLK_TCON_LCD0		112
++#define CLK_BUS_TCON_LCD0	113
++#define CLK_TCON_TV		114
++#define CLK_BUS_TCON_TV		115
++#define CLK_TVE			116
++#define CLK_BUS_TVE_TOP		117
++#define CLK_BUS_TVE		118
++#define CLK_TVD			119
++#define CLK_BUS_TVD_TOP		120
++#define CLK_BUS_TVD		121
++#define CLK_LEDC		122
++#define CLK_BUS_LEDC		123
++#define CLK_CSI_TOP		124
++#define CLK_CSI_MCLK		125
++#define CLK_BUS_CSI		126
++#define CLK_TPADC		127
++#define CLK_BUS_TPADC		128
++#define CLK_BUS_TZMA		129
++#define CLK_DSP			130
++#define CLK_BUS_DSP_CFG		131
++#define CLK_RISCV		132
++#define CLK_RISCV_AXI		133
++#define CLK_BUS_RISCV_CFG	134
++#define CLK_FANOUT_24M		135
++#define CLK_FANOUT_12M		136
++#define CLK_FANOUT_16M		137
++#define CLK_FANOUT_25M		138
++#define CLK_FANOUT_32K		139
++#define CLK_FANOUT_27M		140
++#define CLK_FANOUT_PCLK		141
++#define CLK_FANOUT0		142
++#define CLK_FANOUT1		143
++#define CLK_FANOUT2		144
++
++#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
+--- /dev/null
++++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
+@@ -0,0 +1,77 @@
++/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
++/*
++ * Copyright (c) 2020 huangzhenwei@allwinnertech.com
++ * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
++ */
++
++#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
++#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
++
++#define RST_MBUS		0
++#define RST_BUS_DE		1
++#define RST_BUS_DI		2
++#define RST_BUS_G2D		3
++#define RST_BUS_CE		4
++#define RST_BUS_VE		5
++#define RST_BUS_DMA		6
++#define RST_BUS_MSGBOX0		7
++#define RST_BUS_MSGBOX1		8
++#define RST_BUS_MSGBOX2		9
++#define RST_BUS_SPINLOCK	10
++#define RST_BUS_HSTIMER		11
++#define RST_BUS_DBG		12
++#define RST_BUS_PWM		13
++#define RST_BUS_DRAM		14
++#define RST_BUS_MMC0		15
++#define RST_BUS_MMC1		16
++#define RST_BUS_MMC2		17
++#define RST_BUS_UART0		18
++#define RST_BUS_UART1		19
++#define RST_BUS_UART2		20
++#define RST_BUS_UART3		21
++#define RST_BUS_UART4		22
++#define RST_BUS_UART5		23
++#define RST_BUS_I2C0		24
++#define RST_BUS_I2C1		25
++#define RST_BUS_I2C2		26
++#define RST_BUS_I2C3		27
++#define RST_BUS_SPI0		28
++#define RST_BUS_SPI1		29
++#define RST_BUS_EMAC		30
++#define RST_BUS_IR_TX		31
++#define RST_BUS_GPADC		32
++#define RST_BUS_THS		33
++#define RST_BUS_I2S0		34
++#define RST_BUS_I2S1		35
++#define RST_BUS_I2S2		36
++#define RST_BUS_SPDIF		37
++#define RST_BUS_DMIC		38
++#define RST_BUS_AUDIO		39
++#define RST_USB_PHY0		40
++#define RST_USB_PHY1		41
++#define RST_BUS_OHCI0		42
++#define RST_BUS_OHCI1		43
++#define RST_BUS_EHCI0		44
++#define RST_BUS_EHCI1		45
++#define RST_BUS_OTG		46
++#define RST_BUS_LRADC		47
++#define RST_BUS_DPSS_TOP	48
++#define RST_BUS_HDMI_SUB	49
++#define RST_BUS_HDMI_MAIN	50
++#define RST_BUS_MIPI_DSI	51
++#define RST_BUS_TCON_LCD0	52
++#define RST_BUS_TCON_TV		53
++#define RST_BUS_LVDS0		54
++#define RST_BUS_TVE		55
++#define RST_BUS_TVE_TOP		56
++#define RST_BUS_TVD		57
++#define RST_BUS_TVD_TOP		58
++#define RST_BUS_LEDC		59
++#define RST_BUS_CSI		60
++#define RST_BUS_TPADC		61
++#define RST_DSP			62
++#define RST_BUS_DSP_CFG		63
++#define RST_BUS_DSP_DBG		64
++#define RST_BUS_RISCV_CFG	65
++
++#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */

package/boot/uboot-d1/patches/0012-gpio-axp-Remove-virtual-VBUS-enable-GPIO.patch

@@ -1,7 +1,7 @@
-From 9882140622a7e95e5bf398b3582066fa04931472 Mon Sep 17 00:00:00 2001
+From cbb281e0ec847b9de41970e470348b3534bb9a9f Mon Sep 17 00:00:00 2001
 From: Samuel Holland <samuel@sholland.org>
 Date: Thu, 26 Aug 2021 18:02:54 -0500
-Subject: [PATCH 47/68] gpio: axp: Remove virtual VBUS enable GPIO
+Subject: [PATCH 12/90] gpio: axp: Remove virtual VBUS enable GPIO
 
 Now that this functionality is modeled using the device tree and
 regulator uclass, the named GPIO is not referenced anywhere. Remove
@@ -9,19 +9,50 @@ it, along with the rest of the support for AXP virtual GPIOs.
 
 Signed-off-by: Samuel Holland <samuel@sholland.org>
 ---
- drivers/gpio/axp_gpio.c   | 75 +++++++++++----------------------------
- drivers/gpio/sunxi_gpio.c |  8 -----
- include/axp221.h          |  4 ---
- include/axp809.h          |  4 ---
- include/axp818.h          |  4 ---
- include/sunxi_gpio.h      |  8 -----
+ arch/arm/include/asm/arch-sunxi/gpio.h |  8 ---
+ drivers/gpio/axp_gpio.c                | 75 ++++++++------------------
+ drivers/gpio/sunxi_gpio.c              |  8 ---
+ include/axp221.h                       |  4 --
+ include/axp809.h                       |  4 --
+ include/axp818.h                       |  4 --
  6 files changed, 21 insertions(+), 82 deletions(-)
 
+--- a/arch/arm/include/asm/arch-sunxi/gpio.h
++++ b/arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -111,7 +111,6 @@ enum sunxi_gpio_number {
+ 	SUNXI_GPIO_L_START = 352,
+ 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+ 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
+-	SUNXI_GPIO_AXP0_START = 1024,
+ };
+ 
+ /* SUNXI GPIO number definitions */
+@@ -128,8 +127,6 @@ enum sunxi_gpio_number {
+ #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
+ #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
+ 
+-#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
+-
+ /* GPIO pin function config */
+ #define SUNXI_GPIO_INPUT	0
+ #define SUNXI_GPIO_OUTPUT	1
+@@ -207,11 +204,6 @@ enum sunxi_gpio_number {
+ #define SUNXI_GPIO_PULL_UP	1
+ #define SUNXI_GPIO_PULL_DOWN	2
+ 
+-/* Virtual AXP0 GPIOs */
+-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+-#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+-#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
+-
+ struct sunxi_gpio_plat {
+ 	struct sunxi_gpio	*regs;
+ 	char			bank_name[3];
 --- a/drivers/gpio/axp_gpio.c
 +++ b/drivers/gpio/axp_gpio.c
-@@ -16,6 +16,9 @@
+@@ -15,6 +15,9 @@
+ #include <dm/root.h>
  #include <errno.h>
- #include <sunxi_gpio.h>
  
 +#define AXP_GPIO_PREFIX			"AXP0-"
 +#define AXP_GPIO_COUNT			4
@@ -29,7 +60,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
  
  static u8 axp_get_gpio_ctrl_reg(unsigned pin)
-@@ -47,28 +50,14 @@ static int axp_gpio_direction_input(stru
+@@ -46,28 +49,14 @@ static int axp_gpio_direction_input(stru
  static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
  				     int val)
  {
@@ -63,7 +94,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  }
  
  static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
-@@ -76,25 +65,16 @@ static int axp_gpio_get_value(struct ude
+@@ -75,25 +64,16 @@ static int axp_gpio_get_value(struct ude
  	u8 reg, val, mask;
  	int ret;
  
@@ -95,7 +126,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  	return (val & mask) ? 1 : 0;
  }
  
-@@ -102,25 +82,12 @@ static int axp_gpio_set_value(struct ude
+@@ -101,25 +81,12 @@ static int axp_gpio_set_value(struct ude
  {
  	u8 reg;
  
@@ -126,7 +157,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  }
  
  static const struct dm_gpio_ops gpio_axp_ops = {
-@@ -135,8 +102,8 @@ static int gpio_axp_probe(struct udevice
+@@ -134,8 +101,8 @@ static int gpio_axp_probe(struct udevice
  	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  
  	/* Tell the uclass how many GPIOs we have */
@@ -139,7 +170,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  }
 --- a/drivers/gpio/sunxi_gpio.c
 +++ b/drivers/gpio/sunxi_gpio.c
-@@ -247,15 +247,7 @@ int sunxi_name_to_gpio(const char *name)
+@@ -114,15 +114,7 @@ int sunxi_name_to_gpio(const char *name)
  {
  	unsigned int gpio;
  	int ret;
@@ -194,34 +225,3 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
  #define AXP_GPIO0_CTRL			0x90
  #define AXP_GPIO1_CTRL			0x92
  #define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
---- a/include/sunxi_gpio.h
-+++ b/include/sunxi_gpio.h
-@@ -82,7 +82,6 @@ enum sunxi_gpio_number {
- 	SUNXI_GPIO_L_START = 352,
- 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
- 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
--	SUNXI_GPIO_AXP0_START = 1024,
- };
- 
- /* SUNXI GPIO number definitions */
-@@ -99,8 +98,6 @@ enum sunxi_gpio_number {
- #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
- #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
- 
--#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
--
- /* GPIO pin function config */
- #define SUNXI_GPIO_INPUT	0
- #define SUNXI_GPIO_OUTPUT	1
-@@ -185,11 +182,6 @@ enum sunxi_gpio_number {
- #define SUNXI_GPIO_PULL_UP	1
- #define SUNXI_GPIO_PULL_DOWN	2
- 
--/* Virtual AXP0 GPIOs */
--#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
--#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
--#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
--
- struct sunxi_gpio_plat {
- 	void			*regs;
- 	char			bank_name[3];

package/boot/uboot-d1/patches/0013-clk-sunxi-Add-a-driver-for-the-legacy-A31-A23-A33-PR.patch

@@ -0,0 +1,160 @@
+From 5a909f4d4d10f3a7a59b3b75eee502937e166891 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Mon, 2 May 2022 22:00:05 -0500
+Subject: [PATCH 13/90] clk: sunxi: Add a driver for the legacy A31/A23/A33
+ PRCM
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/Kconfig        | 13 ++++-
+ drivers/clk/sunxi/Makefile       |  1 +
+ drivers/clk/sunxi/clk_a31_apb0.c | 97 ++++++++++++++++++++++++++++++++
+ include/clk/sunxi.h              |  1 +
+ 4 files changed, 110 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/clk/sunxi/clk_a31_apb0.c
+
+--- a/drivers/clk/sunxi/Kconfig
++++ b/drivers/clk/sunxi/Kconfig
+@@ -38,12 +38,21 @@ config CLK_SUN6I_A31
+ 	  This enables common clock driver support for platforms based
+ 	  on Allwinner A31/A31s SoC.
+ 
++config CLK_SUN6I_A31_APB0
++	bool "Clock driver for Allwinner A31 generation PRCM (legacy)"
++	default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
++	help
++	  This enables common clock driver support for the PRCM
++	  in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM
++	  MFD binding.
++
+ config CLK_SUN6I_A31_R
+-	bool "Clock driver for Allwinner A31 generation PRCM"
++	bool "Clock driver for Allwinner A31 generation PRCM (CCU)"
+ 	default SUNXI_GEN_SUN6I
+ 	help
+ 	  This enables common clock driver support for the PRCM
+-	  in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
++	  in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using
++	  the new CCU binding.
+ 
+ config CLK_SUN8I_A23
+ 	bool "Clock driver for Allwinner A23/A33"
+--- a/drivers/clk/sunxi/Makefile
++++ b/drivers/clk/sunxi/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f
+ obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
+ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
+ obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
++obj-$(CONFIG_CLK_SUN6I_A31_APB0) += clk_a31_apb0.o
+ obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
+ obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
+ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
+--- /dev/null
++++ b/drivers/clk/sunxi/clk_a31_apb0.c
+@@ -0,0 +1,97 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) Samuel Holland <samuel@sholland.org>
++ */
++
++#include <clk-uclass.h>
++#include <dm.h>
++#include <clk/sunxi.h>
++#include <linux/bitops.h>
++
++static struct ccu_clk_gate sun6i_apb0_gates[] = {
++	[0]	= GATE(0x028, BIT(0)),
++	[1]	= GATE(0x028, BIT(1)),
++	[2]	= GATE(0x028, BIT(2)),
++	[3]	= GATE(0x028, BIT(3)),
++	[4]	= GATE(0x028, BIT(4)),
++	[5]	= GATE(0x028, BIT(5)),
++	[6]	= GATE(0x028, BIT(6)),
++	[7]	= GATE(0x028, BIT(7)),
++};
++
++static struct ccu_reset sun6i_apb0_resets[] = {
++	[0]	= RESET(0x0b0, BIT(0)),
++	[1]	= RESET(0x0b0, BIT(1)),
++	[2]	= RESET(0x0b0, BIT(2)),
++	[3]	= RESET(0x0b0, BIT(3)),
++	[4]	= RESET(0x0b0, BIT(4)),
++	[5]	= RESET(0x0b0, BIT(5)),
++	[6]	= RESET(0x0b0, BIT(6)),
++	[7]	= RESET(0x0b0, BIT(7)),
++};
++
++const struct ccu_desc sun6i_apb0_clk_desc = {
++	.gates = sun6i_apb0_gates,
++	.resets = sun6i_apb0_resets,
++	.num_gates = ARRAY_SIZE(sun6i_apb0_gates),
++	.num_resets = ARRAY_SIZE(sun6i_apb0_resets),
++};
++
++static int sun6i_apb0_of_to_plat(struct udevice *dev)
++{
++	struct ccu_plat *plat = dev_get_plat(dev);
++
++	plat->base = dev_read_addr_ptr(dev->parent);
++	if (!plat->base)
++		return -ENOMEM;
++
++	plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
++	if (!plat->desc)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct udevice_id sun6i_apb0_clk_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_apb0_clk) = {
++	.name		= "sun6i_apb0_clk",
++	.id		= UCLASS_CLK,
++	.of_match	= sun6i_apb0_clk_ids,
++	.of_to_plat	= sun6i_apb0_of_to_plat,
++	.plat_auto	= sizeof(struct ccu_plat),
++	.ops		= &sunxi_clk_ops,
++};
++
++static const struct udevice_id sun6i_apb0_reset_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-clock-reset",
++	  .data = (ulong)&sun6i_apb0_clk_desc },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_apb0_reset) = {
++	.name		= "sun6i_apb0_reset",
++	.id		= UCLASS_RESET,
++	.of_match	= sun6i_apb0_reset_ids,
++	.of_to_plat	= sun6i_apb0_of_to_plat,
++	.plat_auto	= sizeof(struct ccu_plat),
++	.ops		= &sunxi_reset_ops,
++};
++
++static const struct udevice_id sun6i_prcm_mfd_ids[] = {
++	{ .compatible = "allwinner,sun6i-a31-prcm" },
++	{ .compatible = "allwinner,sun8i-a23-prcm" },
++	{ }
++};
++
++U_BOOT_DRIVER(sun6i_prcm_mfd) = {
++	.name		= "sun6i_prcm_mfd",
++	.id		= UCLASS_SIMPLE_BUS,
++	.of_match	= sun6i_prcm_mfd_ids,
++};
+--- a/include/clk/sunxi.h
++++ b/include/clk/sunxi.h
+@@ -86,5 +86,6 @@ struct ccu_plat {
+ };
+ 
+ extern struct clk_ops sunxi_clk_ops;
++extern struct reset_ops sunxi_reset_ops;
+ 
+ #endif /* _CLK_SUNXI_H */

package/boot/uboot-d1/patches/0014-clk-sunxi-Use-the-right-symbol-in-the-Makefile.patch

@@ -0,0 +1,21 @@
+From 3d97f99cb173422ee8a15b7ec1df83ff61e68204 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 14:28:23 -0500
+Subject: [PATCH 14/90] clk: sunxi: Use the right symbol in the Makefile
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/Makefile
++++ b/drivers/clk/Makefile
+@@ -25,7 +25,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+ obj-$(CONFIG_ARCH_SOCFPGA) += altera/
+ obj-$(CONFIG_ARCH_STM32) += stm32/
+ obj-$(CONFIG_ARCH_STM32MP) += stm32/
+-obj-$(CONFIG_ARCH_SUNXI) += sunxi/
++obj-$(CONFIG_CLK_SUNXI) += sunxi/
+ obj-$(CONFIG_CLK_AT91) += at91/
+ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
+ obj-$(CONFIG_CLK_BOSTON) += clk_boston.o

package/boot/uboot-d1/patches/0015-net-sun8i-emac-Use-common-syscon-setup-for-R40.patch

@@ -0,0 +1,100 @@
+From 9766169812418aee10dbc8d40aca27c1c576f521 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 14 Jul 2022 23:39:46 -0500
+Subject: [PATCH 15/90] net: sun8i-emac: Use common syscon setup for R40
+
+While R40 puts the EMAC syscon register at a different address from
+other variants, the relevant portion of the register's layout is the
+same. Factor out the register offset so the same code can be shared
+by all variants. This matches what the Linux driver does.
+
+This change provides two benefits beyond the simplification:
+ - R40 boards now respect the RX delays from the devicetree
+ - This resolves a warning on architectures where readl/writel
+   expect the address to have a pointer type, not phys_addr_t.
+
+Series-to: sunxi
+
+Cover-letter:
+net: sun8i-emac: Allwinner D1 Support
+D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
+However, there are a couple of issues with the driver preventing it
+being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
+a general cleanup.
+END
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/net/sun8i_emac.c | 29 ++++++++++++-----------------
+ 1 file changed, 12 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/sun8i_emac.c
++++ b/drivers/net/sun8i_emac.c
+@@ -162,7 +162,7 @@ struct emac_eth_dev {
+ 
+ 	enum emac_variant variant;
+ 	void *mac_reg;
+-	phys_addr_t sysctl_reg;
++	void *sysctl_reg;
+ 	struct phy_device *phydev;
+ 	struct mii_dev *bus;
+ 	struct clk tx_clk;
+@@ -317,18 +317,7 @@ static int sun8i_emac_set_syscon(struct
+ {
+ 	u32 reg;
+ 
+-	if (priv->variant == R40_GMAC) {
+-		/* Select RGMII for R40 */
+-		reg = readl(priv->sysctl_reg + 0x164);
+-		reg |= SC_ETCS_INT_GMII |
+-		       SC_EPIT |
+-		       (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
+-
+-		writel(reg, priv->sysctl_reg + 0x164);
+-		return 0;
+-	}
+-
+-	reg = readl(priv->sysctl_reg + 0x30);
++	reg = readl(priv->sysctl_reg);
+ 
+ 	reg = sun8i_emac_set_syscon_ephy(priv, reg);
+ 
+@@ -369,7 +358,7 @@ static int sun8i_emac_set_syscon(struct
+ 		reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
+ 			 & SC_ERXDC_MASK;
+ 
+-	writel(reg, priv->sysctl_reg + 0x30);
++	writel(reg, priv->sysctl_reg);
+ 
+ 	return 0;
+ }
+@@ -792,6 +781,7 @@ static int sun8i_emac_eth_of_to_plat(str
+ 	struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
+ 	struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
+ 	struct emac_eth_dev *priv = dev_get_priv(dev);
++	phys_addr_t syscon_base;
+ 	const fdt32_t *reg;
+ 	int node = dev_of_offset(dev);
+ 	int offset = 0;
+@@ -837,13 +827,18 @@ static int sun8i_emac_eth_of_to_plat(str
+ 		      __func__);
+ 		return -EINVAL;
+ 	}
+-	priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+-						 offset, reg);
+-	if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
++
++	syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
++	if (syscon_base == FDT_ADDR_T_NONE) {
+ 		debug("%s: Cannot find syscon base address\n", __func__);
+ 		return -EINVAL;
+ 	}
+ 
++	if (priv->variant == R40_GMAC)
++		priv->sysctl_reg = (void *)syscon_base + 0x164;
++	else
++		priv->sysctl_reg = (void *)syscon_base + 0x30;
++
+ 	pdata->phy_interface = -1;
+ 	priv->phyaddr = -1;
+ 	priv->use_internal_phy = false;

package/boot/uboot-d1/patches/0016-sunxi-mmc-ignore-card-detect-in-SPL.patch

@@ -0,0 +1,92 @@
+From 2cde6c8a7c41c13137298c19b4e104e4f5d6851c Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 13 Jul 2022 17:21:43 +0100
+Subject: [PATCH 16/90] sunxi: mmc: ignore card detect in SPL
+
+The sunxi MMC code does not use the DM in the SPL, as we don't have a
+device tree available that early, also no space for it.
+This also means we cannot access the card-detect GPIO information from
+there, so we have Kconfig symbols called CONFIG_MMCx_CD_PIN, which each
+board has to define. This is a burden, also requires extra GPIO code in
+the SPL.
+As the SPL is the natural successor of the BootROM (from which we are
+loaded), we can actually ignore the CD pin completely, as this is what
+the BootROM does as well: CD GPIOs are board specific, but the BootROM
+is not, so accesses the MMC devices anyway.
+
+Remove the card detect code from the non-DM implementation of the sunxi
+MMC driver, to get rid of this unneeded code.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 37 ++-----------------------------------
+ 1 file changed, 2 insertions(+), 35 deletions(-)
+
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -44,22 +44,10 @@ struct sunxi_mmc_priv {
+ /* support 4 mmc hosts */
+ struct sunxi_mmc_priv mmc_host[4];
+ 
+-static int sunxi_mmc_getcd_gpio(int sdc_no)
+-{
+-	switch (sdc_no) {
+-	case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
+-	case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
+-	case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
+-	case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
+-	}
+-	return -EINVAL;
+-}
+-
+ static int mmc_resource_init(int sdc_no)
+ {
+ 	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+ 	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+-	int cd_pin, ret = 0;
+ 
+ 	debug("init mmc %d resource\n", sdc_no);
+ 
+@@ -90,16 +78,7 @@ static int mmc_resource_init(int sdc_no)
+ 	}
+ 	priv->mmc_no = sdc_no;
+ 
+-	cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
+-	if (cd_pin >= 0) {
+-		ret = gpio_request(cd_pin, "mmc_cd");
+-		if (!ret) {
+-			sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
+-			ret = gpio_direction_input(cd_pin);
+-		}
+-	}
+-
+-	return ret;
++	return 0;
+ }
+ #endif
+ 
+@@ -523,23 +502,11 @@ static int sunxi_mmc_send_cmd_legacy(str
+ 	return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
+ }
+ 
+-static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
+-{
+-	struct sunxi_mmc_priv *priv = mmc->priv;
+-	int cd_pin;
+-
+-	cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
+-	if (cd_pin < 0)
+-		return 1;
+-
+-	return !gpio_get_value(cd_pin);
+-}
+-
++/* .get_cd is not needed by the SPL */
+ static const struct mmc_ops sunxi_mmc_ops = {
+ 	.send_cmd	= sunxi_mmc_send_cmd_legacy,
+ 	.set_ios	= sunxi_mmc_set_ios_legacy,
+ 	.init		= sunxi_mmc_core_init,
+-	.getcd		= sunxi_mmc_getcd_legacy,
+ };
+ 
+ struct mmc *sunxi_mmc_init(int sdc_no)

package/boot/uboot-d1/patches/0017-sunxi-mmc-group-non-DM-specific-functions.patch

@@ -0,0 +1,177 @@
+From 74afc3a4e0ff780eddd859a25de7142e4baeeed5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 13 Jul 2022 17:21:44 +0100
+Subject: [PATCH 17/90] sunxi: mmc: group non-DM specific functions
+
+As the SPL code for sunxi boards does not use the driver model, we have
+two mmc_ops structures, one for DM, one for non-DM. The actual hardware
+access code is shared, with the respective callback functions using that
+common code.
+
+To make this more obvious and easier to read, reorder the functions to
+group them: we first have the common code, then the non-DM bits, and
+the proper DM implementation at the end.
+Also document this structure in the comment at the beginning of the file.
+
+No functional change intended.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mmc/sunxi_mmc.c | 117 +++++++++++++++++++++-------------------
+ 1 file changed, 61 insertions(+), 56 deletions(-)
+
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -5,6 +5,12 @@
+  * Aaron <leafy.myeh@allwinnertech.com>
+  *
+  * MMC driver for allwinner sunxi platform.
++ *
++ * This driver is used by the (ARM) SPL with the legacy MMC interface, and
++ * by U-Boot proper using the full DM interface. The actual hardware access
++ * code is common, and comes first in this file.
++ * The legacy MMC interface implementation comes next, followed by the
++ * proper DM_MMC implementation at the end.
+  */
+ 
+ #include <common.h>
+@@ -40,48 +46,6 @@ struct sunxi_mmc_priv {
+ 	struct mmc_config cfg;
+ };
+ 
+-#if !CONFIG_IS_ENABLED(DM_MMC)
+-/* support 4 mmc hosts */
+-struct sunxi_mmc_priv mmc_host[4];
+-
+-static int mmc_resource_init(int sdc_no)
+-{
+-	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
+-	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+-
+-	debug("init mmc %d resource\n", sdc_no);
+-
+-	switch (sdc_no) {
+-	case 0:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
+-		priv->mclkreg = &ccm->sd0_clk_cfg;
+-		break;
+-	case 1:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
+-		priv->mclkreg = &ccm->sd1_clk_cfg;
+-		break;
+-#ifdef SUNXI_MMC2_BASE
+-	case 2:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
+-		priv->mclkreg = &ccm->sd2_clk_cfg;
+-		break;
+-#endif
+-#ifdef SUNXI_MMC3_BASE
+-	case 3:
+-		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
+-		priv->mclkreg = &ccm->sd3_clk_cfg;
+-		break;
+-#endif
+-	default:
+-		printf("Wrong mmc number %d\n", sdc_no);
+-		return -1;
+-	}
+-	priv->mmc_no = sdc_no;
+-
+-	return 0;
+-}
+-#endif
+-
+ /*
+  * All A64 and later MMC controllers feature auto-calibration. This would
+  * normally be detected via the compatible string, but we need something
+@@ -269,19 +233,6 @@ static int sunxi_mmc_set_ios_common(stru
+ 	return 0;
+ }
+ 
+-#if !CONFIG_IS_ENABLED(DM_MMC)
+-static int sunxi_mmc_core_init(struct mmc *mmc)
+-{
+-	struct sunxi_mmc_priv *priv = mmc->priv;
+-
+-	/* Reset controller */
+-	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
+-	udelay(1000);
+-
+-	return 0;
+-}
+-#endif
+-
+ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
+ 				 struct mmc_data *data)
+ {
+@@ -486,7 +437,60 @@ out:
+ 	return error;
+ }
+ 
++/* non-DM code here is used by the (ARM) SPL only */
++
+ #if !CONFIG_IS_ENABLED(DM_MMC)
++/* support 4 mmc hosts */
++struct sunxi_mmc_priv mmc_host[4];
++
++static int mmc_resource_init(int sdc_no)
++{
++	struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
++	struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++	debug("init mmc %d resource\n", sdc_no);
++
++	switch (sdc_no) {
++	case 0:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
++		priv->mclkreg = &ccm->sd0_clk_cfg;
++		break;
++	case 1:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
++		priv->mclkreg = &ccm->sd1_clk_cfg;
++		break;
++#ifdef SUNXI_MMC2_BASE
++	case 2:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
++		priv->mclkreg = &ccm->sd2_clk_cfg;
++		break;
++#endif
++#ifdef SUNXI_MMC3_BASE
++	case 3:
++		priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
++		priv->mclkreg = &ccm->sd3_clk_cfg;
++		break;
++#endif
++	default:
++		printf("Wrong mmc number %d\n", sdc_no);
++		return -1;
++	}
++	priv->mmc_no = sdc_no;
++
++	return 0;
++}
++
++static int sunxi_mmc_core_init(struct mmc *mmc)
++{
++	struct sunxi_mmc_priv *priv = mmc->priv;
++
++	/* Reset controller */
++	writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
++	udelay(1000);
++
++	return 0;
++}
++
+ static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
+ {
+ 	struct sunxi_mmc_priv *priv = mmc->priv;
+@@ -562,7 +566,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
+ 
+ 	return mmc_create(cfg, priv);
+ }
+-#else
++
++#else /* CONFIG_DM_MMC code below, as used by U-Boot proper */
+ 
+ static int sunxi_mmc_set_ios(struct udevice *dev)
+ {

package/boot/uboot-d1/patches/0018-sunxi-remove-CONFIG_MMC-_CD_PIN.patch

@@ -0,0 +1,509 @@
+From bcc2e01668041c146d964ed5f77b819dcc35b3e2 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 15:07:47 +0000
+Subject: [PATCH 18/90] sunxi: remove CONFIG_MMC?_CD_PIN
+
+For legacy reasons we were defining the card detect GPIO for all sunxi
+boards in each board's defconfig.
+There is actually no need for a card-detect check in the SPL code (which
+consequently has been removed already), and also in U-Boot proper we
+have DM code to query the CD GPIO name from the device tree.
+
+That means we don't have any user of that information left, so can
+remove the definitions from the defconfigs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/mach-sunxi/Kconfig                  | 27 --------------------
+ configs/A10-OLinuXino-Lime_defconfig         |  1 -
+ configs/A10s-OLinuXino-M_defconfig           |  2 --
+ configs/A13-OLinuXino_defconfig              |  1 -
+ configs/A20-OLinuXino-Lime2-eMMC_defconfig   |  1 -
+ configs/A20-OLinuXino-Lime_defconfig         |  1 -
+ configs/A20-OLinuXino_MICRO-eMMC_defconfig   |  1 -
+ configs/A20-OLinuXino_MICRO_defconfig        |  2 --
+ configs/A20-Olimex-SOM-EVB_defconfig         |  2 --
+ configs/A20-Olimex-SOM204-EVB-eMMC_defconfig |  1 -
+ configs/Bananapi_M2_Ultra_defconfig          |  1 -
+ configs/Bananapi_m2m_defconfig               |  1 -
+ configs/Cubieboard2_defconfig                |  1 -
+ configs/Cubieboard4_defconfig                |  1 -
+ configs/Cubieboard_defconfig                 |  1 -
+ configs/Itead_Ibox_A20_defconfig             |  1 -
+ configs/Lamobo_R1_defconfig                  |  1 -
+ configs/Mele_M3_defconfig                    |  1 -
+ configs/Mele_M5_defconfig                    |  1 -
+ configs/Merrii_A80_Optimus_defconfig         |  1 -
+ configs/Orangepi_mini_defconfig              |  2 --
+ configs/Sinlinx_SinA31s_defconfig            |  1 -
+ configs/Sinlinx_SinA33_defconfig             |  1 -
+ configs/Sunchip_CX-A99_defconfig             |  1 -
+ configs/UTOO_P66_defconfig                   |  1 -
+ configs/Yones_Toptech_BD1078_defconfig       |  2 --
+ configs/bananapi_m2_zero_defconfig           |  1 -
+ configs/bananapi_m64_defconfig               |  1 -
+ configs/beelink_gs1_defconfig                |  1 -
+ configs/nanopi_m1_plus_defconfig             |  1 -
+ configs/oceanic_5205_5inmfd_defconfig        |  1 -
+ configs/orangepi_3_defconfig                 |  1 -
+ configs/orangepi_lite2_defconfig             |  1 -
+ configs/orangepi_one_plus_defconfig          |  1 -
+ configs/orangepi_zero2_defconfig             |  1 -
+ configs/orangepi_zero_plus2_defconfig        |  1 -
+ configs/orangepi_zero_plus2_h3_defconfig     |  1 -
+ configs/parrot_r16_defconfig                 |  1 -
+ configs/pine64-lts_defconfig                 |  1 -
+ configs/pine_h64_defconfig                   |  1 -
+ configs/sopine_baseboard_defconfig           |  1 -
+ configs/tanix_tx6_defconfig                  |  1 -
+ 42 files changed, 73 deletions(-)
+
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -652,33 +652,6 @@ config MACPWR
+ 	  Set the pin used to power the MAC. This takes a string in the format
+ 	  understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+ 
+-config MMC0_CD_PIN
+-	string "Card detect pin for mmc0"
+-	default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
+-	default ""
+-	---help---
+-	Set the card detect pin for mmc0, leave empty to not use cd. This
+-	takes a string in the format understood by sunxi_name_to_gpio, e.g.
+-	PH1 for pin 1 of port H.
+-
+-config MMC1_CD_PIN
+-	string "Card detect pin for mmc1"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+-config MMC2_CD_PIN
+-	string "Card detect pin for mmc2"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+-config MMC3_CD_PIN
+-	string "Card detect pin for mmc3"
+-	default ""
+-	---help---
+-	See MMC0_CD_PIN help text.
+-
+ config MMC1_PINS_PH
+ 	bool "Pins for mmc1 are on Port H"
+ 	depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
+--- a/configs/A10-OLinuXino-Lime_defconfig
++++ b/configs/A10-OLinuXino-Lime_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN4I=y
+ CONFIG_DRAM_CLK=480
+ CONFIG_DRAM_EMR1=4
+ CONFIG_SYS_CLK_FREQ=912000000
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+--- a/configs/A10s-OLinuXino-M_defconfig
++++ b/configs/A10s-OLinuXino-M_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-o
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=432
+-CONFIG_MMC0_CD_PIN="PG1"
+-CONFIG_MMC1_CD_PIN="PG13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+ CONFIG_USB1_VBUS_PIN="PB10"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/A13-OLinuXino_defconfig
++++ b/configs/A13-OLinuXino_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=408
+ CONFIG_DRAM_EMR1=0
+-CONFIG_MMC0_CD_PIN="PG0"
+ CONFIG_USB0_VBUS_DET="PG1"
+ CONFIG_USB1_VBUS_PIN="PG11"
+ CONFIG_AXP_GPIO=y
+--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
++++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/A20-OLinuXino-Lime_defconfig
++++ b/configs/A20-OLinuXino-Lime_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_SATAPWR="PC3"
+ CONFIG_AHCI=y
+--- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig
++++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_VIDEO_VGA=y
+--- a/configs/A20-OLinuXino_MICRO_defconfig
++++ b/configs/A20-OLinuXino_MICRO_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC3_CD_PIN="PH11"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_I2C1_ENABLE=y
+ CONFIG_VIDEO_VGA=y
+--- a/configs/A20-Olimex-SOM-EVB_defconfig
++++ b/configs/A20-Olimex-SOM-EVB_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC3_CD_PIN="PH0"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB0_VBUS_PIN="PB9"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
++++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ol
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PC17"
+ CONFIG_USB0_VBUS_DET="PH5"
+--- a/configs/Bananapi_M2_Ultra_defconfig
++++ b/configs/Bananapi_M2_Ultra_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_R40=y
+ CONFIG_DRAM_CLK=576
+ CONFIG_MACPWR="PA17"
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB1_VBUS_PIN="PH23"
+ CONFIG_USB2_VBUS_PIN="PH23"
+--- a/configs/Bananapi_m2m_defconfig
++++ b/configs/Bananapi_m2m_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=15291
+ CONFIG_DRAM_ODT_EN=y
+-CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PH8"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Cubieboard2_defconfig
++++ b/configs/Cubieboard2_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Cubieboard4_defconfig
++++ b/configs/Cubieboard4_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=672
+-CONFIG_MMC0_CD_PIN="PH18"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+--- a/configs/Cubieboard_defconfig
++++ b/configs/Cubieboard_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN4I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Itead_Ibox_A20_defconfig
++++ b/configs/Itead_Ibox_A20_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-it
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=480
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_SATAPWR="PB8"
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Lamobo_R1_defconfig
++++ b/configs/Lamobo_R1_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_MACPWR="PH23"
+-CONFIG_MMC0_CD_PIN="PH10"
+ CONFIG_SATAPWR="PB3"
+ CONFIG_GMAC_TX_DELAY=4
+ CONFIG_AHCI=y
+--- a/configs/Mele_M3_defconfig
++++ b/configs/Mele_M3_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=384
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_VIDEO_VGA=y
+ CONFIG_VIDEO_COMPOSITE=y
+--- a/configs/Mele_M5_defconfig
++++ b/configs/Mele_M5_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_ZQ=122
+-CONFIG_MMC0_CD_PIN="PH1"
+ CONFIG_VIDEO_COMPOSITE=y
+ CONFIG_AHCI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/Merrii_A80_Optimus_defconfig
++++ b/configs/Merrii_A80_Optimus_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-op
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=672
+-CONFIG_MMC0_CD_PIN="PH18"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+--- a/configs/Orangepi_mini_defconfig
++++ b/configs/Orangepi_mini_defconfig
+@@ -5,8 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_MACPWR="PH23"
+-CONFIG_MMC0_CD_PIN="PH10"
+-CONFIG_MMC3_CD_PIN="PH11"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB1_VBUS_PIN="PH26"
+ CONFIG_USB2_VBUS_PIN="PH22"
+--- a/configs/Sinlinx_SinA31s_defconfig
++++ b/configs/Sinlinx_SinA31s_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN6I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_ZQ=251
+-CONFIG_MMC0_CD_PIN="PA4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+ CONFIG_USB1_VBUS_PIN=""
+ CONFIG_USB2_VBUS_PIN=""
+--- a/configs/Sinlinx_SinA33_defconfig
++++ b/configs/Sinlinx_SinA33_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=15291
+-CONFIG_MMC0_CD_PIN="PB4"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PH8"
+ CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0"
+--- a/configs/Sunchip_CX-A99_defconfig
++++ b/configs/Sunchip_CX-A99_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN9I=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=3881915
+ CONFIG_DRAM_ODT_EN=y
+-CONFIG_MMC0_CD_PIN="PH17"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PH15"
+ CONFIG_USB1_VBUS_PIN="PL7"
+--- a/configs/UTOO_P66_defconfig
++++ b/configs/UTOO_P66_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN5I=y
+ CONFIG_DRAM_CLK=432
+ CONFIG_DRAM_EMR1=0
+-CONFIG_MMC0_CD_PIN="PG0"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_VBUS_PIN="PB04"
+ CONFIG_USB0_VBUS_DET="PG01"
+--- a/configs/Yones_Toptech_BD1078_defconfig
++++ b/configs/Yones_Toptech_BD1078_defconfig
+@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yo
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN7I=y
+ CONFIG_DRAM_CLK=408
+-CONFIG_MMC0_CD_PIN="PH1"
+-CONFIG_MMC1_CD_PIN="PH2"
+ CONFIG_MMC1_PINS_PH=y
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+ CONFIG_USB0_VBUS_PIN="PB9"
+--- a/configs/bananapi_m2_zero_defconfig
++++ b/configs/bananapi_m2_zero_defconfig
+@@ -4,5 +4,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plu
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=408
+-CONFIG_MMC0_CD_PIN=""
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/bananapi_m64_defconfig
++++ b/configs/bananapi_m64_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-b
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I=y
+ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUPPORT_EMMC_BOOT=y
+--- a/configs/beelink_gs1_defconfig
++++ b/configs/beelink_gs1_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-be
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/nanopi_m1_plus_defconfig
++++ b/configs/nanopi_m1_plus_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=408
+ CONFIG_MACPWR="PD6"
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/oceanic_5205_5inmfd_defconfig
++++ b/configs/oceanic_5205_5inmfd_defconfig
+@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/orangepi_3_defconfig
++++ b/configs/orangepi_3_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5"
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/orangepi_lite2_defconfig
++++ b/configs/orangepi_lite2_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_USB_EHCI_HCD=y
+--- a/configs/orangepi_one_plus_defconfig
++++ b/configs/orangepi_one_plus_defconfig
+@@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-or
+ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ # CONFIG_PSCI_RESET is not set
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_USB_EHCI_HCD=y
+--- a/configs/orangepi_zero2_defconfig
++++ b/configs/orangepi_zero2_defconfig
+@@ -7,7 +7,6 @@ CONFIG_DRAM_SUN50I_H616_READ_CALIBRATION
+ CONFIG_DRAM_SUN50I_H616_READ_TRAINING=y
+ CONFIG_DRAM_SUN50I_H616_WRITE_TRAINING=y
+ CONFIG_MACH_SUN50I_H616=y
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_R_I2C_ENABLE=y
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/orangepi_zero_plus2_defconfig
++++ b/configs/orangepi_zero_plus2_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
+ CONFIG_DRAM_CLK=672
+ CONFIG_DRAM_ZQ=3881977
+ # CONFIG_DRAM_ODT_EN is not set
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/orangepi_zero_plus2_h3_defconfig
++++ b/configs/orangepi_zero_plus2_h3_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_H3=y
+ CONFIG_DRAM_CLK=672
+ # CONFIG_DRAM_ODT_EN is not set
+-CONFIG_MMC0_CD_PIN="PH13"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+ CONFIG_SUN8I_EMAC=y
+--- a/configs/parrot_r16_defconfig
++++ b/configs/parrot_r16_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN8I_A33=y
+ CONFIG_DRAM_CLK=600
+ CONFIG_DRAM_ZQ=15291
+-CONFIG_MMC0_CD_PIN="PD14"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB0_ID_DET="PD10"
+ CONFIG_USB1_VBUS_PIN="PD12"
+--- a/configs/pine64-lts_defconfig
++++ b/configs/pine64-lts_defconfig
+@@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/pine_h64_defconfig
++++ b/configs/pine_h64_defconfig
+@@ -5,7 +5,6 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+ CONFIG_MACPWR="PC16"
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_USB3_VBUS_PIN="PL5"
+ CONFIG_SPL_SPI_SUNXI=y
+--- a/configs/sopine_baseboard_defconfig
++++ b/configs/sopine_baseboard_defconfig
+@@ -7,7 +7,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+ CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
+ CONFIG_DRAM_CLK=552
+ CONFIG_DRAM_ZQ=3881949
+-CONFIG_MMC0_CD_PIN=""
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ CONFIG_SPL_SPI_SUNXI=y
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+--- a/configs/tanix_tx6_defconfig
++++ b/configs/tanix_tx6_defconfig
+@@ -5,6 +5,5 @@ CONFIG_SPL=y
+ CONFIG_MACH_SUN50I_H6=y
+ CONFIG_SUNXI_DRAM_H6_DDR3_1333=y
+ CONFIG_DRAM_CLK=648
+-CONFIG_MMC0_CD_PIN="PF6"
+ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+ # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

package/boot/uboot-d1/patches/0019-sunxi-mmc-Move-header-to-the-driver-directory.patch

@@ -0,0 +1,323 @@
+From 4c0c00e7131baf410702555342337c178dd0de98 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 30 Oct 2022 16:04:47 -0500
+Subject: [PATCH 19/90] sunxi: mmc: Move header to the driver directory
+
+The MMC controller driver is (and ought to be) the only user of these
+register definitions. Put them in a header next to the driver to remove
+the dependency on a specific ARM platform's headers.
+
+Due to the sunxi_mmc_init() prototype, the file was not renamed. None of
+the register definitions were changed.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/include/asm/arch-sunxi/mmc.h | 139 +-------------------------
+ drivers/mmc/sunxi_mmc.c               |   4 +
+ drivers/mmc/sunxi_mmc.h               | 138 +++++++++++++++++++++++++
+ 3 files changed, 146 insertions(+), 135 deletions(-)
+ create mode 100644 drivers/mmc/sunxi_mmc.h
+
+--- a/arch/arm/include/asm/arch-sunxi/mmc.h
++++ b/arch/arm/include/asm/arch-sunxi/mmc.h
+@@ -1,139 +1,8 @@
+ /* SPDX-License-Identifier: GPL-2.0+ */
+-/*
+- * (C) Copyright 2007-2011
+- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+- * Aaron <leafy.myeh@allwinnertech.com>
+- *
+- * MMC register definition for allwinner sunxi platform.
+- */
+ 
+-#ifndef _SUNXI_MMC_H
+-#define _SUNXI_MMC_H
+-
+-#include <linux/types.h>
+-
+-struct sunxi_mmc {
+-	u32 gctrl;		/* 0x00 global control */
+-	u32 clkcr;		/* 0x04 clock control */
+-	u32 timeout;		/* 0x08 time out */
+-	u32 width;		/* 0x0c bus width */
+-	u32 blksz;		/* 0x10 block size */
+-	u32 bytecnt;		/* 0x14 byte count */
+-	u32 cmd;		/* 0x18 command */
+-	u32 arg;		/* 0x1c argument */
+-	u32 resp0;		/* 0x20 response 0 */
+-	u32 resp1;		/* 0x24 response 1 */
+-	u32 resp2;		/* 0x28 response 2 */
+-	u32 resp3;		/* 0x2c response 3 */
+-	u32 imask;		/* 0x30 interrupt mask */
+-	u32 mint;		/* 0x34 masked interrupt status */
+-	u32 rint;		/* 0x38 raw interrupt status */
+-	u32 status;		/* 0x3c status */
+-	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
+-	u32 funcsel;		/* 0x44 function select */
+-	u32 cbcr;		/* 0x48 CIU byte count */
+-	u32 bbcr;		/* 0x4c BIU byte count */
+-	u32 dbgc;		/* 0x50 debug enable */
+-	u32 res0;		/* 0x54 reserved */
+-	u32 a12a;		/* 0x58 Auto command 12 argument */
+-	u32 ntsr;		/* 0x5c	New timing set register */
+-	u32 res1[8];
+-	u32 dmac;		/* 0x80 internal DMA control */
+-	u32 dlba;		/* 0x84 internal DMA descr list base address */
+-	u32 idst;		/* 0x88 internal DMA status */
+-	u32 idie;		/* 0x8c internal DMA interrupt enable */
+-	u32 chda;		/* 0x90 */
+-	u32 cbda;		/* 0x94 */
+-	u32 res2[26];
+-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
+-	u32 res3[17];
+-	u32 samp_dl;
+-	u32 res4[46];
+-#endif
+-	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
+-};
+-
+-#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
+-#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
+-#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
+-
+-#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
+-#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
+-#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
+-#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
+-					 SUNXI_MMC_GCTRL_FIFO_RESET|\
+-					 SUNXI_MMC_GCTRL_DMA_RESET)
+-#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
+-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
+-
+-#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
+-#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
+-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
+-#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
+-#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
+-#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
+-#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
+-#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
+-#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
+-#define SUNXI_MMC_CMD_START		(0x1 << 31)
+-
+-#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
+-#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
+-#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
+-#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
+-#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
+-#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
+-#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
+-#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
+-#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
+-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
+-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
+-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
+-#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
+-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
+-#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
+-#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
+-#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
+-#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
+-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
+-	(SUNXI_MMC_RINT_RESP_ERROR |		\
+-	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
+-	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
+-	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
+-	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
+-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
+-	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
+-	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
+-	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
+-	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
+-	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
+-	 SUNXI_MMC_RINT_DATA_OVER |		\
+-	 SUNXI_MMC_RINT_COMMAND_DONE |		\
+-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+-
+-#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
+-#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
+-#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
+-#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
+-#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
+-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
+-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
+-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
+-
+-#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
+-
+-#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
+-#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
+-#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
+-
+-#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
+-#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
+-
+-#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
+-#define SUNXI_MMC_COMMON_RESET			(1 << 18)
+-
+-#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
++#ifndef _ASM_ARCH_MMC_H_
++#define _ASM_ARCH_MMC_H_
+ 
+ struct mmc *sunxi_mmc_init(int sdc_no);
+-#endif /* _SUNXI_MMC_H */
++
++#endif /* _ASM_ARCH_MMC_H_ */
+--- a/drivers/mmc/sunxi_mmc.c
++++ b/drivers/mmc/sunxi_mmc.c
+@@ -25,9 +25,13 @@
+ #include <asm/io.h>
+ #include <asm/arch/clock.h>
+ #include <asm/arch/cpu.h>
++#if !CONFIG_IS_ENABLED(DM_MMC)
+ #include <asm/arch/mmc.h>
++#endif
+ #include <linux/delay.h>
+ 
++#include "sunxi_mmc.h"
++
+ #ifndef CCM_MMC_CTRL_MODE_SEL_NEW
+ #define CCM_MMC_CTRL_MODE_SEL_NEW	0
+ #endif
+--- /dev/null
++++ b/drivers/mmc/sunxi_mmc.h
+@@ -0,0 +1,138 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * (C) Copyright 2007-2011
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Aaron <leafy.myeh@allwinnertech.com>
++ *
++ * MMC register definition for allwinner sunxi platform.
++ */
++
++#ifndef _SUNXI_MMC_H
++#define _SUNXI_MMC_H
++
++#include <linux/types.h>
++
++struct sunxi_mmc {
++	u32 gctrl;		/* 0x00 global control */
++	u32 clkcr;		/* 0x04 clock control */
++	u32 timeout;		/* 0x08 time out */
++	u32 width;		/* 0x0c bus width */
++	u32 blksz;		/* 0x10 block size */
++	u32 bytecnt;		/* 0x14 byte count */
++	u32 cmd;		/* 0x18 command */
++	u32 arg;		/* 0x1c argument */
++	u32 resp0;		/* 0x20 response 0 */
++	u32 resp1;		/* 0x24 response 1 */
++	u32 resp2;		/* 0x28 response 2 */
++	u32 resp3;		/* 0x2c response 3 */
++	u32 imask;		/* 0x30 interrupt mask */
++	u32 mint;		/* 0x34 masked interrupt status */
++	u32 rint;		/* 0x38 raw interrupt status */
++	u32 status;		/* 0x3c status */
++	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
++	u32 funcsel;		/* 0x44 function select */
++	u32 cbcr;		/* 0x48 CIU byte count */
++	u32 bbcr;		/* 0x4c BIU byte count */
++	u32 dbgc;		/* 0x50 debug enable */
++	u32 res0;		/* 0x54 reserved */
++	u32 a12a;		/* 0x58 Auto command 12 argument */
++	u32 ntsr;		/* 0x5c	New timing set register */
++	u32 res1[8];
++	u32 dmac;		/* 0x80 internal DMA control */
++	u32 dlba;		/* 0x84 internal DMA descr list base address */
++	u32 idst;		/* 0x88 internal DMA status */
++	u32 idie;		/* 0x8c internal DMA interrupt enable */
++	u32 chda;		/* 0x90 */
++	u32 cbda;		/* 0x94 */
++	u32 res2[26];
++#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
++	u32 res3[17];
++	u32 samp_dl;
++	u32 res4[46];
++#endif
++	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
++};
++
++#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
++#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
++#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
++
++#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
++#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
++#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
++#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
++					 SUNXI_MMC_GCTRL_FIFO_RESET|\
++					 SUNXI_MMC_GCTRL_DMA_RESET)
++#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
++#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
++
++#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
++#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
++#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
++#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
++#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
++#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
++#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
++#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
++#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
++#define SUNXI_MMC_CMD_START		(0x1 << 31)
++
++#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
++#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
++#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
++#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
++#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
++#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
++#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
++#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
++#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
++#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
++#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
++#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
++#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
++#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
++#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
++#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
++#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
++#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
++#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
++	(SUNXI_MMC_RINT_RESP_ERROR |		\
++	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
++	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
++	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
++	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
++	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
++	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
++	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
++#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
++	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
++	 SUNXI_MMC_RINT_DATA_OVER |		\
++	 SUNXI_MMC_RINT_COMMAND_DONE |		\
++	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
++
++#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
++#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
++#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
++#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
++#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
++#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
++#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
++#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
++
++#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
++
++#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
++#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
++#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
++
++#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
++#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
++
++#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
++#define SUNXI_MMC_COMMON_RESET			(1 << 18)
++
++#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
++
++#endif /* _SUNXI_MMC_H */

package/boot/uboot-d1/patches/0020-pinctrl-sunxi-Add-support-for-the-D1.patch

@@ -0,0 +1,72 @@
+From fdf871a6089ee2f56439880b69d33a7d0d707d15 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 Aug 2021 22:24:28 -0500
+Subject: [PATCH 20/90] pinctrl: sunxi: Add support for the D1
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/pinctrl/sunxi/Kconfig         |  5 +++++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 31 +++++++++++++++++++++++++++
+ 2 files changed, 36 insertions(+)
+
+--- a/drivers/pinctrl/sunxi/Kconfig
++++ b/drivers/pinctrl/sunxi/Kconfig
+@@ -89,6 +89,11 @@ config PINCTRL_SUN9I_A80_R
+ 	default MACH_SUN9I
+ 	select PINCTRL_SUNXI
+ 
++config PINCTRL_SUN20I_D1
++	bool "Support for the Allwinner D1 PIO"
++	default TARGET_SUN20I_D1
++	select PINCTRL_SUNXI
++
+ config PINCTRL_SUN50I_A64
+ 	bool "Support for the Allwinner A64 PIO"
+ 	default MACH_SUN50I
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -588,6 +588,31 @@ static const struct sunxi_pinctrl_desc _
+ 	.num_banks	= 3,
+ };
+ 
++static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
++	{ "emac",	8 },	/* PE0-PE15 */
++	{ "gpio_in",	0 },
++	{ "gpio_out",	1 },
++	{ "i2c0",	4 },	/* PB10-PB11 */
++	{ "mmc0",	2 },	/* PF0-PF5 */
++	{ "mmc1",	2 },	/* PG0-PG5 */
++	{ "mmc2",	3 },	/* PC2-PC7 */
++	{ "spi0",	2 },	/* PC2-PC7 */
++#if IS_ENABLED(CONFIG_UART0_PORT_F)
++	{ "uart0",	3 },	/* PF2-PF4 */
++#else
++	{ "uart0",	6 },	/* PB8-PB9 */
++#endif
++	{ "uart1",	2 },	/* PG6-PG7 */
++	{ "uart2",	7 },	/* PB0-PB1 */
++};
++
++static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
++	.functions	= sun20i_d1_pinctrl_functions,
++	.num_functions	= ARRAY_SIZE(sun20i_d1_pinctrl_functions),
++	.first_bank	= SUNXI_GPIO_A,
++	.num_banks	= 7,
++};
++
+ static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
+ 	{ "emac",	4 },	/* PD8-PD23 */
+ 	{ "gpio_in",	0 },
+@@ -849,6 +874,12 @@ static const struct udevice_id sunxi_pin
+ 		.data = (ulong)&sun9i_a80_r_pinctrl_desc,
+ 	},
+ #endif
++#ifdef CONFIG_PINCTRL_SUN20I_D1
++	{
++		.compatible = "allwinner,sun20i-d1-pinctrl",
++		.data = (ulong)&sun20i_d1_pinctrl_desc,
++	},
++#endif
+ #ifdef CONFIG_PINCTRL_SUN50I_A64
+ 	{
+ 		.compatible = "allwinner,sun50i-a64-pinctrl",

package/boot/uboot-d1/patches/0021-serial-ns16550-Enable-clocks-during-probe.patch

@@ -1,12 +1,11 @@
-From 0617377a2555031f02a459b3451fa33ce53e9b74 Mon Sep 17 00:00:00 2001
+From 8fde85b609273f8389178d4c0d066390a0e0773d Mon Sep 17 00:00:00 2001
 From: Samuel Holland <samuel@sholland.org>
 Date: Sun, 30 Oct 2022 14:56:10 -0500
-Subject: [PATCH 33/68] serial: ns16550: Enable clocks during probe
+Subject: [PATCH 21/90] serial: ns16550: Enable clocks during probe
 
 If the UART bus or baud clock has a gate, it must be enabled before the
 UART can be used.
 
-Reviewed-by: Stefan Roese <sr@denx.de>
 Signed-off-by: Samuel Holland <samuel@sholland.org>
 ---
  drivers/serial/ns16550.c | 5 +++++
@@ -14,15 +13,15 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
 
 --- a/drivers/serial/ns16550.c
 +++ b/drivers/serial/ns16550.c
-@@ -514,6 +514,7 @@ int ns16550_serial_probe(struct udevice
+@@ -506,6 +506,7 @@ int ns16550_serial_probe(struct udevice
  	struct ns16550_plat *plat = dev_get_plat(dev);
  	struct ns16550 *const com_port = dev_get_priv(dev);
  	struct reset_ctl_bulk reset_bulk;
 +	struct clk_bulk clk_bulk;
  	fdt_addr_t addr;
- 	fdt_addr_t size;
  	int ret;
-@@ -533,6 +534,10 @@ int ns16550_serial_probe(struct udevice
+ 
+@@ -524,6 +525,10 @@ int ns16550_serial_probe(struct udevice
  	if (!ret)
  		reset_deassert_bulk(&reset_bulk);
  

package/boot/uboot-d1/patches/0022-fdt-Fix-bounds-check-in-devfdt_get_addr_index.patch

@@ -1,7 +1,7 @@
-From 8d12d6e5730c80503840e3c18fafb9bed4133dc9 Mon Sep 17 00:00:00 2001
+From 0e4edc3a01f179337bb0bd0d31855dbce338a23e Mon Sep 17 00:00:00 2001
 From: Samuel Holland <samuel@sholland.org>
 Date: Sun, 30 Oct 2022 14:53:45 -0500
-Subject: [PATCH 07/68] fdt: Fix bounds check in devfdt_get_addr_index
+Subject: [PATCH 22/90] fdt: Fix bounds check in devfdt_get_addr_index
 
 reg must contain enough cells for the entire next address/size pair
 after skipping `index` pairs. The previous code allows an out-of-bounds
@@ -17,7 +17,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
 
 --- a/drivers/core/fdtaddr.c
 +++ b/drivers/core/fdtaddr.c
-@@ -44,7 +44,7 @@ fdt_addr_t devfdt_get_addr_index(const s
+@@ -43,7 +43,7 @@ fdt_addr_t devfdt_get_addr_index(const s
  		}
  
  		reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);

package/boot/uboot-d1/patches/0023-Kconfig-Remove-an-impossible-condition.patch

@@ -0,0 +1,25 @@
+From 2d85df851c590b454749ac989a778bb226637bfc Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Tue, 6 Jun 2023 15:08:39 +0000
+Subject: [PATCH 23/90] Kconfig: Remove an impossible condition
+
+ARCH_SUNXI selects BINMAN, so the condition "!BINMAN && ARCH_SUNXI"
+is impossible to satisfy.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Kconfig
++++ b/Kconfig
+@@ -459,7 +459,7 @@ config BUILD_TARGET
+ 	default "u-boot-with-spl.kwb" if ARCH_MVEBU && SPL
+ 	default "u-boot-elf.srec" if RCAR_GEN3
+ 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
+-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
++				RISCV || ARCH_ZYNQMP)
+ 	default "u-boot.kwb" if ARCH_KIRKWOOD
+ 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
+ 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL

package/boot/uboot-d1/patches/0024-binman-Prevent-entries-in-a-section-from-overlapping.patch

@@ -0,0 +1,33 @@
+From b7150f7dd885012868c94b29ac4fe6152c065a95 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 10:43:56 -0500
+Subject: [PATCH 24/90] binman: Prevent entries in a section from overlapping
+
+Currently, if the "offset" property is given for an entry, the section's
+running offset is completely ignored. This causes entries to overlap if
+the provided offset is less than the size of the entries earlier in the
+section. Avoid the overlap by only using the provided offset when it is
+greater than the running offset.
+
+The motivation for this change is the rule used by SPL to find U-Boot on
+sunxi boards: U-Boot starts 32 KiB after the start of SPL, unless SPL is
+larger than 32 KiB, in which case U-Boot immediately follows SPL.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ tools/binman/entry.py | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/tools/binman/entry.py
++++ b/tools/binman/entry.py
+@@ -483,7 +483,9 @@ class Entry(object):
+             if self.offset_unset:
+                 self.Raise('No offset set with offset-unset: should another '
+                            'entry provide this correct offset?')
+-            self.offset = tools.align(offset, self.align)
++        elif self.offset > offset:
++            offset = self.offset
++        self.offset = tools.align(offset, self.align)
+         needed = self.pad_before + self.contents_size + self.pad_after
+         needed = tools.align(needed, self.align_size)
+         size = self.size

package/boot/uboot-d1/patches/0025-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch

@@ -0,0 +1,192 @@
+From b641ca5f4d272b83ef77ebcf5c75678cf139c69a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 17 Apr 2021 13:33:54 -0500
+Subject: [PATCH 25/90] sunxi: binman: Enable SPL FIT loading for 32-bit SoCs
+
+Now that Crust (SCP firmware) has support for H3, we need a FIT image to
+load it. H3 also needs to load a SoC-specific eGon blob to support CPU 0
+hotplug. Let's first enable FIT support before adding extra firmware.
+
+Update the binman description to work on either 32-bit or 64-bit SoCs:
+ - Make BL31 optional, since it is not used on 32-bit SoCs (though BL32
+   may be used in the future).
+ - Explicitly set the minimum offset of the FIT to 32 KiB, since SPL on
+   some boards is still only 24 KiB large even with FIT support enabled.
+   CONFIG_SPL_PAD_TO cannot be used because it is not defined for H616.
+
+FIT unlocks more features (signatures, multiple DTBs, etc.), so enable
+it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs
+SPL_FIT_IMAGE_TINY. For simplicity, enable that option everywhere.
+
+Cover-letter:
+sunxi: SPL FIT support for 32-bit sunxi SoCs
+This series makes the necessary changes so 32-bit sunxi SoCs can load
+additional device trees or firmware from SPL along with U-Boot proper.
+
+There was no existing binman entry property that put the FIT at the
+right offset. The minimum offset is 32k, but this matches neither the
+SPL size (which is no more than 24k on some SoCs) nor the FIT alignment
+(which is 512 bytes in practice due to SPL size constraints). So instead
+of adding a new property, I fixed what is arguably a bug in the offset
+property -- though this strategy will not work if someone is
+intentionally creating overlapping entries.
+END
+Series-to: sunxi
+Series-to: sjg
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/Kconfig               |  1 +
+ arch/arm/dts/sunxi-u-boot.dtsi | 46 ++++++++++++++++++++++------------
+ common/spl/Kconfig             |  9 +++----
+ 3 files changed, 35 insertions(+), 21 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1135,6 +1135,7 @@ config ARCH_SUNXI
+ 	imply SPL_GPIO
+ 	imply SPL_LIBCOMMON_SUPPORT
+ 	imply SPL_LIBGENERIC_SUPPORT
++	imply SPL_LOAD_FIT
+ 	imply SPL_MMC if MMC
+ 	imply SPL_POWER
+ 	imply SPL_SERIAL
+--- a/arch/arm/dts/sunxi-u-boot.dtsi
++++ b/arch/arm/dts/sunxi-u-boot.dtsi
+@@ -1,13 +1,19 @@
+ #include <config.h>
+ 
+-#ifdef CONFIG_MACH_SUN50I_H6
+-#define BL31_ADDR 0x104000
+-#define  SCP_ADDR 0x114000
+-#elif defined(CONFIG_MACH_SUN50I_H616)
+-#define BL31_ADDR 0x40000000
++#ifdef CONFIG_ARM64
++#define ARCH "arm64"
+ #else
+-#define BL31_ADDR  0x44000
+-#define  SCP_ADDR  0x50000
++#define ARCH "arm"
++#endif
++
++#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
++#define BL31_ADDR	0x00044000
++#define SCP_ADDR	0x00050000
++#elif defined(CONFIG_MACH_SUN50I_H6)
++#define BL31_ADDR	0x00104000
++#define SCP_ADDR	0x00114000
++#elif defined(CONFIG_MACH_SUN50I_H616)
++#define BL31_ADDR	0x40000000
+ #endif
+ 
+ / {
+@@ -34,30 +40,33 @@
+ 			filename = "spl/sunxi-spl.bin";
+ 		};
+ 
+-#ifdef CONFIG_ARM64
++#ifdef CONFIG_SPL_LOAD_FIT
+ 		fit {
+-			description = "Configuration to load ATF before U-Boot";
++			description = "Configuration to load U-Boot and firmware";
++			offset = <32768>;
+ 			#address-cells = <1>;
+ 			fit,fdt-list = "of-list";
+ 
+ 			images {
+ 				uboot {
+-					description = "U-Boot (64-bit)";
++					description = "U-Boot";
+ 					type = "standalone";
+ 					os = "u-boot";
+-					arch = "arm64";
++					arch = ARCH;
+ 					compression = "none";
+ 					load = <CONFIG_TEXT_BASE>;
++					entry = <CONFIG_TEXT_BASE>;
+ 
+ 					u-boot-nodtb {
+ 					};
+ 				};
+ 
++#ifdef BL31_ADDR
+ 				atf {
+ 					description = "ARM Trusted Firmware";
+ 					type = "firmware";
+ 					os = "arm-trusted-firmware";
+-					arch = "arm64";
++					arch = ARCH;
+ 					compression = "none";
+ 					load = <BL31_ADDR>;
+ 					entry = <BL31_ADDR>;
+@@ -67,6 +76,7 @@
+ 						missing-msg = "atf-bl31-sunxi";
+ 					};
+ 				};
++#endif
+ 
+ #ifdef SCP_ADDR
+ 				scp {
+@@ -95,19 +105,23 @@
+ 
+ 				@config-SEQ {
+ 					description = "NAME";
++#ifdef BL31_ADDR
+ 					firmware = "atf";
+-#ifndef SCP_ADDR
+-					loadables = "uboot";
+ #else
+-					loadables = "scp", "uboot";
++					firmware = "uboot";
++#endif
++					loadables =
++#ifdef SCP_ADDR
++						    "scp",
+ #endif
++						    "uboot";
+ 					fdt = "fdt-SEQ";
+ 				};
+ 			};
+ 		};
+ #else
+ 		u-boot-img {
+-			offset = <CONFIG_SPL_PAD_TO>;
++			offset = <32768>;
+ 		};
+ #endif
+ 	};
+--- a/common/spl/Kconfig
++++ b/common/spl/Kconfig
+@@ -76,12 +76,12 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
+ 
+ config SPL_MAX_SIZE
+ 	hex "Maximum size of the SPL image, excluding BSS"
++	default 0x37fa0 if MACH_SUN50I_H616
+ 	default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
++	default 0x25fa0 if MACH_SUN50I_H6
+ 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
+ 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
+ 	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
+-	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
+-	default 0xbfa0 if MACH_SUN50I_H616
+ 	default 0x7000 if RCAR_GEN3
+ 	default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ 	default 0x10000 if ASPEED_AST2600
+@@ -97,7 +97,7 @@ config SPL_PAD_TO
+ 	default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
+ 	default 0x11000 if ARCH_MX7 || (ARCH_MX6 && !MX6_OCRAM_256KB)
+ 	default 0x10000 if ARCH_KEYSTONE
+-	default 0x8000 if ARCH_SUNXI && !MACH_SUN50I_H616
++	default 0x0 if ARCH_SUNXI
+ 	default 0x0 if ARCH_MTMIPS
+ 	default TPL_MAX_SIZE if TPL_MAX_SIZE > SPL_MAX_SIZE
+ 	default SPL_MAX_SIZE
+@@ -575,8 +575,7 @@ config SPL_MD5
+ config SPL_FIT_IMAGE_TINY
+ 	bool "Remove functionality from SPL FIT loading to reduce size"
+ 	depends on SPL_FIT
+-	default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
+-	default y if ARCH_IMX8M || ARCH_IMX9
++	default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI
+ 	help
+ 	  Enable this to reduce the size of the FIT image loading code
+ 	  in SPL, if space for the SPL binary is very tight.

package/boot/uboot-d1/patches/0026-sunxi-psci-Avoid-hanging-when-CPU-0-is-hot-unplugged.patch

@@ -0,0 +1,51 @@
+From ca1e6f4491981432c3e88441131c8e25067da95e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 9 Oct 2021 22:00:22 -0500
+Subject: [PATCH 26/90] sunxi: psci: Avoid hanging when CPU 0 is hot-unplugged
+
+Do not try to send an SGI from CPU 0 to itself. Since FIQs are masked
+when entering monitor mode, this will hang. Plus, CPU 0 cannot fully
+power itself off anyway. Instead, have it turn FIQs back on and continue
+servicing SGIs from other cores.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/cpu/armv7/sunxi/psci.c | 20 +++++++++++++++++---
+ 1 file changed, 17 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/cpu/armv7/sunxi/psci.c
++++ b/arch/arm/cpu/armv7/sunxi/psci.c
+@@ -38,6 +38,15 @@
+ #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
+ #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
+ 
++static inline u32 __secure cp15_read_mpidr(void)
++{
++	u32 val;
++
++	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
++
++	return val;
++}
++
+ static void __secure cp15_write_cntp_tval(u32 tval)
+ {
+ 	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+@@ -281,9 +290,14 @@ s32 __secure psci_cpu_off(void)
+ {
+ 	psci_cpu_off_common();
+ 
+-	/* Ask CPU0 via SGI15 to pull the rug... */
+-	writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
+-	dsb();
++	if (cp15_read_mpidr() & 3) {
++		/* Ask CPU0 via SGI15 to pull the rug... */
++		writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
++		dsb();
++	} else {
++		/* Unmask FIQs to service SGI15. */
++		asm volatile ("cpsie f");
++	}
+ 
+ 	/* Wait to be turned off */
+ 	while (1)

package/boot/uboot-d1/patches/0027-clk-sunxi-Add-NAND-clocks-and-resets.patch

@@ -0,0 +1,295 @@
+From 2f48dfc23d612f6f1798ff761854fd3141d0671f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 15 May 2022 21:29:22 -0500
+Subject: [PATCH 27/90] clk: sunxi: Add NAND clocks and resets
+
+Currently NAND clock setup is done in board code, both in SPL and in
+U-Boot proper. Add the NAND clocks/resets here so they can be used by
+the "full" NAND driver once it is converted to the driver model.
+
+The bit locations are copied from the Linux CCU drivers.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi/clk_a10.c  | 2 ++
+ drivers/clk/sunxi/clk_a10s.c | 2 ++
+ drivers/clk/sunxi/clk_a23.c  | 3 +++
+ drivers/clk/sunxi/clk_a31.c  | 6 ++++++
+ drivers/clk/sunxi/clk_a64.c  | 3 +++
+ drivers/clk/sunxi/clk_a80.c  | 8 ++++++++
+ drivers/clk/sunxi/clk_a83t.c | 3 +++
+ drivers/clk/sunxi/clk_h3.c   | 3 +++
+ drivers/clk/sunxi/clk_h6.c   | 6 ++++++
+ drivers/clk/sunxi/clk_h616.c | 6 ++++++
+ drivers/clk/sunxi/clk_r40.c  | 3 +++
+ 11 files changed, 45 insertions(+)
+
+--- a/drivers/clk/sunxi/clk_a10.c
++++ b/drivers/clk/sunxi/clk_a10.c
+@@ -23,6 +23,7 @@ static struct ccu_clk_gate a10_gates[] =
+ 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_AHB_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+@@ -47,6 +48,7 @@ static struct ccu_clk_gate a10_gates[] =
+ 	[CLK_APB1_UART6]	= GATE(0x06c, BIT(22)),
+ 	[CLK_APB1_UART7]	= GATE(0x06c, BIT(23)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+--- a/drivers/clk/sunxi/clk_a10s.c
++++ b/drivers/clk/sunxi/clk_a10s.c
+@@ -20,6 +20,7 @@ static struct ccu_clk_gate a10s_gates[]
+ 	[CLK_AHB_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_AHB_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_AHB_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_AHB_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
+@@ -35,6 +36,7 @@ static struct ccu_clk_gate a10s_gates[]
+ 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
+ 	[CLK_APB1_UART3]	= GATE(0x06c, BIT(19)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+--- a/drivers/clk/sunxi/clk_a23.c
++++ b/drivers/clk/sunxi/clk_a23.c
+@@ -17,6 +17,7 @@ static struct ccu_clk_gate a23_gates[] =
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+ 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
+@@ -34,6 +35,7 @@ static struct ccu_clk_gate a23_gates[] =
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -52,6 +54,7 @@ static struct ccu_reset a23_resets[] = {
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+ 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
+--- a/drivers/clk/sunxi/clk_a31.c
++++ b/drivers/clk/sunxi/clk_a31.c
+@@ -18,6 +18,8 @@ static struct ccu_clk_gate a31_gates[] =
+ 	[CLK_AHB1_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_AHB1_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_AHB1_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_AHB1_NAND1]	= GATE(0x060, BIT(12)),
++	[CLK_AHB1_NAND0]	= GATE(0x060, BIT(13)),
+ 	[CLK_AHB1_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_AHB1_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_AHB1_SPI1]		= GATE(0x060, BIT(21)),
+@@ -43,6 +45,8 @@ static struct ccu_clk_gate a31_gates[] =
+ 	[CLK_APB2_UART4]	= GATE(0x06c, BIT(20)),
+ 	[CLK_APB2_UART5]	= GATE(0x06c, BIT(21)),
+ 
++	[CLK_NAND0]		= GATE(0x080, BIT(31)),
++	[CLK_NAND1]		= GATE(0x084, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+@@ -65,6 +69,8 @@ static struct ccu_reset a31_resets[] = {
+ 	[RST_AHB1_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_AHB1_MMC2]		= RESET(0x2c0, BIT(10)),
+ 	[RST_AHB1_MMC3]		= RESET(0x2c0, BIT(11)),
++	[RST_AHB1_NAND1]	= RESET(0x2c0, BIT(12)),
++	[RST_AHB1_NAND0]	= RESET(0x2c0, BIT(13)),
+ 	[RST_AHB1_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_AHB1_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_AHB1_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_a64.c
++++ b/drivers/clk/sunxi/clk_a64.c
+@@ -19,6 +19,7 @@ static const struct ccu_clk_gate a64_gat
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -39,6 +40,7 @@ static const struct ccu_clk_gate a64_gat
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -58,6 +60,7 @@ static const struct ccu_reset a64_resets
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_a80.c
++++ b/drivers/clk/sunxi/clk_a80.c
+@@ -14,12 +14,18 @@
+ #include <linux/bitops.h>
+ 
+ static const struct ccu_clk_gate a80_gates[] = {
++	[CLK_NAND0_0]		= GATE(0x400, BIT(31)),
++	[CLK_NAND0_1]		= GATE(0x404, BIT(31)),
++	[CLK_NAND1_0]		= GATE(0x408, BIT(31)),
++	[CLK_NAND1_1]		= GATE(0x40c, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x430, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x434, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x438, BIT(31)),
+ 	[CLK_SPI3]		= GATE(0x43c, BIT(31)),
+ 
+ 	[CLK_BUS_MMC]		= GATE(0x580, BIT(8)),
++	[CLK_BUS_NAND0]		= GATE(0x580, BIT(12)),
++	[CLK_BUS_NAND1]		= GATE(0x580, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x580, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x580, BIT(21)),
+ 	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
+@@ -42,6 +48,8 @@ static const struct ccu_clk_gate a80_gat
+ 
+ static const struct ccu_reset a80_resets[] = {
+ 	[RST_BUS_MMC]		= RESET(0x5a0, BIT(8)),
++	[RST_BUS_NAND0]		= RESET(0x5a0, BIT(12)),
++	[RST_BUS_NAND1]		= RESET(0x5a0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x5a0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x5a0, BIT(21)),
+ 	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
+--- a/drivers/clk/sunxi/clk_a83t.c
++++ b/drivers/clk/sunxi/clk_a83t.c
+@@ -17,6 +17,7 @@ static struct ccu_clk_gate a83t_gates[]
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -36,6 +37,7 @@ static struct ccu_clk_gate a83t_gates[]
+ 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
+ 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -54,6 +56,7 @@ static struct ccu_reset a83t_resets[] =
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_h3.c
++++ b/drivers/clk/sunxi/clk_h3.c
+@@ -19,6 +19,7 @@ static struct ccu_clk_gate h3_gates[] =
+ 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+@@ -44,6 +45,7 @@ static struct ccu_clk_gate h3_gates[] =
+ 
+ 	[CLK_BUS_EPHY]		= GATE(0x070, BIT(0)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 
+@@ -66,6 +68,7 @@ static struct ccu_reset h3_resets[] = {
+ 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+--- a/drivers/clk/sunxi/clk_h6.c
++++ b/drivers/clk/sunxi/clk_h6.c
+@@ -18,6 +18,10 @@ static struct ccu_clk_gate h6_gates[] =
+ 
+ 	[CLK_APB1]		= GATE_DUMMY,
+ 
++	[CLK_NAND0]		= GATE(0x810, BIT(31)),
++	[CLK_NAND1]		= GATE(0x814, BIT(31)),
++	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
++
+ 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+ 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+ 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+@@ -58,6 +62,8 @@ static struct ccu_clk_gate h6_gates[] =
+ };
+ 
+ static struct ccu_reset h6_resets[] = {
++	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
++
+ 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+ 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+ 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+--- a/drivers/clk/sunxi/clk_h616.c
++++ b/drivers/clk/sunxi/clk_h616.c
+@@ -17,6 +17,10 @@ static struct ccu_clk_gate h616_gates[]
+ 
+ 	[CLK_APB1]		= GATE_DUMMY,
+ 
++	[CLK_NAND0]		= GATE(0x810, BIT(31)),
++	[CLK_NAND1]		= GATE(0x814, BIT(31)),
++	[CLK_BUS_NAND]		= GATE(0x82c, BIT(0)),
++
+ 	[CLK_BUS_MMC0]		= GATE(0x84c, BIT(0)),
+ 	[CLK_BUS_MMC1]		= GATE(0x84c, BIT(1)),
+ 	[CLK_BUS_MMC2]		= GATE(0x84c, BIT(2)),
+@@ -67,6 +71,8 @@ static struct ccu_clk_gate h616_gates[]
+ };
+ 
+ static struct ccu_reset h616_resets[] = {
++	[RST_BUS_NAND]		= RESET(0x82c, BIT(16)),
++
+ 	[RST_BUS_MMC0]		= RESET(0x84c, BIT(16)),
+ 	[RST_BUS_MMC1]		= RESET(0x84c, BIT(17)),
+ 	[RST_BUS_MMC2]		= RESET(0x84c, BIT(18)),
+--- a/drivers/clk/sunxi/clk_r40.c
++++ b/drivers/clk/sunxi/clk_r40.c
+@@ -18,6 +18,7 @@ static struct ccu_clk_gate r40_gates[] =
+ 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
+ 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
+ 	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
++	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
+ 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
+ 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
+ 	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
+@@ -48,6 +49,7 @@ static struct ccu_clk_gate r40_gates[] =
+ 	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
+ 	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
+ 
++	[CLK_NAND]		= GATE(0x080, BIT(31)),
+ 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
+ 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
+ 	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
+@@ -70,6 +72,7 @@ static struct ccu_reset r40_resets[] = {
+ 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
+ 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
+ 	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
++	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
+ 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
+ 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
+ 	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),