oops

This reverts commit d8c455f988.

let's try ethernet again!

target/linux/octeon/config-5.4

@@ -214,9 +214,9 @@ CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
 CONFIG_NR_CPUS=16
 CONFIG_NR_CPUS_DEFAULT_64=y
 CONFIG_NVMEM=y
-CONFIG_OCTEON_ETHERNET=n
+CONFIG_OCTEON_ETHERNET=y
 CONFIG_OCTEON_ILM=y
-CONFIG_OCTEON_MGMT_ETHERNET=n
+CONFIG_OCTEON_MGMT_ETHERNET=y
 CONFIG_OCTEON_USB=y
 CONFIG_OCTEON_WDT=y
 CONFIG_OF=y

target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/snic10e.dts

@@ -116,7 +116,6 @@
 			reg = <0x11800 0x00001800 0x0 0x40>;
 			status = "disabled";
 			mphyA: ethernet-phy-nexus@A {
-				status = "disabled";
 				reg = <0>;
 				/* The Vitesse VSC8488 is a dual-PHY where
 				 * some of the configuration is common across
@@ -133,7 +132,6 @@
 				reset = <&gpio 17 0>;
 
 				phy0: ethernet-phy@0 {
-					status = "disabled";
 					/* Absolute address */
 					reg = <0>;
 					compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
@@ -350,7 +348,6 @@
 				};
 
 				phy1: ethernet-phy@1 {
-					status = "disabled";
 					/* Absolute address */
 					reg = <0x1>;
 					compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
@@ -567,7 +564,6 @@
 				};
 			};
 			mphyB: ethernet-phy-nexus@B {
-				status = "disabled";
 				reg = <0>;
 				/* The TI TLK10232 is a dual-PHY where
 				 * some of the configuration is common across
@@ -584,7 +580,6 @@
 				reset = <&gpio 17 2>;
 
 				phy11: ethernet-phy@0 {
-					status = "disabled";
 					/* Absolute address */
 					reg = <0>;
 					compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
@@ -608,7 +603,6 @@
 				};
 
 				phy10: ethernet-phy@1 {
-					status = "disabled";
 					/* Absolute address */
 					reg = <0x1>;
 					compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";

target/linux/octeon/patches-5.4/702-honor_xaui_node_device_tree_status.patch

@@ -1,15 +0,0 @@
---- a/drivers/staging/octeon/ethernet.c
-+++ b/drivers/staging/octeon/ethernet.c
-@@ -860,8 +860,10 @@ static int cvm_oct_probe(struct platform_device *pdev)
- 				break;
- 
- 			case CVMX_HELPER_INTERFACE_MODE_XAUI:
--				dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
--				strscpy(dev->name, "xaui%d", sizeof(dev->name));
-+				if (0) { //of_device_is_available(priv->of_node)) {
-+					dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
-+					strscpy(dev->name, "xaui%d", sizeof(dev->name));
-+				}
- 				break;
- 
- 			case CVMX_HELPER_INTERFACE_MODE_LOOP:

target/linux/octeon/patches-5.4/703-debug-it-all.patch

@@ -0,0 +1,79 @@
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
+@@ -1041,12 +1041,14 @@ int cvmx_helper_initialize_packet_io_global(void)
+ 		result |= __cvmx_helper_interface_setup_ipd(interface);
+ 		result |= __cvmx_helper_interface_setup_pko(interface);
+ 	}
+-
++	cvmx_dprintf("Gets past end of interfaces setup\n");
+ 	result |= __cvmx_helper_global_setup_ipd();
+ 	result |= __cvmx_helper_global_setup_pko();
+ 
++	cvmx_dprintf("Sets up global helpers\n");
+ 	/* Enable any flow control and backpressure */
+ 	result |= __cvmx_helper_global_setup_backpressure();
++	cvmx_dprintf("Sets up backpressure helpers\n");
+ 
+ #if CVMX_HELPER_ENABLE_IPD
+ 	result |= cvmx_helper_ipd_and_packet_input_enable();
+--- a/drivers/staging/octeon/ethernet.c
++++ b/drivers/staging/octeon/ethernet.c
+@@ -700,6 +700,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 	cvm_oct_configure_common_hw();
+ 
+ 	cvmx_helper_initialize_packet_io_global();
++	pr_err("OK, we got out of packet_io_global()\n");
+ 
+ 	if (receive_group_order) {
+ 		if (receive_group_order > 4)
+@@ -709,9 +710,11 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 		pow_receive_groups = BIT(pow_receive_group);
+ 	}
+ 
++	pr_err("We got through receive_group_order\n");
+ 	/* Change the input group for all ports before input is enabled */
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
++		pr_err("We are starting on interface %d\n", interface);
+ 		int num_ports = cvmx_helper_ports_on_interface(interface);
+ 		int port;
+ 
+@@ -752,14 +755,14 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 				pip_prt_tagx.s.grptag	= 0;
+ 				pip_prt_tagx.s.grp	= pow_receive_group;
+ 			}
+-
++			pr_err("COULD IT BE CSR WRITES???\n");
+ 			cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
+ 				       pip_prt_tagx.u64);
+ 		}
+ 	}
+-
++	pr_err("COULD it be cvmx_helper_ipd_and_packet_input_enable???\n");
+ 	cvmx_helper_ipd_and_packet_input_enable();
+-
++	pr_err("COULD it be this memset??\n");
+ 	memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
+ 
+ 	/*
+@@ -804,6 +807,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	pr_err("OK, we got THIS far, all the way to the interface init. Which is weird, we shoulda crashed by now\n");
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
+ 		cvmx_helper_interface_mode_t imode =
+@@ -860,8 +864,10 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 				break;
+ 
+ 			case CVMX_HELPER_INTERFACE_MODE_XAUI:
+-				dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
+-				strscpy(dev->name, "xaui%d", sizeof(dev->name));
++				if (of_device_is_available(priv->of_node)) {
++					dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
++					strscpy(dev->name, "xaui%d", sizeof(dev->name));
++				}
+ 				break;
+ 
+ 			case CVMX_HELPER_INTERFACE_MODE_LOOP:

target/linux/octeon/patches-5.4/704-more-debugs.patch

@@ -0,0 +1,48 @@
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
+@@ -971,6 +971,7 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
+ 	int interface;
+ 
+ 	/* Enable IPD */
++    cvmx_dprintf("COULD IT BE cvmx_ipd_enable???\n");
+ 	cvmx_ipd_enable();
+ 
+ 	/*
+@@ -978,13 +979,16 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
+ 	 * that at this point IPD/PIP must be fully functional and PKO
+ 	 * must be disabled
+ 	 */
++    cvmx_dprintf("COULD IT BE getting no of interfaces????\n");
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
++      cvmx_dprintf("COULD IT BE interface # %d ??ces????\n", interface);
+ 		if (cvmx_helper_ports_on_interface(interface) > 0)
+ 			__cvmx_helper_packet_hardware_enable(interface);
+ 	}
+ 
+ 	/* Finally enable PKO now that the entire path is up and running */
++    cvmx_dprintf("COULD IT BE PKO???\n");
+ 	cvmx_pko_enable();
+ 
+ 	if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1)
+--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
++++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
+@@ -129,15 +129,18 @@ static inline void cvmx_ipd_config(uint64_t mbuff_size,
+ static inline void cvmx_ipd_enable(void)
+ {
+ 	union cvmx_ipd_ctl_status ipd_reg;
++	cvmx_dprintf("COULD IT BE THIS ONE CSR READ IN cvmx_ipd_enable ??\n");
+ 	ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+ 	if (ipd_reg.s.ipd_en) {
+ 		cvmx_dprintf
+ 		    ("Warning: Enabling IPD when IPD already enabled.\n");
+ 	}
++    cvmx_dprintf("OK IT PASSED THE READ. BUT THERE'S THIS CVMX_ENABLE_LEN_M8_FIX THAT COULD APPLY??\n");
+ 	ipd_reg.s.ipd_en = 1;
+ #if  CVMX_ENABLE_LEN_M8_FIX
+ 	if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ 		ipd_reg.s.len_m8 = TRUE;
+ #endif
++    cvmx_dprintf("COULD IT BE THIS ONE CSR WRITE??? IN cvmx_ipd_enable ??\n");
+ 	cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+ }

target/linux/octeon/patches-5.4/705-last-debugs.patch

@@ -0,0 +1,186 @@
+diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+index 93a498d05184..27733d710355 100644
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+@@ -121,58 +121,80 @@ int __cvmx_helper_xaui_enable(int interface)
+ 	union cvmx_gmxx_tx_int_en gmx_tx_int_en;
+ 	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
+ 
++    cvmx_dprintf("COULD IT BE THE FEATURE CHECK FOR PKND??\n");
+ 	/* Setup PKND */
+ 	if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
++      cvmx_dprintf("COULD IT BE THE FIRST CSR READ??\n");
+ 		gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
++        cvmx_dprintf("COULD IT BE THE second CSR READ??\n");
+ 		gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
++        cvmx_dprintf("COULD IT BE THE third CSR /write READ??\n");
+ 		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 	}
+ 
+ 	/* (1) Interface has already been enabled. */
+ 
+ 	/* (2) Disable GMX. */
++    cvmx_dprintf("step2 start!?? could it be the csr read??\n");
+ 	xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
+ 	xauiMiscCtl.s.gmxeno = 1;
++    cvmx_dprintf("step2 could it be the csr write to disable gmx??\n");
+ 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+ 
+ 	/* (3) Disable GMX and PCSX interrupts. */
++    cvmx_dprintf("step3 start. could it be the csr read??\n");
+ 	gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
++    cvmx_dprintf("step3 start. could it be the write for disabling interrupts???\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
++    cvmx_dprintf("step3 start. could it be read for setting up the gmx_tx_int_en???\n");
+ 	gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
++    cvmx_dprintf("step3 start. could it be the cvmx_gmxx write???\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
++    cvmx_dprintf("step3 start almost done. show up tell us about the PCSXX write???\n");
+ 	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
++    cvmx_dprintf("step3, this final csr write?\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+ 
+ 	/* (4) Bring up the PCSX and GMX reconciliation layer. */
+ 	/* (4)a Set polarity and lane swapping. */
+ 	/* (4)b */
++    cvmx_dprintf("4.1\n");
+ 	gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+ 	/* Enable better IFG packing and improves performance */
+ 	gmxXauiTxCtl.s.dic_en = 1;
+ 	gmxXauiTxCtl.s.uni_en = 0;
++    cvmx_dprintf("4.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
+ 
+ 	/* (4)c Aply reset sequence */
++    cvmx_dprintf("4.3\n");
+ 	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
+ 	xauiCtl.s.lo_pwr = 0;
+ 
+ 	/* Issuing a reset here seems to hang some CN68XX chips. */
+ 	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
+-	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
++	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X) &&
++        0)
+ 		xauiCtl.s.reset = 1;
+ 
++    cvmx_dprintf("4.4\n");
+ 	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
+ 
++    cvmx_dprintf("4.5\n");
+ 	/* Wait for PCS to come out of reset */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
+ 	     reset, ==, 0, 10000))
+ 		return -1;
++
++    cvmx_dprintf("4.6\n");
+ 	/* Wait for PCS to be aligned */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_10GBX_STATUS_REG(interface),
+ 	     union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
+ 		return -1;
++
++    cvmx_dprintf("4.7\n");
+ 	/* Wait for RX to be ready */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
+@@ -180,8 +202,11 @@ int __cvmx_helper_xaui_enable(int interface)
+ 		return -1;
+ 
+ 	/* (6) Configure GMX */
++    cvmx_dprintf("6.1\n");
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
++
+ 	gmx_cfg.s.en = 0;
++    cvmx_dprintf("6.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
+ 	/* Wait for GMX RX to be idle */
+@@ -189,62 +214,87 @@ int __cvmx_helper_xaui_enable(int interface)
+ 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+ 		    rx_idle, ==, 1, 10000))
+ 		return -1;
++    cvmx_dprintf("6.3\n");
+ 	/* Wait for GMX TX to be idle */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+ 		    tx_idle, ==, 1, 10000))
+ 		return -1;
+ 
++    cvmx_dprintf("6.4\n");
+ 	/* GMX configure */
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+ 	gmx_cfg.s.speed = 1;
+ 	gmx_cfg.s.speed_msb = 0;
+ 	gmx_cfg.s.slottime = 1;
++    cvmx_dprintf("6.5\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
++    cvmx_dprintf("6.6\n");
+ 	cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
++    cvmx_dprintf("6.7\n");
+ 	cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
++    cvmx_dprintf("6.8\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
+ 	/* (7) Clear out any error state */
++    cvmx_dprintf("7.1\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
+ 		       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
++    cvmx_dprintf("7.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
+ 		       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
++    cvmx_dprintf("7.3\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
+ 		       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
+ 
++    cvmx_dprintf("7.4\n");
+ 	/* Wait for receive link */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
+ 	     rcv_lnk, ==, 1, 10000))
+ 		return -1;
++    cvmx_dprintf("7.5\n");
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+ 	     xmtflt, ==, 0, 10000))
+ 		return -1;
++    cvmx_dprintf("7.6\n");
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+ 	     rcvflt, ==, 0, 10000))
+ 		return -1;
+ 
++    cvmx_dprintf("7.7\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
++    cvmx_dprintf("7.8\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
++    cvmx_dprintf("7.9\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
+ 
+ 	/* (8) Enable packet reception */
+ 	xauiMiscCtl.s.gmxeno = 0;
++    cvmx_dprintf("8.1\n");
+ 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+ 
++    cvmx_dprintf("8.2\n");
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+ 	gmx_cfg.s.en = 1;
++    cvmx_dprintf("8.3\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
++    cvmx_dprintf("8.4\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
++    cvmx_dprintf("8.5\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
++    cvmx_dprintf("8.6\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
++    cvmx_dprintf("8.7\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
++    cvmx_dprintf("8.8\n");
+ 	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
++    cvmx_dprintf("8.9\n");
+ 	__cvmx_interrupt_gmxx_enable(interface);
++    cvmx_dprintf("8.10\n");
+ 
+ 	return 0;
+ }