oops

This reverts commit d8c455f988.

let's try ethernet again!

target/linux/octeon/base-files/lib/preinit/01_sysinfo

@@ -22,6 +22,10 @@ do_sysinfo_octeon() {
 		return 0
 		;;
 
+	"SNIC10E"*)
+		name="snic10e"
+		;;
+
 	"ITUS_SHIELD"*)
 		name="itus,shield-router"
 		;;

target/linux/octeon/config-5.4

@@ -24,8 +24,9 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BLK_SCSI_REQUEST=y
 CONFIG_BUILTIN_DTB=y
-# CONFIG_CAVIUM_CN63XXP1 is not set
+CONFIG_CAVIUM_CN63XXP1=y
 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0
+CONFIG_CAVIUM_OCTEON2=y
 CONFIG_CAVIUM_OCTEON_LOCK_L2=y
 CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
 CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y

target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/snic10e.dts

@@ -0,0 +1,847 @@
+/dts-v1/;
+/*
+ * Cavium Inc. (Small) NIC10e board
+ */
+/ {
+	model = "cavium,snic10e";
+	compatible = "cavium,snic10e";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&ciu>;
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges; /* Direct mapping */
+
+		ciu: interrupt-controller@1070000000000 {
+			compatible = "cavium,octeon-3860-ciu";
+			interrupt-controller;
+			/* Interrupts are specified by two parts:
+			 * 1) Controller register (0 or 1)
+			 * 2) Bit within the register (0..63)
+			 */
+			#interrupt-cells = <2>;
+			reg = <0x10700 0x00000000 0x0 0x7000>;
+		};
+
+		gpio: gpio-controller@1070000000800 {
+			#gpio-cells = <2>;
+			compatible = "cavium,octeon-3860-gpio";
+			reg = <0x10700 0x00000800 0x0 0x100>;
+			gpio-controller;
+			/* Interrupts are specified by two parts:
+			 * 1) GPIO pin number (0..15)
+			 * 2) Triggering (1 - edge rising
+			 *		  2 - edge falling
+			 *		  4 - level active high
+			 *		  8 - level active low)
+			 */
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			/* The GPIO pins connect to 16 consecutive CUI bits */
+			interrupts = <0 16>; /* <0 17> <0 18> <0 19>
+				     <0 20> <0 21> <0 22> <0 23>
+				     <0 24> <0 25> <0 26> <0 27>
+				     <0 28> <0 29> <0 30> <0 31>; */
+		};
+
+		twsi0: i2c@1180000001000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-3860-twsi";
+			reg = <0x11800 0x00001000 0x0 0x200>;
+			interrupts = <0 45>;
+			/* NOTE: In order to get the proper delay between
+			 * i2c bus transactions for the SFP we need to either
+			 * slow the bus down to no more than 30KHz or else
+			 * somehow insert a delay between transactions.  Only
+			 * U-Boot is capable of inserting the appropriate delay
+			 * at this time.
+			 */
+			clock-frequency = <30000>;
+
+			tmp@4c {
+				compatible = "ti,tmp421";
+				reg = <0x4c>;
+			};
+			sfp0: eeprom@50 {
+				compatible = "atmel,24c01";
+				reg = <0x50>;
+			};
+			tlv-eeprom@53 {
+				compatible = "atmel,24c256";
+				reg = <0x53>;
+				pagesize = <64>;
+			};
+		};
+
+		twsi1: i2c@1180000001200 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "cavium,octeon-3860-twsi";
+			reg = <0x11800 0x00001200 0x0 0x200>;
+			interrupts = <0 59>;
+			/* NOTE: In order to get the proper delay between
+			 * i2c bus transactions for the SFP we need to either
+			 * slow the bus down to no more than 30KHz or else
+			 * somehow insert a delay between transactions.  Only
+			 * U-Boot is capable of inserting the appropriate delay
+			 * at this time.
+			 */
+			clock-frequency = <30000>;
+
+			sfp1: eeprom@50 {
+				compatible = "atmel,24c01";
+				reg = <0x50>;
+			};
+			gpio1: gpio@20 {
+				reg = <0x20>;
+				compatible = "nxp,pca9554";
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-parent = <&gpio>;
+				interrupt = <13 2>; /* OCTEON GPIO 13, falling edge */
+				#interrupt-cells = <1>;
+				cavium,phy-trim = "0,ti";
+			};
+
+		};
+
+		smi0: mdio@1180000001800 {
+			compatible = "cavium,octeon-3860-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x11800 0x00001800 0x0 0x40>;
+			status = "disabled";
+			mphyA: ethernet-phy-nexus@A {
+				reg = <0>;
+				/* The Vitesse VSC8488 is a dual-PHY where
+				 * some of the configuration is common across
+				 * both of the phy devices such as the reset
+				 * line and the base MDIO address.
+				 */
+				compatible = "vitesse,vsc8488-nexus", "ethernet-phy-nexus";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ranges;
+				cavium,phy-trim = "0,vitesse";
+
+				/* Hardware reset signal */
+				reset = <&gpio 17 0>;
+
+				phy0: ethernet-phy@0 {
+					/* Absolute address */
+					reg = <0>;
+					compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
+					interrupt-parent = <&gpio>;
+					interrupts = <13 8>;
+
+					mod_abs = <0>;
+					/* TX Fault GPIO line */
+					tx_fault = <1>;
+					/* GPIO that enables output */
+					txon = <4>;
+					/* INT A GPIO output */
+					inta = <5>;
+
+					/* Optional equalization value to
+					 * program into the PHY XS XAUI Rx
+					 * Equalization control register.
+					 * It is broken up into one nibble for
+					 * each lane with lane 0 using bits
+					 * 12 - 15.
+					 * Use the following table:
+					 *	0x0 - 0dB
+					 *	0x1 - 1.41dB
+					 *	0x2 - 2.24dB
+					 *	0x3 - 2.83dB
+					 *	0x5 - 4.48dB
+					 *	0x6 - 5.39dB
+					 *	0x7 - 6.07dB
+					 *	0x9 - 6.18dB
+					 *	0xA - 7.08dB (default)
+					 *	0xB - 7.79dB
+					 *	0xD - 9.96dB
+					 *	0xE - 10.84dB
+					 *	0xF - 11.55dB
+					 *
+					 * This is board specific and should
+					 * only be defined by the hardware
+					 * vendor.
+					 */
+					vitesse,rx_equalization = <0x0000>;
+					/* Optional transmit pre-emphasis
+					 * control.  This sets the
+					 * PHY XS XAUI TX pre-emphasis control
+					 * register.
+					 *
+					 * It uses bits 13-14 for lane 0,
+					 * 10-11 for lane 1, 7-8 for lane 2
+					 * and 4-5 for lane 3.
+					 *
+					 * Bits 2-3 are the LOS threshold
+					 * setting and bit 1 enables
+					 * the XAUI output high swing mode.
+					 *
+					 * Use the following table for
+					 * pre-emphasis:
+					 * 0b00 - 0dB
+					 * 0b01 - 2.5dB
+					 * 0b10 - 6dB (default)
+					 * 0b11 - 12dB
+					 *
+					 * Use the following table for the LOS
+					 * threshold setting:
+					 *
+					 * 0b00 - 50mV - 175mV (default)
+					 * 0b01 - 60mV - 185mV
+					 * 0b10 - 70mV - 195mV
+					 * 0b11 - 80mV - 205mV
+					 */
+					vitesse,tx_preemphasis = <0x0000>;
+
+					/* TX output driver slew rate control
+					 * is bits 8-11 where 0x0 is the minimum
+					 * and 0xF is the maximum.
+					 * Default is 0xA.
+					 *
+					 * The TX output driver C(-1)
+					 * coefficient is bits 0-4 where
+					 * 0b00000 is the minimum (-4ma) and
+					 * 0b11111 is the maximum (4ma).  The
+					 * default 0x 0b01111.
+					 */
+					vitesse,txout_driver_ctrl1 = <0x0A0F>;
+
+					/* The TX output driver C(0) coefficient
+					 * is bits 8-12 with 0b00000 being the
+					 * minimum (0mA) and 0b11111 being
+					 * the maximum (16mA). The default is
+					 * 0b10011
+					 *
+					 * The C(+1) coefficient is bits 0-5
+					 * with 0b000000 being the minimum
+					 * (-0.25mA) and 0b111111 being the
+					 * maximum (-16mA).  The default is
+					 * 0b000000.
+					 */
+					/*vitesse,txout_driver_ctrl2 = <0x1300>;*/
+
+					/* DC_AGC_LOS_CONFIG1:
+					 *   15: Suppress_Coarse_Adj_on_LOS_Clear
+					 *	0: DC offset correction performed using coarse
+					 *	   resolution mode (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   mode when correction resumes after LOPC/LOS alarms
+					 *	   clear.  This guarantees there will be no big jumps in
+					 *	   the offset at the expense of taking longer to reach
+					 *	   optimal setting.
+					 *   14: Force_DC2_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   13: Force_DC1_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   12: Force_DC0_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   10: Skip_DC2_Adj, 1 = skip DC2 offset correction
+					 *   9:  Skip_DC1_Adj, 1 = skip DC1 offset correction
+					 *   8:  Skip_DC0_Adj, 1 = skip DC0 offset correction
+					 *
+					 *   6-4: DC_Offset_Alarm_Mode (default 1)
+					 *	Selects the alarm condition that will halt the DC offset
+					 *	correction logic when the alarm(s) are set.
+					 *	111: reserved
+					 *	110: reserved
+					 *	101: LOPC and software LOS detection
+					 *	100: LOPC and hardware LOS detection
+					 *	011: Software LOS detection
+					 *	010: Hardware LOS detection
+					 *	001: LOPC
+					 *	000: Never.  DC offset correction will continue to make
+					 *	     fine resolution adjustments to the offsets even
+					 *	     when LOPC and LOS alarms are present.
+					 *
+					 *  3: AGC_Enable
+					 *	Selects when hardware AGC adjustment logic and LOS
+					 *	detection logic is enabled (default 1)
+					 *	0: disabled
+					 *	1: enabled
+					 *  2: AGC_Suspend
+					 *	Suspends the LOS detection logic and AGC logic
+					 *	from making adjustments to the gain.  Bit valid only
+					 *	if AGC_Enable=1
+					 *	0: AGC adjustment enabled (default)
+					 *	1: AGC adjustment suspended
+					 *  1: DC_Offset_Adj_Enable
+					 *	Select when the hardware DC offset correction logic is
+					 *	enabled.
+					 *	0: disable
+					 *	1: enable (default)
+					 *  0: DC_Offset_Adj_Suspend
+					 *	Suspends the DC offset correction logic from making
+					 *	adjustments to all offset settings.  Bit valid only if
+					 *	DC_Offset_Adj_Enable=1
+					 *	0: DC offset correction enabled (default)
+					 *	1: DC offset correction suspended
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_dc_agc_los_config1 = <0x000A>;
+
+					/* Disable aggressive track phase during
+					 * firmware convergence if 0, enabled
+					 * otherwise (default).
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_agg_track_phase = <0>;
+
+					/* AGC_Config4
+					 *
+					 * 13-8: Ampl_Tolerance
+					 *	This defines the hysterisis
+					 *	built in to the AGC adjustment
+					 *	circuit.  The VGA gain will not
+					 *	be adjusted as long as the
+					 *	measured input amplitude is
+					 *	Inp_Ampl_Target +/- Amnpl_Tolerance.
+					 *	 Default is 4.
+					 * 7-0: Inp_Ampl_Target
+					 *	This is the target amplitude
+					 *	desired to be measured at the
+					 *	peak detector when measuring
+					 *	input amplitude.  The VGA gain
+					 *	is adjusted to achieve this
+					 *	target setting.
+					 *	Default is 0x6E.
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_agc_config4 = <0x0496>;
+
+					/* The Vitesse 10G PHY does not
+					 * automatically read the SFP EEPROM
+					 * so the host needs to do it to put
+					 * the PHY in the proper mode for
+					 * copper or optical.
+					 */
+					sfp-eeprom = <&sfp0>;
+				};
+
+				phy1: ethernet-phy@1 {
+					/* Absolute address */
+					reg = <0x1>;
+					compatible = "vitesse,vsc8488", "ethernet-phy-ieee802.3-c45";
+					interrupt-parent = <&gpio>;
+					interrupts = <13 8>;
+
+					mod_abs = <9>;
+					/* TX Fault GPIO line */
+					tx_fault = <8>;
+					/* GPIO that enables output */
+					txon = <10>;
+					/* INT A GPIO output */
+					inta = <5>;
+
+					/* Optional equalization value to
+					 * program into the PHY XS XAUI Rx
+					 * Equalization control register.
+					 * It is broken up into one nibble for
+					 * each lane with lane 0 using bits
+					 * 12 - 15.
+					 * Use the following table:
+					 *	0x0 - 0dB
+					 *	0x1 - 1.41dB
+					 *	0x2 - 2.24dB
+					 *	0x3 - 2.83dB
+					 *	0x5 - 4.48dB
+					 *	0x6 - 5.39dB
+					 *	0x7 - 6.07dB
+					 *	0x9 - 6.18dB
+					 *	0xA - 7.08dB (default)
+					 *	0xB - 7.79dB
+					 *	0xD - 9.96dB
+					 *	0xE - 10.84dB
+					 *	0xF - 11.55dB
+					 *
+					 * This is board specific and should
+					 * only be defined by the hardware
+					 * vendor.
+					 */
+					rx_equalization = <0x0000>;
+					/* Optional transmit pre-emphasis
+					 * control.  This sets the
+					 * PHY XS XAUI TX pre-emphasis control
+					 * register.
+					 *
+					 * It uses bits 13-14 for lane 0,
+					 * 10-11 for lane 1, 7-8 for lane 2
+					 * and 4-5 for lane 3.
+					 *
+					 * Bits 2-3 are the LOS threshold
+					 * setting and bit 1 enables
+					 * the XAUI output high swing mode.
+					 *
+					 * Use the following table for
+					 * pre-emphasis:
+					 * 0b00 - 0dB
+					 * 0b01 - 2.5dB
+					 * 0b10 - 6dB (default)
+					 * 0b11 - 12dB
+					 *
+					 * Use the following table for the LOS
+					 * threshold setting:
+					 *
+					 * 0b00 - 50mV - 175mV (default)
+					 * 0b01 - 60mV - 185mV
+					 * 0b10 - 70mV - 195mV
+					 * 0b11 - 80mV - 205mV
+					 */
+					tx_preemphasis = <0x0000>;
+
+					/* TX output driver slew rate control
+					 * is bits 8-11 where 0x0 is the minimum
+					 * and 0xF is the maximum.
+					 * Default is 0xA.
+					 *
+					 * The TX output driver C(-1)
+					 * coefficient is bits 0-4 where
+					 * 0b00000 is the minimum (-4ma) and
+					 * 0b11111 is the maximum (4ma).  The
+					 * default 0x 0b01111.
+					 */
+					txout_driver_ctrl1 = <0x0A0F>;
+
+					/* The TX output driver C(0) coefficient
+					 * is bits 8-12 with 0b00000 being the
+					 * minimum (0mA) and 0b11111 being
+					 * the maximum (16mA). The default is
+					 * 0b10011
+					 *
+					 * The C(+1) coefficient is bits 0-5
+					 * with 0b000000 being the minimum
+					 * (-0.25mA) and 0b111111 being the
+					 * maximum (-16mA).  The default is
+					 * 0b000000.
+					 */
+					/*txout_driver_ctrl2 = <0x1300>;*/
+
+					/* DC_AGC_LOS_CONFIG1:
+					 *   15: Suppress_Coarse_Adj_on_LOS_Clear
+					 *	0: DC offset correction performed using coarse
+					 *	   resolution mode (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   mode when correction resumes after LOPC/LOS alarms
+					 *	   clear.  This guarantees there will be no big jumps in
+					 *	   the offset at the expense of taking longer to reach
+					 *	   optimal setting.
+					 *   14: Force_DC2_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   13: Force_DC1_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   12: Force_DC0_Fine_Adj:
+					 *	Forces the DC offset correction to operate in fine
+					 *	resolution adjustment mode at times when the algorithm.
+					 *	0: DC offset correction makes coarse adjustments when
+					 *	   correction mode is first enabled (default)
+					 *	1: DC offset correction performed using fine resolution
+					 *	   at all times.  This is slower.
+					 *   10: Skip_DC2_Adj, 1 = skip DC2 offset correction
+					 *   9:  Skip_DC1_Adj, 1 = skip DC1 offset correction
+					 *   8:  Skip_DC0_Adj, 1 = skip DC0 offset correction
+					 *
+					 *   6-4: DC_Offset_Alarm_Mode (default 1)
+					 *	Selects the alarm condition that will halt the DC offset
+					 *	correction logic when the alarm(s) are set.
+					 *	111: reserved
+					 *	110: reserved
+					 *	101: LOPC and software LOS detection
+					 *	100: LOPC and hardware LOS detection
+					 *	011: Software LOS detection
+					 *	010: Hardware LOS detection
+					 *	001: LOPC
+					 *	000: Never.  DC offset correction will continue to make
+					 *	     fine resolution adjustments to the offsets even
+					 *	     when LOPC and LOS alarms are present.
+					 *
+					 *  3: AGC_Enable
+					 *	Selects when hardware AGC adjustment logic and LOS
+					 *	detection logic is enabled (default 1)
+					 *	0: disabled
+					 *	1: enabled
+					 *  2: AGC_Suspend
+					 *	Suspends the LOS detection logic and AGC logic
+					 *	from making adjustments to the gain.  Bit valid only
+					 *	if AGC_Enable=1
+					 *	0: AGC adjustment enabled (default)
+					 *	1: AGC adjustment suspended
+					 *  1: DC_Offset_Adj_Enable
+					 *	Select when the hardware DC offset correction logic is
+					 *	enabled.
+					 *	0: disable
+					 *	1: enable (default)
+					 *  0: DC_Offset_Adj_Suspend
+					 *	Suspends the DC offset correction logic from making
+					 *	adjustments to all offset settings.  Bit valid only if
+					 *	DC_Offset_Adj_Enable=1
+					 *	0: DC offset correction enabled (default)
+					 *	1: DC offset correction suspended
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_dc_agc_los_config1 = <0x000A>;
+
+					/* Disable aggressive track phase during
+					 * firmware convergence if 0, enabled
+					 * otherwise (default).
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_agg_track_phase = <0>;
+
+					/* AGC_Config4
+					 *
+					 * 13-8: Ampl_Tolerance
+					 *	This defines the hysterisis
+					 *	built in to the AGC adjustment
+					 *	circuit.  The VGA gain will not
+					 *	be adjusted as long as the
+					 *	measured input amplitude is
+					 *	Inp_Ampl_Target +/- Amnpl_Tolerance.
+					 *	 Default is 4.
+					 * 7-0: Inp_Ampl_Target
+					 *	This is the target amplitude
+					 *	desired to be measured at the
+					 *	peak detector when measuring
+					 *	input amplitude.  The VGA gain
+					 *	is adjusted to achieve this
+					 *	target setting.
+					 *	Default is 0x6E.
+					 *
+					 * This setting is only applied for
+					 * passive copper.
+					 */
+					vitesse,copper_agc_config4 = <0x0496>;
+
+					/* The Vitesse 10G PHY does not
+					 * automatically read the SFP EEPROM
+					 * so the host needs to do it to put
+					 * the PHY in the proper mode for
+					 * copper or optical.
+					 */
+					sfp-eeprom = <&sfp1>;
+				};
+			};
+			mphyB: ethernet-phy-nexus@B {
+				reg = <0>;
+				/* The TI TLK10232 is a dual-PHY where
+				 * some of the configuration is common across
+				 * both of the phy devices such as the reset
+				 * line and the base MDIO address.
+				 */
+				compatible = "ti,tlk10232-nexus", "ethernet-phy-nexus";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ranges;
+				cavium,phy-trim = "0,ti";
+
+				/* Hardware reset signal open-drain active low on GPIO 17, must not be driven high. */
+				reset = <&gpio 17 2>;
+
+				phy11: ethernet-phy@0 {
+					/* Absolute address */
+					reg = <0>;
+					compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
+
+					/* The TI 10G PHY does not
+					 * automatically read the SFP EEPROM
+					 * so the host needs to do it to put
+					 * the PHY in the proper mode for
+					 * copper or optical.
+					 */
+					sfp-eeprom = <&sfp0>;
+
+					/* TX fault input signal for PHY from SFP+ */
+					tx-fault	= <&gpio1 4 0>;
+					/* TX disable for PHY to SFP+ */
+					tx-disable	= <&gpio1 5 0>;
+					/* MOD ABS signal for PHY from SFP+ */
+					mod-abs		= <&gpio1 6 0>;
+					/* RX los of singal for PHY from SFP+ */
+					rx-los		= <&gpio1 7 0>;
+				};
+
+				phy10: ethernet-phy@1 {
+					/* Absolute address */
+					reg = <0x1>;
+					compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
+
+					/* The TI 10G PHY does not
+					 * automatically read the SFP EEPROM
+					 * so the host needs to do it to put
+					 * the PHY in the proper mode for
+					 * copper or optical.
+					 */
+					sfp-eeprom = <&sfp1>;
+					/* TX fault input signal for PHY */
+					tx-fault	= <&gpio1 0 0>;
+					/* TX disable for PHY */
+					tx-disable	= <&gpio1 1 0>;
+					/* MOD ABS signal for PHY */
+					mod-abs		= <&gpio1 2 0>;
+					/* RX los of singal for PHY */
+					rx-los		= <&gpio1 3 0>;
+				};
+			};
+		};
+
+		pip: pip@11800a0000000 {
+			compatible = "cavium,octeon-3860-pip";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+			interface@A {
+				compatible = "cavium,octeon-3860-pip-interface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>; /* interface */
+				cavium,phy-trim = "0,vitesse";
+
+				ethernet@0 {
+					compatible = "cavium,octeon-3860-pip-port";
+					reg = <0x0>; /* Port */
+					local-mac-address = [ 00 00 00 00 00 00 ];
+					phy-handle = <&phy0>;
+				};
+			};
+			interface@B {
+				compatible = "cavium,octeon-3860-pip-interface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>; /* interface */
+				cavium,phy-trim = "0,vitesse";
+
+				ethernet@0 {
+					compatible = "cavium,octeon-3860-pip-port";
+					reg = <0x0>; /* Port */
+					local-mac-address = [ 00 00 00 00 00 00 ];
+					phy-handle = <&phy1>;
+				};
+			};
+			interface@C {
+				compatible = "cavium,octeon-3860-pip-interface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>; /* interface */
+				cavium,phy-trim = "0,ti";
+
+				ethernet@0 {
+					compatible = "cavium,octeon-3860-pip-port";
+					reg = <0x0>; /* Port */
+					local-mac-address = [ 00 00 00 00 00 00 ];
+					phy-handle = <&phy10>;
+				};
+			};
+			interface@D {
+				compatible = "cavium,octeon-3860-pip-interface";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <1>; /* interface */
+				cavium,phy-trim = "0,ti";
+
+				ethernet@0 {
+					compatible = "cavium,octeon-3860-pip-port";
+					reg = <0x0>; /* Port */
+					local-mac-address = [ 00 00 00 00 00 00 ];
+					phy-handle = <&phy11>;
+				};
+			};
+		};
+
+		uart0: serial@1180000000800 {
+			compatible = "cavium,octeon-3860-uart","ns16550";
+			reg = <0x11800 0x00000800 0x0 0x400>;
+			clock-frequency = <400000000>;
+			current-speed = <115200>;
+			reg-shift = <3>;
+			interrupts = <0 34>;
+		};
+
+		uart1: serial@1180000000c00 {
+			compatible = "cavium,octeon-3860-uart","ns16550";
+			reg = <0x11800 0x00000c00 0x0 0x400>;
+			clock-frequency = <400000000>;
+			current-speed = <115200>;
+			reg-shift = <3>;
+			interrupts = <0 35>;
+		};
+
+		bootbus: bootbus@1180000000000 {
+			compatible = "cavium,octeon-3860-bootbus";
+			reg = <0x11800 0x00000000 0x0 0x200>;
+			/* The chip select number and offset */
+			#address-cells = <2>;
+			/* The size of the chip select region */
+			#size-cells = <1>;
+			ranges = <0 0  0       0x1f400000  0xc00000>,
+				 <1 0  0x10000 0x30000000  0>,
+				 <2 0  0       0x1f000000  0x100000>,
+				 <3 0  0x10000 0x50000000  0>,
+				 <4 0  0x10000 0x60000000  0>,
+				 <5 0  0x10000 0x70000000  0>,
+				 <6 0  0x10000 0x80000000  0>,
+				 <7 0  0x10000 0x90000000  0>;
+
+			cavium,cs-config@0 {
+				compatible = "cavium,octeon-3860-bootbus-config";
+				cavium,cs-index = <0>;
+				cavium,t-adr  = <10>;
+				cavium,t-ce   = <50>;
+				cavium,t-oe   = <50>;
+				cavium,t-we   = <35>;
+				cavium,t-rd-hld = <25>;
+				cavium,t-wr-hld = <35>;
+				cavium,t-pause  = <0>;
+				cavium,t-wait   = <300>;
+				cavium,t-page   = <25>;
+				cavium,t-rd-dly = <0>;
+
+				cavium,pages     = <0>;
+				cavium,bus-width = <8>;
+			};
+			cavium,cs-config@2 {
+				compatible = "cavium,octeon-3860-bootbus-config";
+				cavium,cs-index = <2>;
+				cavium,t-adr  = <0>;
+				cavium,t-ce   = <50>;
+				cavium,t-oe   = <20>;
+				cavium,t-we   = <46>;
+				cavium,t-rd-hld = <8>;
+				cavium,t-wr-hld = <10>;
+				cavium,t-pause  = <0>;
+				cavium,t-wait   = <0>;
+				cavium,t-page   = <1>;
+				cavium,t-ale	= <1>;
+				cavium,t-rd-dly = <0>;
+
+				cavium,pages     = <0>;
+				cavium,bus-width = <8>;
+			};
+			flash0: nor@0,0 {
+				compatible = "cfi-flash";
+				reg = <0 0 0x800000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				partition@0 {
+					label = "bootloader";
+					reg = <0x0 0x1c0000>;
+					read-only;
+				};
+				partition@1c0000 {
+					label = "kernel";
+					reg = <0x1c0000 0x63e000>;
+				};
+				partition@7fe000 {
+					label = "environment";
+					reg = <0x7fe0000 0x2000>;
+					read-only;
+				};
+			};
+			psram0: psram@2,0 {
+				compatible = "micron,mt45w1mw16pd";
+				reg = <2 0x20 0x20>, <2 0 0x20>;
+			};
+		};
+
+		dma0: dma-engine@1180000000100 {
+			compatible = "cavium,octeon-5750-bootbus-dma";
+			reg = <0x11800 0x00000100 0x0 0x8>;
+			interrupts = <0 63>;
+		};
+		dma1: dma-engine@1180000000108 {
+			compatible = "cavium,octeon-5750-bootbus-dma";
+			reg = <0x11800 0x00000108 0x0 0x8>;
+			interrupts = <0 63>;
+		};
+		nand-flash-interface@1070001000000 {
+			compatible = "cavium,octeon-5230-nand";
+			reg = <0x10700 0x1000000 0x0 0x100 0x11800 0x168 0x0 0x20>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			interrupts = <0x0 0x3f>;
+			flash@1 {
+				compatible = "nand-flash";
+				reg = <0x1>;
+				nand-ecc-mode = "soft";
+				nand-ecc-size = <0x200>;
+				nand-ecc-bytes = <0x7>;
+				nand-bus-width = <0x8>;
+			};
+		};
+	};
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		d1a {
+			label = "bottom";
+			gpios = <&gpio 1 0>;
+			default-state = "keep";
+			cavium,phy-trim = "0,ti";
+		};
+		d1b-t {
+			label = "top";
+			gpios = <&gpio 2 0>;
+			default-state = "keep";
+			cavium,phy-trim = "0,ti";
+		};
+		d1b-v {
+			label = "top";
+			gpios = <&gpio 2 0>;
+			default-state = "keep";
+			cavium,phy-trim = "0,vitesse";
+		};
+	};
+
+	aliases {
+		pip = &pip;
+		smi0 = &smi0;
+		twsi0 = &twsi0;
+		twsi1 = &twsi1;
+		uart0 = &uart0;
+		uart1 = &uart1;
+		flash0 = &flash0;
+	};
+ };

target/linux/octeon/image/Makefile

@@ -65,6 +65,16 @@ define Device/ubnt_edgerouter-4
 endef
 TARGET_DEVICES += ubnt_edgerouter-4
 
+define Device/snic10e
+  DEVICE_VENDOR := Cavium
+  DEVICE_MODEL := snic10e
+  DEVICE_DTS := snic10e
+  DEVICE_PACKAGES += kmod-gpio-button-hotplug kmod-leds-gpio kmod-of-mdio kmod-sfp kmod-usb3 kmod-usb-storage-uas
+  KERNEL := kernel-bin | append-dtb-to-elf
+  KERNEL_DEPENDS := $$(wildcard $(DTS_DIR)/$(DEVICE_DTS).dts)
+endef
+
+TARGET_DEVICES += snic10e
 ERLITE_CMDLINE:=-mtdparts=phys_mapped_flash:512k(boot0)ro,512k(boot1)ro,64k(eeprom)ro root=/dev/sda2 rootfstype=squashfs,ext4 rootwait
 define Device/ubnt_edgerouter-lite
   DEVICE_VENDOR := Ubiquiti

target/linux/octeon/patches-5.4/141-octeon_snic10e_support.patch

@@ -0,0 +1,18 @@
+--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
++++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+@@ -253,6 +253,7 @@ enum cvmx_board_types_enum {
+ 	CVMX_BOARD_TYPE_REDWING = 43,
+ 	CVMX_BOARD_TYPE_NIC68_4 = 44,
+ 	CVMX_BOARD_TYPE_NIC10E_66 = 45,
++	CVMX_BOARD_TYPE_SNIC10E = 50,
+ 	CVMX_BOARD_TYPE_MAX,
+ 
+ 	/*
+@@ -366,6 +367,7 @@ static inline const char *cvmx_board_type_to_string(enum
+ 		ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
+ 		ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
+ 		ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
++		ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SNIC10E)
+ 		ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
+ 
+ 			/* Customer boards listed here */

target/linux/octeon/patches-5.4/703-debug-it-all.patch

@@ -0,0 +1,79 @@
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
+@@ -1041,12 +1041,14 @@ int cvmx_helper_initialize_packet_io_global(void)
+ 		result |= __cvmx_helper_interface_setup_ipd(interface);
+ 		result |= __cvmx_helper_interface_setup_pko(interface);
+ 	}
+-
++	cvmx_dprintf("Gets past end of interfaces setup\n");
+ 	result |= __cvmx_helper_global_setup_ipd();
+ 	result |= __cvmx_helper_global_setup_pko();
+ 
++	cvmx_dprintf("Sets up global helpers\n");
+ 	/* Enable any flow control and backpressure */
+ 	result |= __cvmx_helper_global_setup_backpressure();
++	cvmx_dprintf("Sets up backpressure helpers\n");
+ 
+ #if CVMX_HELPER_ENABLE_IPD
+ 	result |= cvmx_helper_ipd_and_packet_input_enable();
+--- a/drivers/staging/octeon/ethernet.c
++++ b/drivers/staging/octeon/ethernet.c
+@@ -700,6 +700,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 	cvm_oct_configure_common_hw();
+ 
+ 	cvmx_helper_initialize_packet_io_global();
++	pr_err("OK, we got out of packet_io_global()\n");
+ 
+ 	if (receive_group_order) {
+ 		if (receive_group_order > 4)
+@@ -709,9 +710,11 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 		pow_receive_groups = BIT(pow_receive_group);
+ 	}
+ 
++	pr_err("We got through receive_group_order\n");
+ 	/* Change the input group for all ports before input is enabled */
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
++		pr_err("We are starting on interface %d\n", interface);
+ 		int num_ports = cvmx_helper_ports_on_interface(interface);
+ 		int port;
+ 
+@@ -752,14 +755,14 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 				pip_prt_tagx.s.grptag	= 0;
+ 				pip_prt_tagx.s.grp	= pow_receive_group;
+ 			}
+-
++			pr_err("COULD IT BE CSR WRITES???\n");
+ 			cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
+ 				       pip_prt_tagx.u64);
+ 		}
+ 	}
+-
++	pr_err("COULD it be cvmx_helper_ipd_and_packet_input_enable???\n");
+ 	cvmx_helper_ipd_and_packet_input_enable();
+-
++	pr_err("COULD it be this memset??\n");
+ 	memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
+ 
+ 	/*
+@@ -804,6 +807,7 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	pr_err("OK, we got THIS far, all the way to the interface init. Which is weird, we shoulda crashed by now\n");
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
+ 		cvmx_helper_interface_mode_t imode =
+@@ -860,8 +864,10 @@ static int cvm_oct_probe(struct platform_device *pdev)
+ 				break;
+ 
+ 			case CVMX_HELPER_INTERFACE_MODE_XAUI:
+-				dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
+-				strscpy(dev->name, "xaui%d", sizeof(dev->name));
++				if (of_device_is_available(priv->of_node)) {
++					dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
++					strscpy(dev->name, "xaui%d", sizeof(dev->name));
++				}
+ 				break;
+ 
+ 			case CVMX_HELPER_INTERFACE_MODE_LOOP:

target/linux/octeon/patches-5.4/704-more-debugs.patch

@@ -0,0 +1,48 @@
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
+@@ -971,6 +971,7 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
+ 	int interface;
+ 
+ 	/* Enable IPD */
++    cvmx_dprintf("COULD IT BE cvmx_ipd_enable???\n");
+ 	cvmx_ipd_enable();
+ 
+ 	/*
+@@ -978,13 +979,16 @@ int cvmx_helper_ipd_and_packet_input_enable(void)
+ 	 * that at this point IPD/PIP must be fully functional and PKO
+ 	 * must be disabled
+ 	 */
++    cvmx_dprintf("COULD IT BE getting no of interfaces????\n");
+ 	num_interfaces = cvmx_helper_get_number_of_interfaces();
+ 	for (interface = 0; interface < num_interfaces; interface++) {
++      cvmx_dprintf("COULD IT BE interface # %d ??ces????\n", interface);
+ 		if (cvmx_helper_ports_on_interface(interface) > 0)
+ 			__cvmx_helper_packet_hardware_enable(interface);
+ 	}
+ 
+ 	/* Finally enable PKO now that the entire path is up and running */
++    cvmx_dprintf("COULD IT BE PKO???\n");
+ 	cvmx_pko_enable();
+ 
+ 	if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1)
+--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
++++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
+@@ -129,15 +129,18 @@ static inline void cvmx_ipd_config(uint64_t mbuff_size,
+ static inline void cvmx_ipd_enable(void)
+ {
+ 	union cvmx_ipd_ctl_status ipd_reg;
++	cvmx_dprintf("COULD IT BE THIS ONE CSR READ IN cvmx_ipd_enable ??\n");
+ 	ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+ 	if (ipd_reg.s.ipd_en) {
+ 		cvmx_dprintf
+ 		    ("Warning: Enabling IPD when IPD already enabled.\n");
+ 	}
++    cvmx_dprintf("OK IT PASSED THE READ. BUT THERE'S THIS CVMX_ENABLE_LEN_M8_FIX THAT COULD APPLY??\n");
+ 	ipd_reg.s.ipd_en = 1;
+ #if  CVMX_ENABLE_LEN_M8_FIX
+ 	if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+ 		ipd_reg.s.len_m8 = TRUE;
+ #endif
++    cvmx_dprintf("COULD IT BE THIS ONE CSR WRITE??? IN cvmx_ipd_enable ??\n");
+ 	cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+ }

target/linux/octeon/patches-5.4/705-last-debugs.patch

@@ -0,0 +1,186 @@
+diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+index 93a498d05184..27733d710355 100644
+--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
++++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+@@ -121,58 +121,80 @@ int __cvmx_helper_xaui_enable(int interface)
+ 	union cvmx_gmxx_tx_int_en gmx_tx_int_en;
+ 	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
+ 
++    cvmx_dprintf("COULD IT BE THE FEATURE CHECK FOR PKND??\n");
+ 	/* Setup PKND */
+ 	if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
++      cvmx_dprintf("COULD IT BE THE FIRST CSR READ??\n");
+ 		gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
++        cvmx_dprintf("COULD IT BE THE second CSR READ??\n");
+ 		gmx_cfg.s.pknd = cvmx_helper_get_ipd_port(interface, 0);
++        cvmx_dprintf("COULD IT BE THE third CSR /write READ??\n");
+ 		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 	}
+ 
+ 	/* (1) Interface has already been enabled. */
+ 
+ 	/* (2) Disable GMX. */
++    cvmx_dprintf("step2 start!?? could it be the csr read??\n");
+ 	xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
+ 	xauiMiscCtl.s.gmxeno = 1;
++    cvmx_dprintf("step2 could it be the csr write to disable gmx??\n");
+ 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+ 
+ 	/* (3) Disable GMX and PCSX interrupts. */
++    cvmx_dprintf("step3 start. could it be the csr read??\n");
+ 	gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
++    cvmx_dprintf("step3 start. could it be the write for disabling interrupts???\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
++    cvmx_dprintf("step3 start. could it be read for setting up the gmx_tx_int_en???\n");
+ 	gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
++    cvmx_dprintf("step3 start. could it be the cvmx_gmxx write???\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
++    cvmx_dprintf("step3 start almost done. show up tell us about the PCSXX write???\n");
+ 	pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
++    cvmx_dprintf("step3, this final csr write?\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+ 
+ 	/* (4) Bring up the PCSX and GMX reconciliation layer. */
+ 	/* (4)a Set polarity and lane swapping. */
+ 	/* (4)b */
++    cvmx_dprintf("4.1\n");
+ 	gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+ 	/* Enable better IFG packing and improves performance */
+ 	gmxXauiTxCtl.s.dic_en = 1;
+ 	gmxXauiTxCtl.s.uni_en = 0;
++    cvmx_dprintf("4.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
+ 
+ 	/* (4)c Aply reset sequence */
++    cvmx_dprintf("4.3\n");
+ 	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
+ 	xauiCtl.s.lo_pwr = 0;
+ 
+ 	/* Issuing a reset here seems to hang some CN68XX chips. */
+ 	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
+-	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
++	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X) &&
++        0)
+ 		xauiCtl.s.reset = 1;
+ 
++    cvmx_dprintf("4.4\n");
+ 	cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
+ 
++    cvmx_dprintf("4.5\n");
+ 	/* Wait for PCS to come out of reset */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
+ 	     reset, ==, 0, 10000))
+ 		return -1;
++
++    cvmx_dprintf("4.6\n");
+ 	/* Wait for PCS to be aligned */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_10GBX_STATUS_REG(interface),
+ 	     union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
+ 		return -1;
++
++    cvmx_dprintf("4.7\n");
+ 	/* Wait for RX to be ready */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
+@@ -180,8 +202,11 @@ int __cvmx_helper_xaui_enable(int interface)
+ 		return -1;
+ 
+ 	/* (6) Configure GMX */
++    cvmx_dprintf("6.1\n");
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
++
+ 	gmx_cfg.s.en = 0;
++    cvmx_dprintf("6.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
+ 	/* Wait for GMX RX to be idle */
+@@ -189,62 +214,87 @@ int __cvmx_helper_xaui_enable(int interface)
+ 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+ 		    rx_idle, ==, 1, 10000))
+ 		return -1;
++    cvmx_dprintf("6.3\n");
+ 	/* Wait for GMX TX to be idle */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+ 		    tx_idle, ==, 1, 10000))
+ 		return -1;
+ 
++    cvmx_dprintf("6.4\n");
+ 	/* GMX configure */
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+ 	gmx_cfg.s.speed = 1;
+ 	gmx_cfg.s.speed_msb = 0;
+ 	gmx_cfg.s.slottime = 1;
++    cvmx_dprintf("6.5\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
++    cvmx_dprintf("6.6\n");
+ 	cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
++    cvmx_dprintf("6.7\n");
+ 	cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
++    cvmx_dprintf("6.8\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
+ 	/* (7) Clear out any error state */
++    cvmx_dprintf("7.1\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
+ 		       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
++    cvmx_dprintf("7.2\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
+ 		       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
++    cvmx_dprintf("7.3\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
+ 		       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
+ 
++    cvmx_dprintf("7.4\n");
+ 	/* Wait for receive link */
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
+ 	     rcv_lnk, ==, 1, 10000))
+ 		return -1;
++    cvmx_dprintf("7.5\n");
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+ 	     xmtflt, ==, 0, 10000))
+ 		return -1;
++    cvmx_dprintf("7.6\n");
+ 	if (CVMX_WAIT_FOR_FIELD64
+ 	    (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+ 	     rcvflt, ==, 0, 10000))
+ 		return -1;
+ 
++    cvmx_dprintf("7.7\n");
+ 	cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
++    cvmx_dprintf("7.8\n");
+ 	cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
++    cvmx_dprintf("7.9\n");
+ 	cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
+ 
+ 	/* (8) Enable packet reception */
+ 	xauiMiscCtl.s.gmxeno = 0;
++    cvmx_dprintf("8.1\n");
+ 	cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+ 
++    cvmx_dprintf("8.2\n");
+ 	gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+ 	gmx_cfg.s.en = 1;
++    cvmx_dprintf("8.3\n");
+ 	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+ 
++    cvmx_dprintf("8.4\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
++    cvmx_dprintf("8.5\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
++    cvmx_dprintf("8.6\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
++    cvmx_dprintf("8.7\n");
+ 	__cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
++    cvmx_dprintf("8.8\n");
+ 	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
++    cvmx_dprintf("8.9\n");
+ 	__cvmx_interrupt_gmxx_enable(interface);
++    cvmx_dprintf("8.10\n");
+ 
+ 	return 0;
+ }