include: always set macro-prefix-map for reproducibility

The current implementation either adds macro-prefix-map XOR file-prefix-map (if REPRODUCIBLE_DEBUG_INFO is defined). Let's have the former always active to improve the reproducibility. Signed-off-by: Paul Spooren <mail@aparcar.org>
2026-06-12 09:57:26 -04:00 · 2025-08-22 09:52:59 +02:00
2411 changed files with 61381 additions and 155313 deletions
--- a/.github/labeler.yml
+++ b/.github/labeler.yml
@@ -54,10 +54,6 @@
    - "target/linux/d1/**"
    - "package/boot/uboot-d1/**"
    - "package/boot/opensbi/**"
-"target/econet":
- changed-files:
-  - any-glob-to-any-file:
-    - "target/linux/econet/**"
 "target/gemini":
 - changed-files:
  - any-glob-to-any-file:
--- a/config/Config-build.in
+++ b/config/Config-build.in
@@ -358,11 +358,9 @@ menu "Global build settings"
 		config PKG_FORTIFY_SOURCE_NONE
 			bool "None"
 		config PKG_FORTIFY_SOURCE_1
-			bool "Conservative Level 1"
+			bool "Conservative"
 		config PKG_FORTIFY_SOURCE_2
-			bool "Aggressive Level 2"
-		config PKG_FORTIFY_SOURCE_3
-			bool "Aggressive Level 3"
+			bool "Aggressive"
 	endchoice

 	choice
@@ -383,15 +381,6 @@ menu "Global build settings"
 			bool "Full"
 	endchoice

-	config PKG_DT_RELR
-		bool "Link with relative relocations (RELR)"
-		depends on (aarch64 || i386 || loongarch64 || x86_64)
-		default y
-		help
-		  Link all applications with -Wl,-z,pack-relative-relocs.
-		  This will reduce the size of many applications.
-		  This is only supported on a limited number of architectures.
-
 	config TARGET_ROOTFS_SECURITY_LABELS
 		bool
 		select KERNEL_SQUASHFS_XATTR
--- a/include/cmake.mk
+++ b/include/cmake.mk
@@ -113,7 +113,7 @@ define Build/Configure/Default
 			-DCMAKE_NM="$(CMAKE_NM)" \
 			-DCMAKE_RANLIB="$(CMAKE_RANLIB)" \
 			-DCMAKE_FIND_ROOT_PATH="$(CMAKE_FIND_ROOT_PATH)" \
-			-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \
+			-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=BOTH \
 			-DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \
 			-DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=ONLY \
 			-DCMAKE_STRIP=: \
--- a/include/download.mk
+++ b/include/download.mk
@@ -159,7 +159,7 @@ $(if $(if $(MIRROR), \
 		( $(3) ) \
 		$(if $(filter-out x,$(MIRROR_HASH)), && ( \
 			file_hash="$$$$($(MKHASH) sha256 "$(DL_DIR)/$(FILE)")"; \
-			[ "$$$$file_hash" = "$(MIRROR_HASH)" ] || [ "$(MIRROR_HASH)" = "skip" ] || { \
+			[ "$$$$file_hash" = "$(MIRROR_HASH)" ] || { \
 				echo "Hash mismatch for file $(FILE): expected $(MIRROR_HASH), got $$$$file_hash"; \
 				false; \
 			}; \
@@ -238,7 +238,7 @@ define DownloadMethod/rawgit
 	[ \! -d $(SUBDIR) ] && \
 	git clone $(OPTS) $(URL) $(SUBDIR) && \
 	(cd $(SUBDIR) && git checkout $(SOURCE_VERSION)) && \
-	export TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --no-show-signature --format='@%ct'` && \
+	export TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --format='@%ct'` && \
 	echo "Generating formal git archive (apply .gitattributes rules)" && \
 	(cd $(SUBDIR) && git config core.abbrev 8 && \
 	git archive --format=tar HEAD --output=../$(SUBDIR).tar.git) && \
--- a/include/hardening.mk
+++ b/include/hardening.mk
@@ -8,7 +8,6 @@ PKG_ASLR_PIE_REGULAR ?= 0
 PKG_SSP ?= 1
 PKG_FORTIFY_SOURCE ?= 1
 PKG_RELRO ?= 1
-PKG_DT_RELR ?= 1

 ifdef CONFIG_PKG_CHECK_FORMAT_SECURITY
  ifeq ($(strip $(PKG_CHECK_FORMAT_SECURITY)),1)
@@ -52,11 +51,6 @@ ifdef CONFIG_PKG_FORTIFY_SOURCE_2
    TARGET_CFLAGS += -D_FORTIFY_SOURCE=2
  endif
 endif
-ifdef CONFIG_PKG_FORTIFY_SOURCE_3
-  ifeq ($(strip $(PKG_FORTIFY_SOURCE)),1)
-    TARGET_CFLAGS += -D_FORTIFY_SOURCE=3
-  endif
-endif
 ifdef CONFIG_PKG_RELRO_PARTIAL
  ifeq ($(strip $(PKG_RELRO)),1)
    TARGET_CFLAGS += -Wl,-z,relro
@@ -70,10 +64,3 @@ ifdef CONFIG_PKG_RELRO_FULL
  endif
 endif

-ifdef CONFIG_PKG_DT_RELR
-  ifeq ($(strip $(PKG_DT_RELR)),1)
-    TARGET_CFLAGS += -Wl,-z,pack-relative-relocs
-    TARGET_LDFLAGS += -zpack-relative-relocs
-  endif
-endif
-
--- a/include/image-commands.mk
+++ b/include/image-commands.mk
@@ -130,33 +130,6 @@ define Build/append-gl-metadata
 	}
 endef

-define Build/append-teltonika-metadata
-	echo \
-		'{$(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
-			"metadata_version": "1.1", \
-			"compat_version": "$(call json_quote,$(compat_version))", \
-			"version":"$(call json_quote,$(VERSION_DIST))-$(call json_quote,$(VERSION_NUMBER))-$(call json_quote,$(REVISION))", \
-			"device_code": [".*"], \
-			"hwver": [".*"], \
-			"batch": [".*"], \
-			"serial": [".*"], \
-			$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
-			$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
-				[$(call metadata_devices,$(SUPPORTED_TELTONIKA_DEVICES))]$(comma) \
-				"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
-			$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_TELTONIKA_DEVICES))]$(comma)) \
-			"version_wrt": { \
-			"dist": "$(call json_quote,$(VERSION_DIST))", \
-			"version": "$(call json_quote,$(VERSION_NUMBER))", \
-			"revision": "$(call json_quote,$(REVISION))", \
-			"target": "$(call json_quote,$(TARGETID))", \
-			"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
-		}, \
-			"hw_support": {}, \
-			"hw_mods": {$(shell i=1; for mod in $(SUPPORTED_TELTONIKA_HW_MODS); do [ $$i -gt 1 ] && echo -n ,; echo -n "\"mod$$i\": \"$$mod\""; i=$$((i+1)); done)} \
-		}' | fwtool -I - $@
-endef
-
 define Build/append-rootfs
 	dd if=$(IMAGE_ROOTFS) >> $@
 endef
@@ -431,10 +404,7 @@ define Build/initrd_compression
 endef

 define Build/fit
-	$(if $(findstring with-rootfs,$(word 3,$(1))), \
-		$(call locked,dd if=$(IMAGE_ROOTFS) of=$(IMAGE_ROOTFS).pagesync bs=4096 conv=sync, \
-		  gen-cpio$(if $(TARGET_PER_DEVICE_ROOTFS),.$(ROOTFS_ID/$(DEVICE_NAME)))))
-	$(TOPDIR)/scripts/mkits.sh \
+	$(call locked,$(TOPDIR)/scripts/mkits.sh \
 		-D $(DEVICE_NAME) -o $@.its -k $@ \
 		-C $(word 1,$(1)) \
 		$(if $(word 2,$(1)),\
@@ -451,10 +421,9 @@ define Build/fit
 		$(if $(DEVICE_DTS_LOADADDR),-s $(DEVICE_DTS_LOADADDR)) \
 		$(if $(DEVICE_DTS_OVERLAY),$(foreach dtso,$(DEVICE_DTS_OVERLAY), -O $(dtso):$(KERNEL_BUILD_DIR)/image-$(dtso).dtbo)) \
 		-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),"config-1") \
-		-A $(LINUX_KARCH) -v $(LINUX_VERSION)
+		-A $(LINUX_KARCH) -v $(LINUX_VERSION), gen-cpio$(if $(TARGET_PER_DEVICE_ROOTFS),.$(ROOTFS_ID/$(DEVICE_NAME))))
 	$(call locked,PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage $(if $(findstring external,$(word 3,$(1))),\
-		-E -B 0x1000 $(if $(findstring static,$(word 3,$(1))),-p 0x1000)) -f $@.its $@.new, \
-	  gen-cpio$(if $(TARGET_PER_DEVICE_ROOTFS),.$(ROOTFS_ID/$(DEVICE_NAME))))
+		-E -B 0x1000 $(if $(findstring static,$(word 3,$(1))),-p 0x1000)) -f $@.its $@.new)
 	@mv $@.new $@
 endef

@@ -523,7 +492,7 @@ define Build/yaffs-filesystem
 		filesystem_size="filesystem_blocks * 64 * 1024" \
 		filesystem_size_with_reserve="(filesystem_blocks + 2) * 64 * 1024"; \
 		head -c $$filesystem_size_with_reserve /dev/zero | tr "\000" "\377" > $@.img \
-		&& yafut -d $@.img -w -i $@ -o $(if $(findstring v7,$@),bootimage,kernel) -C 1040 -B 64k -E -P -S $(1) \
+		&& yafut -d $@.img -w -i $@ -o kernel -C 1040 -B 64k -E -P -S $(1) \
 		&& truncate -s $$filesystem_size $@.img \
 		&& mv $@.img $@
 endef
@@ -561,11 +530,6 @@ define Build/gl-qsdk-factory
 		$(KDIR_TMP)/$(notdir $(BOOT_SCRIPT))
 endef

-define Build/kernel-pack-npk
-	$(STAGING_DIR_HOST)/bin/npk_pack_kernel $@ $@.npk
-	mv $@.npk $@
-endef
-
 define Build/linksys-image
 	let \
 		size="$$(stat -c%s $@)" \
@@ -644,19 +608,6 @@ define Build/openmesh-image
 		"$(call param_get_default,rootfs,$(1),$@)" "rootfs"
 endef

-define Build/dualboot-datachk-nand-image
-	$(TOPDIR)/scripts/nand-fwupgradecfg-gen.sh \
-		"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" \
-		"$@-fwupgrade.cfg" \
-		"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" \
-		"$(call param_get_default,rootfs,$(1),$@)"
-	$(TOPDIR)/scripts/combined-ext-image.sh \
-		"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))" "$@" \
-		"$@-fwupgrade.cfg" "fwupgrade.cfg" \
-		"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))" "kernel" \
-		"$(call param_get_default,rootfs,$(1),$@)" "rootfs"
-endef
-
 define Build/pad-extra
 	dd if=/dev/zero bs=$(1) count=1 >> $@
 endef
--- a/include/image.mk
+++ b/include/image.mk
@@ -595,6 +595,7 @@ define Device/Check/Common
      _PROFILE_SET :=
    endif
  endif
+  DEVICE_PACKAGES += $$(call extra_packages,$$(DEVICE_PACKAGES))
  ifdef TARGET_PER_DEVICE_ROOTFS
    $$(eval $$(call merge_packages,_PACKAGES,$$(DEVICE_PACKAGES) $$(call DEVICE_EXTRA_PACKAGES,$(1))))
    ROOTFS_ID/$(1) := $$(if $$(_PROFILE_SET),$$(call mkfs_packages_id,$$(_PACKAGES)))
--- a/include/openssl-module.mk
+++ b/include/openssl-module.mk
@@ -3,7 +3,6 @@
 # Copyright (C) 2022-2023 Enéas Ulir de Queiroz

 ENGINES_DIR=engines-3
-MODULES_DIR=ossl-modules

 define Package/openssl/module/Default
  SECTION:=libs
@@ -75,6 +74,6 @@ endef
 # 1 = provider name
 # 2 = [ package name, defaults to libopenssl-$(1) ]
 define Package/openssl/add-provider
-  $(call Package/openssl/add-module,provider,$(1),/usr/lib/$(MODULES_DIR),$(2))
+  $(call Package/openssl/add-module,provider,$(1),/usr/lib/ossl-modules,$(2))
 endef

--- a/include/package-defaults.mk
+++ b/include/package-defaults.mk
@@ -20,7 +20,7 @@ define Package/Default
  PROVIDES:=
  EXTRA_DEPENDS:=
  MAINTAINER:=$(PKG_MAINTAINER)
-  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(if $(__pkg_source_makefile),$(__pkg_source_makefile),$(CURDIR)))
+  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(patsubst $(TOPDIR)/package/%,feeds/base/%,$(CURDIR)))
  ifneq ($(PKG_VERSION),)
    ifneq ($(PKG_RELEASE),)
      VERSION:=$(PKG_VERSION)-r$(PKG_RELEASE)
--- a/include/package-pack.mk
+++ b/include/package-pack.mk
@@ -232,7 +232,6 @@ $(_endef)
    $$(PACK_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
    $$(PACK_$(1)) : export PATH=$$(TARGET_PATH_PKG)
    $$(PACK_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
-    $$(PACK_$(1)) : export SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
    $(PKG_INFO_DIR)/$(1).provides $$(PACK_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-pack.mk
 	rm -rf $$(IDIR_$(1))
 ifeq ($$(CONFIG_USE_APK),)
@@ -354,7 +353,7 @@ else

 	if [ -n "$(USERID)" ]; then echo $(USERID) > $$(IDIR_$(1))/lib/apk/packages/$(1).rusers; fi;
 	if [ -n "$(ALTERNATIVES)" ]; then echo $(ALTERNATIVES) > $$(IDIR_$(1))/lib/apk/packages/$(1).alternatives; fi;
-	(cd $$(IDIR_$(1)) && find . -type f,l -printf "/%P\n" | sort > $(TMP_DIR)/$(1).list && mv $(TMP_DIR)/$(1).list $$(IDIR_$(1))/lib/apk/packages/$(1).list)
+	(cd $$(IDIR_$(1)) && find . -type f,l -printf "/%P\n" | sort > $$(IDIR_$(1))/lib/apk/packages/$(1).list)
 	# Move conffiles to IDIR and build conffiles_static with csums
 	if [ -f $$(ADIR_$(1))/conffiles ]; then \
 		mv -f $$(ADIR_$(1))/conffiles $$(IDIR_$(1))/lib/apk/packages/$(1).conffiles; \
@@ -408,7 +407,8 @@ else
 	  $$(APK_SCRIPTS_$(1)) \
 	  --info "depends:$$(foreach depends,$$(subst $$(comma),$$(space),$$(subst $$(space),,$$(subst $$(paren_right),,$$(subst $$(paren_left),,$$(Package/$(1)/DEPENDS))))),$$(depends))" \
 	  --files "$$(IDIR_$(1))" \
-	  --output "$$(PACK_$(1))"
+	  --output "$$(PACK_$(1))" \
+	  --sign "$(BUILD_KEY_APK_SEC)"
 endif

 	@[ -f $$(PACK_$(1)) ]
--- a/include/package.mk
+++ b/include/package.mk
@@ -134,35 +134,6 @@ endef

 PKG_INSTALL_STAMP:=$(PKG_INFO_DIR)/$(PKG_DIR_NAME).$(if $(BUILD_VARIANT),$(BUILD_VARIANT),default).install

-# Normalize package SOURCE entry to pack reproducible package
-# If we are packing a package with OpenWrt buildroot:
-# - Replace package/... with feeds/base/...
-# If we are packing a package with SDK:
-# - Replace feeds/.*_root/... with feeds/.*/... and remove
-#   the intermediate directory to reflect what the symbolic link
-#   points to.
-#   Example:
-#   Feed link: feeds/base_root/package -> feeds/base
-#   Package: feeds/base_root/package/system/uci -> feeds/base/system/uci
-ifeq ($(DUMP),)
-  __pkg_base_path:=$(patsubst $(TOPDIR)/%,%,$(CURDIR))
-  __pkg_provider_path:=$(word 1,$(subst /, ,$(__pkg_base_path)))
-  ifeq ($(__pkg_provider_path), feeds)
-    __pkg_feed_path:=$(word 2,$(subst /, ,$(__pkg_base_path)))
-    __pkg_feed_name:=$(patsubst %_root,%,$(__pkg_feed_path))
-    ifneq (__pkg_feed_path, __pkg_feed_name)
-      __pkg_feed_realpath:=$(realpath $(TOPDIR)/feeds/$(__pkg_feed_name))
-      __pkg_feed_dir:=$(patsubst $(TOPDIR)/feeds/$(__pkg_feed_path)/%,%,$(__pkg_feed_realpath))
-      __pkg_path:=$(patsubst feeds/$(__pkg_feed_path)/$(__pkg_feed_dir)/%,%,$(__pkg_base_path))
-    else
-      __pkg_path:=$(patsubst feeds/$(__pkg_feed_path)/%,%,$(__pkg_base_path))
-    endif
-    __pkg_source_makefile:=$(TOPDIR)/feeds/$(__pkg_feed_name)/$(__pkg_path)
-  else ifeq ($(__pkg_provider_path), package)
-    __pkg_source_makefile:=$(TOPDIR)/feeds/base/$(patsubst package/%,%,$(__pkg_base_path))
-  endif
-endif
-
 include $(INCLUDE_DIR)/package-defaults.mk
 include $(INCLUDE_DIR)/package-dumpinfo.mk
 include $(INCLUDE_DIR)/package-pack.mk
--- a/include/prereq-build.mk
+++ b/include/prereq-build.mk
@@ -9,11 +9,11 @@ SHELL:=sh
 PKG_NAME:=Build dependency

 $(eval $(call TestHostCommand,true, \
-	Please install 'coreutils', \
+	Please install GNU 'coreutils', \
 	$(TRUE)))

 $(eval $(call TestHostCommand,false, \
-	Please install 'coreutils', \
+	Please install GNU 'coreutils', \
 	$(FALSE); [ $$$$$$$$? = 1 ] && $(TRUE)))

 # Required for the toolchain
@@ -178,16 +178,15 @@ $(eval $(call SetupHostCommand,bzip2,Please install 'bzip2', \
 $(eval $(call SetupHostCommand,wget,Please install GNU 'wget', \
 	wget --version | grep GNU))

-$(eval $(call SetupHostCommand,install,Please install 'install', \
+$(eval $(call SetupHostCommand,install,Please install GNU 'install', \
 	$(TOPDIR)/staging_dir/host/bin/ginstall --version | grep GNU, \
-	install --version | grep 'GNU\|uutils', \
+	install --version | grep GNU, \
 	ginstall --version | grep GNU))

 $(eval $(call SetupHostCommand,perl,Please install Perl 5.x, \
 	perl --version | grep "perl.*v5"))

 $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \
-	python3.13 -V 2>&1 | grep 'Python 3', \
 	python3.12 -V 2>&1 | grep 'Python 3', \
 	python3.11 -V 2>&1 | grep 'Python 3', \
 	python3.10 -V 2>&1 | grep 'Python 3', \
@@ -197,7 +196,6 @@ $(eval $(call SetupHostCommand,python,Please install Python >= 3.7, \
 	python3 -V 2>&1 | grep -E 'Python 3\.([7-9]|[0-9][0-9])\.?'))

 $(eval $(call SetupHostCommand,python3,Please install Python >= 3.7, \
-	python3.13 -V 2>&1 | grep 'Python 3', \
 	python3.12 -V 2>&1 | grep 'Python 3', \
 	python3.11 -V 2>&1 | grep 'Python 3', \
 	python3.10 -V 2>&1 | grep 'Python 3', \
@@ -239,7 +237,7 @@ endif

 $(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c
 	mkdir -p $(dir $@)
-	$(STAGING_DIR_HOST)/bin/gcc -O2 -I$(TOPDIR)/tools/include -o $@ $<
+	$(CC) -O2 -I$(TOPDIR)/tools/include -o $@ $<

 $(STAGING_DIR_HOST)/bin/xxd: $(SCRIPT_DIR)/xxdi.pl
 	$(LN) $< $@
--- a/include/prereq.mk
+++ b/include/prereq.mk
@@ -71,7 +71,7 @@ endef
 # 4: optional link library test (example -lncurses)
 define RequireCHeader
  define Require/$(1)
-    echo 'int main(int argc, char **argv) { $(3); return 0; }' | $(STAGING_DIR_HOST)/bin/gcc -include $(1) -x c -o $(TMP_DIR)/a.out - $(4)
+    echo 'int main(int argc, char **argv) { $(3); return 0; }' | gcc -include $(1) -x c -o $(TMP_DIR)/a.out - $(4)
  endef

  $$(eval $$(call Require,$(1),$(2)))
--- a/include/target.mk
+++ b/include/target.mk
@@ -105,6 +105,13 @@ DEFAULT_PACKAGES += $(DEFAULT_PACKAGES.$(DEVICE_TYPE))
 ##
 filter_packages = $(filter-out -% $(patsubst -%,%,$(filter -%,$(1))),$(1))

+##@
+# @brief Append extra package dependencies.
+#
+# @param 1: Package list.
+##
+extra_packages = $(if $(filter wpad wpad-% nas,$(1)),iwinfo)
+
 define ProfileDefault
  NAME:=
  PRIORITY:=
@@ -121,7 +128,7 @@ define Profile
 	echo "Target-Profile: $(1)"; \
 	$(if $(PRIORITY), echo "Target-Profile-Priority: $(PRIORITY)"; ) \
 	echo "Target-Profile-Name: $(NAME)"; \
-	echo "Target-Profile-Packages: $(PACKAGES)"; \
+	echo "Target-Profile-Packages: $(PACKAGES) $(call extra_packages,$(DEFAULT_PACKAGES) $(PACKAGES))"; \
 	echo "Target-Profile-Description:"; \
 	echo "$$$$$$$$$(call shvar,Profile/$(1)/Description)"; \
 	echo "@@"; \
@@ -379,7 +386,7 @@ define BuildTargets/DumpCurrent
 	 echo "$$$$DESCRIPTION"; \
 	 echo '@@'; \
 	 $(if $(DEFAULT_PROFILE),echo 'Target-Default-Profile: $(DEFAULT_PROFILE)';) \
-	 echo 'Default-Packages: $(DEFAULT_PACKAGES)'; \
+	 echo 'Default-Packages: $(DEFAULT_PACKAGES) $(call extra_packages,$(DEFAULT_PACKAGES))'; \
 	 $(DUMPINFO)
 	$(if $(CUR_SUBTARGET),$(SUBMAKE) -r --no-print-directory -C image -s DUMP=1 SUBTARGET=$(CUR_SUBTARGET))
 	$(if $(SUBTARGET),,@$(foreach SUBTARGET,$(SUBTARGETS),$(SUBMAKE) --no-print-directory -s DUMP=1 SUBTARGET=$(SUBTARGET); ))
--- a/include/toplevel.mk
+++ b/include/toplevel.mk
@@ -78,7 +78,7 @@ _ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p))
 prepare-tmpinfo: FORCE
 	@+$(MAKE) -r -s $(STAGING_DIR_HOST)/.prereq-build $(PREP_MK)
 	mkdir -p tmp/info feeds
-	[ -e $(TOPDIR)/feeds/base ] || ln -sf ../package $(TOPDIR)/feeds/base
+	[ -e $(TOPDIR)/feeds/base ] || ln -sf $(TOPDIR)/package $(TOPDIR)/feeds/base
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="packageinfo" SCAN_DIR="package" SCAN_NAME="package" SCAN_DEPTH=5 SCAN_EXTRA=""
 	$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET="targetinfo" SCAN_DIR="target/linux" SCAN_NAME="target" SCAN_DEPTH=3 SCAN_EXTRA="" SCAN_MAKEOPTS="TARGET_BUILD=1"
 	for type in package target; do \
--- a/package/Makefile
+++ b/package/Makefile
@@ -70,8 +70,7 @@ ifneq ($(CONFIG_USE_APK),)
 	(cd $(PACKAGE_DIR_ALL) && $(STAGING_DIR_HOST)/bin/apk mkndx \
 			--root $(TOPDIR) \
 			--keys-dir $(TOPDIR) \
-			--allow-untrusted \
-			$(if $(CONFIG_SIGNED_PACKAGES),--sign $(BUILD_KEY_APK_SEC),) \
+			--sign $(BUILD_KEY_APK_SEC) \
 			--output packages.adb \
 			*.apk; \
 	)
@@ -101,7 +100,6 @@ ifneq ($(CONFIG_USE_APK),)
 	    $(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg))))
 	$(call apk,$(TARGET_DIR)) add --no-cache --initdb --no-scripts --arch $(ARCH_PACKAGES) \
 		--repositories-file /dev/null --repository file://$(PACKAGE_DIR_ALL)/packages.adb \
-		$(if $(CONFIG_SIGNED_PACKAGES),,--allow-untrusted) \
 		$$(cat $(TMP_DIR)/apk_install_list) \
 			"base-files=$(shell cat $(TMP_DIR)/base-files.version)" \
 			"libc=$(shell cat $(TMP_DIR)/libc.version)" \
@@ -135,8 +133,7 @@ ifneq ($(CONFIG_USE_APK),)
 		$(STAGING_DIR_HOST)/bin/apk mkndx \
 			--root $(TOPDIR) \
 			--keys-dir $(TOPDIR) \
-			--allow-untrusted \
-			$(if $(CONFIG_SIGNED_PACKAGES),--sign $(BUILD_KEY_APK_SEC),) \
+			--sign $(BUILD_KEY_APK_SEC) \
 			--output packages.adb \
 			*.apk; \
 		$(STAGING_DIR_HOST)/bin/apk adbdump --format json packages.adb | \
@@ -172,7 +169,6 @@ ifdef CONFIG_JSON_CYCLONEDX_SBOM
 	); done
 endif
 endif
-	$(call sha256sums,$(OUTPUT_DIR)/packages/$(ARCH_PACKAGES),1)

 $(curdir)/flags-install:= -j1

--- a/package/base-files/files/bin/config_generate
+++ b/package/base-files/files/bin/config_generate
@@ -44,15 +44,14 @@ generate_static_network() {
 		set network.loopback.device='lo'
 		set network.loopback.proto='static'
 		add_list network.loopback.ipaddr='127.0.0.1/8'
-		delete network.globals
-		set network.globals='globals'
-		set network.globals.dhcp_default_duid='auto'
 	EOF
-	[ -e /proc/sys/net/ipv6 ] && {
-		uci -q batch <<-EOF
-			set network.globals.ula_prefix='auto'
-		EOF
-	}
+		[ -e /proc/sys/net/ipv6 ] && {
+			uci -q batch <<-EOF
+				delete network.globals
+				set network.globals='globals'
+				set network.globals.ula_prefix='auto'
+			EOF
+		}

 	if json_is_a dsl object; then
 		json_select dsl
--- a/package/base-files/files/etc/init.d/boot
+++ b/package/base-files/files/etc/init.d/boot
@@ -10,13 +10,10 @@ uci_apply_defaults() {
 	cd /etc/uci-defaults || return 0
 	files="$(ls)"
 	[ -z "$files" ] && return 0
-	applied=""
 	for file in $files; do
-		( . "./$(basename $file)" ) && applied="$applied $file"
+		( . "./$(basename $file)" ) && rm -f "$file"
 	done
 	uci commit
-	sync
-	rm -f $applied
 }

 boot() {
--- a/package/base-files/files/etc/uci-defaults/14_network-generate-clientid
+++ b/package/base-files/files/etc/uci-defaults/14_network-generate-clientid
@@ -1,9 +0,0 @@
-[ "$(uci -q get network.globals.dhcp_default_duid)" != "auto" ] && exit 0
-
-uci -q batch <<-EOF >/dev/null
-	# DUID-UUID - RFC6355
-	set network.globals.dhcp_default_duid="$(printf '%s%s' '0004' $(cat /proc/sys/kernel/random/uuid | sed -e 's/-//g'))"
-	commit network
-EOF
-
-exit 0
--- a/package/base-files/files/lib/functions/uci-defaults.sh
+++ b/package/base-files/files/lib/functions/uci-defaults.sh
@@ -771,27 +771,6 @@ ucidef_add_wlan() {
 	ucidef_wlan_idx="$((ucidef_wlan_idx + 1))"
 }

-ucidef_set_interface_netdev_range() {
-	local interface="$1"
-	local base_netdev="$2"
-	local start="$3"
-	local stop="$4"
-	local netdevs
-	local i
-
-	if [ "$stop" -ge "$start" ]; then
-		i="$start"
-		netdevs="$base_netdev$i"
-
-		while [ "$i" -lt "$stop" ]; do
-			i=$((i + 1))
-			netdevs="$netdevs $base_netdev$i"
-		done
-
-		ucidef_set_interface "$interface" device "$netdevs"
-	fi
-}
-
 board_config_update() {
 	json_init
 	[ -f ${CFG} ] && json_load "$(cat ${CFG})"
--- a/package/boot/arm-trusted-firmware-mediatek/Makefile
+++ b/package/boot/arm-trusted-firmware-mediatek/Makefile
@@ -29,7 +29,6 @@ define Trusted-Firmware-A/Default
  HIDDEN:=y
  BOOT_DEVICE:=
  DDR3_FLYBY:=
-  DDR3_FREQ_1866:=
  DDR_TYPE:=
  NAND_TYPE:=
  BOARD_QFN:=
@@ -38,7 +37,6 @@ define Trusted-Firmware-A/Default
  USE_UBI:=
  FIP_OFFSET:=
  FIP_SIZE:=
-  SPIM_CTRL:=
 endef

 define Trusted-Firmware-A/mt7622-nor-1ddr
@@ -180,7 +178,6 @@ define Trusted-Firmware-A/mt7981-ram-ddr3
  BUILD_SUBTARGET:=filogic
  PLAT:=mt7981
  DDR_TYPE:=ddr3
-  DDR3_FREQ_1866:=1
  RAM_BOOT_UART_DL:=1
  HIDDEN:=
  DEFAULT:=TARGET_mediatek_filogic
@@ -202,15 +199,6 @@ define Trusted-Firmware-A/mt7981-emmc-ddr3
  DDR_TYPE:=ddr3
 endef

-define Trusted-Firmware-A/mt7981-emmc-ddr3-1866mhz
-  NAME:=MediaTek MT7981 (eMMC, DDR3 1866 MHz)
-  BOOT_DEVICE:=emmc
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7981
-  DDR_TYPE:=ddr3
-  DDR3_FREQ_1866:=1
-endef
-
 define Trusted-Firmware-A/mt7981-sdmmc-ddr3
  NAME:=MediaTek MT7981 (SD card, DDR3)
  BOOT_DEVICE:=sdmmc
@@ -235,15 +223,6 @@ define Trusted-Firmware-A/mt7981-spim-nand-ddr3
  DDR_TYPE:=ddr3
 endef

-define Trusted-Firmware-A/mt7981-spim-nand-ddr3-1866mhz
-  NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR3 1866 MHz)
-  BOOT_DEVICE:=spim-nand
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7981
-  DDR_TYPE:=ddr3
-  DDR3_FREQ_1866:=1
-endef
-
 define Trusted-Firmware-A/mt7981-cudy-tr3000-v1
  NAME:=Cudy TR3000 v1 (SPI-NAND via SPIM, DDR3)
  BOOT_DEVICE:=spim-nand
@@ -394,61 +373,6 @@ define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr3
  USE_UBI:=1
 endef

-define Trusted-Firmware-A/mt7987-emmc-comb
-  NAME:=MediaTek MT7987 (eMMC)
-  BOOT_DEVICE:=emmc
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-endef
-
-define Trusted-Firmware-A/mt7987-nor-comb
-  NAME:=MediaTek MT7987 (NOR)
-  BOOT_DEVICE:=nor
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-endef
-
-define Trusted-Firmware-A/mt7987-sdmmc-comb
-  NAME:=MediaTek MT7987 (SD card)
-  BOOT_DEVICE:=sdmmc
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-endef
-
-define Trusted-Firmware-A/mt7987-spim-nand0-ubi-comb
-  NAME:=MediaTek MT7987 (SPI-NAND via SPIM, UBI)
-  BOOT_DEVICE:=spim-nand
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-  USE_UBI:=1
-  SPIM_CTRL:=0
-endef
-
-define Trusted-Firmware-A/mt7987-spim-nand2-ubi-comb
-  NAME:=MediaTek MT7987 (SPI-NAND via SPIM, UBI)
-  BOOT_DEVICE:=spim-nand
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-  USE_UBI:=1
-  SPIM_CTRL:=2
-endef
-
-define Trusted-Firmware-A/mt7987-ram-comb
-  NAME:=MediaTek MT7987 (RAM)
-  BOOT_DEVICE:=ram
-  BUILD_SUBTARGET:=filogic
-  PLAT:=mt7987
-  DRAM_USE_COMB:=1
-  RAM_BOOT_UART_DL:=1
-  HIDDEN:=
-  DEFAULT:=TARGET_mediatek_filogic
-endef
-
 define Trusted-Firmware-A/mt7988-nor-ddr3
  NAME:=MediaTek MT7988 (SPI-NOR, DDR3)
  BOOT_DEVICE:=nor
@@ -633,13 +557,11 @@ TFA_TARGETS:= \
 	mt7622-sdmmc-2ddr \
 	mt7981-ram-ddr3 \
 	mt7981-emmc-ddr3 \
-	mt7981-emmc-ddr3-1866mhz \
 	mt7981-nor-ddr3 \
 	mt7981-nor-ddr4 \
 	mt7981-sdmmc-ddr3 \
 	mt7981-snand-ddr3 \
 	mt7981-spim-nand-ddr3 \
-	mt7981-spim-nand-ddr3-1866mhz \
 	mt7981-spim-nand-ubi-ddr4 \
 	mt7981-ram-ddr4 \
 	mt7981-emmc-ddr4 \
@@ -660,12 +582,6 @@ TFA_TARGETS:= \
 	mt7986-spim-nand-ddr4 \
 	mt7986-spim-nand-ubi-ddr4 \
 	mt7986-spim-nand-4k-ddr4 \
-	mt7987-emmc-comb \
-	mt7987-nor-comb \
-	mt7987-sdmmc-comb \
-	mt7987-spim-nand0-ubi-comb \
-	mt7987-spim-nand2-ubi-comb \
-	mt7987-ram-comb \
 	mt7988-emmc-ddr3 \
 	mt7988-nor-ddr3 \
 	mt7988-sdmmc-ddr3 \
@@ -695,7 +611,6 @@ TFA_MAKE_FLAGS += \
 	$(if $(NAND_TYPE),NAND_TYPE=$(NAND_TYPE)) \
 	HAVE_DRAM_OBJ_FILE=yes \
 	$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \
-	$(if $(DDR3_FREQ_1866),DDR3_FREQ_1866=1) \
 	$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
 	$(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \
 	$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
@@ -703,7 +618,6 @@ TFA_MAKE_FLAGS += \
 	$(if $(USE_UBI),UBI=1 $(if $(findstring mt7986,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x200000)) \
 	$(if $(FIP_OFFSET),OVERRIDE_FIP_BASE=$(FIP_OFFSET)) \
 	$(if $(FIP_SIZE),OVERRIDE_FIP_SIZE=$(FIP_SIZE)) \
-	$(if $(SPIM_CTRL),SPIM_CTRL=$(SPIM_CTRL)) \
 	$(if $(RAM_BOOT_UART_DL),bl2,all)

 define Package/trusted-firmware-a-ram/install
@@ -716,7 +630,6 @@ Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-
 Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
 Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
 Package/trusted-firmware-a-mt7986-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
-Package/trusted-firmware-a-mt7987-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
 Package/trusted-firmware-a-mt7988-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
 Package/trusted-firmware-a-mt7988-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)

--- a/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-add-FudanMicro-manufacturer.patch
+++ b/package/boot/arm-trusted-firmware-mediatek/patches/0004-mediatek-snfi-add-FudanMicro-manufacturer.patch
@@ -1,41 +0,0 @@
-From fd057aba83aea8458986e11c81dbb75a69468b84 Mon Sep 17 00:00:00 2001
-From: Mikhail Zhilkin <csharper2005@gmail.com>
-Date: Wed, 13 Aug 2025 22:46:54 +0300
-Subject: arm-trusted-firmware-mediatek: add FudanMicro manufacturer
-
-Add FudanMicro manufacturer.
-
-Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
---
-
--- a/plat/mediatek/apsoc_common/drivers/spi_nand/mtk_spi_nand.c
-+++ b/plat/mediatek/apsoc_common/drivers/spi_nand/mtk_spi_nand.c
-@@ -21,6 +21,7 @@
- #define SPI_NAND_MAX_ID_LEN		4U
- #define DELAY_US_400MS			400000U
- #define ETRON_ID			0xD5U
-+#define FUDAN_ID			0xA1U
- #define GIGADEVICE_ID			0xC8U
- #define MACRONIX_ID			0xC2U
- #define MICRON_ID			0x2CU
-@@ -146,7 +147,8 @@ static int spi_nand_quad_enable(uint8_t
- 	if (manufacturer_id != MACRONIX_ID &&
- 	    manufacturer_id != GIGADEVICE_ID &&
- 	    manufacturer_id != ETRON_ID &&
-	    manufacturer_id != FORESEE_ID) {
-+	    manufacturer_id != FORESEE_ID &&
-+	    manufacturer_id != FUDAN_ID) {
- 		return 0;
- 	}
- 
-@@ -543,6 +545,10 @@ static int spi_nand_check_pp(struct para
- 		INFO("PP COPY %d CRC read: 0x%x, compute: 0x%x\n",
- 		     i, crc, crc_compute);
- 
-+		// FUDAN integrity CRC (bytes 254-255) is reversed
-+		if (crc != crc_compute)
-+			crc = htobe16(pp->integrity_crc);
-+
- 		if (crc != crc_compute) {
- 			ret = -EBADMSG;
- 			continue;
--- a/package/boot/arm-trusted-firmware-mediatek/patches/0005-mt7987-make-SPI-controller-configurable.patch
+++ b/package/boot/arm-trusted-firmware-mediatek/patches/0005-mt7987-make-SPI-controller-configurable.patch
@@ -1,128 +0,0 @@
-From e2e43103c00b5f7ccedbdbdece0f622cb420b4a5 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 3 Oct 2025 12:53:10 +0100
-Subject: [PATCH] mt7987: make SPI controller configurable
-
-Allow selecting the SPI controller used for SPIM-NAND or SPI-NOR boot
-devices (either SPI0 or SPI2).
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- plat/mediatek/apsoc_common/Config.in        |  1 +
- plat/mediatek/mt7987/Config.in              | 29 +++++++++++++++++++++
- plat/mediatek/mt7987/bl2/bl2.mk             | 12 +++++++++
- plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c | 10 ++++++-
- plat/mediatek/mt7987/platform.mk            |  4 +--
- 5 files changed, 53 insertions(+), 3 deletions(-)
- create mode 100644 plat/mediatek/mt7987/Config.in
-
--- a/plat/mediatek/apsoc_common/Config.in
-+++ b/plat/mediatek/apsoc_common/Config.in
-@@ -783,6 +783,7 @@ config ENABLE_BL31_RUNTIME_LOG
- 	default 1
- 	depends on _ENABLE_BL31_RUNTIME_LOG
- 
-+source "plat/mediatek/mt7987/Config.in"
- source "plat/mediatek/mt7988/Config.in"
- 
- endmenu # Platform configurations
--- /dev/null
-+++ b/plat/mediatek/mt7987/Config.in
-@@ -0,0 +1,29 @@
-+# SPDX-License-Identifier: BSD-3-Clause
-+#
-+# Copyright (c) 2025 Daniel Golle <daniel@makrotopia.org>
-+#
-+# MT7987 platform-specific configurations
-+#
-+
-+if _PLAT_MT7987
-+
-+choice
-+	prompt "SPI controller"
-+	depends on (_BOOT_DEVICE_SPIM_NAND || _BOOT_DEVICE_SPI_NOR)
-+	default _SPIM_CTRL_0 if _BOOT_DEVICE_SPIM_NAND
-+	default _SPIM_CTRL_2 if _BOOT_DEVICE_SPI_NOR
-+
-+	config _SPIM_CTRL_0
-+		bool "0"
-+
-+	config _SPIM_CTRL_2
-+		bool "2"
-+
-+endchoice
-+
-+config SPIM_CTRL
-+	int
-+	default 0 if _SPIM_CTRL_0
-+	default 2 if _SPIM_CTRL_2
-+
-+endif # _PLAT_MT7987
--- a/plat/mediatek/mt7987/bl2/bl2.mk
-+++ b/plat/mediatek/mt7987/bl2/bl2.mk
-@@ -91,7 +91,11 @@ endif # END OF BOOT_DEVICE = ram
- ifeq ($(BOOT_DEVICE),nor)
- $(eval $(call BL2_BOOT_NOR))
- BL2_SOURCES		+=	$(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nor.c
-+ifeq ($(SPIM_CTRL),0)
-+DTS_NAME		:=	mt7987-spi0
-+else
- DTS_NAME		:=	mt7987-spi2
-+endif
- endif # END OF BOOTDEVICE = nor
- 
- ifeq ($(BOOT_DEVICE),emmc)
-@@ -112,10 +116,18 @@ ifeq ($(BOOT_DEVICE),spim-nand)
- $(eval $(call BL2_BOOT_SPI_NAND,0,0))
- BL2_SOURCES		+=	$(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nand.c
- NAND_TYPE		?=	spim:2k+64
-+ifeq ($(SPIM_CTRL),2)
-+DTS_NAME		:=	mt7987-spi2
-+else
- DTS_NAME		:=	mt7987-spi0
-+endif
- $(eval $(call BL2_BOOT_NAND_TYPE_CHECK,$(NAND_TYPE),spim:2k+64 spim:2k+128 spim:4k+256))
- endif # END OF BOOTDEVICE = spim-nand
- 
-+ifneq ($(SPIM_CTRL),)
-+BL2_CPPFLAGS		+=	-DSPIM_CTRL=$(SPIM_CTRL)
-+endif
-+
- ifeq ($(BROM_HEADER_TYPE),)
- $(error BOOT_DEVICE has invalid value. Please re-check.)
- endif
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
-+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
-@@ -12,10 +12,18 @@
- 
- #define MTK_QSPI_SRC_CLK		CB_MPLL_D2
- 
-+#if SPIM_CTRL == 0
-+#define SELECTED_SPIM SPIM0
-+#elif SPIM_CTRL == 2
-+#define SELECTED_SPIM SPIM2
-+#else
-+#error "Invalid SPI controller selection"
-+#endif
-+
- uint32_t mtk_plat_get_qspi_src_clk(void)
- {
- 	/* config GPIO pinmux to spi mode */
-	mtk_spi_gpio_init(SPIM0);
-+	mtk_spi_gpio_init(SELECTED_SPIM);
- 
- 	/* select 208M clk */
- 	mtk_spi_source_clock_select(MTK_QSPI_SRC_CLK);
--- a/plat/mediatek/mt7987/platform.mk
-+++ b/plat/mediatek/mt7987/platform.mk
-@@ -56,8 +56,8 @@ include make_helpers/dep.mk
- 
- $(call GEN_DEP_RULES,bl2,emicfg bl2_boot_ram bl2_boot_nand_nmbm bl2_dev_mmc bl2_plat_init bl2_plat_setup mt7987_gpio dtb)
- $(call MAKE_DEP,bl2,emicfg,DDR4_4BG_MODE DRAM_DEBUG_LOG DDR3_FREQ_2133 DDR3_FREQ_1866 DDR4_FREQ_3200 DDR4_FREQ_2666)
-$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS)
-$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET)
-+$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS SPIM_CTRL)
-+$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET SPIM_CTRL)
- $(call MAKE_DEP,bl2,bl2_dev_mmc,BOOT_DEVICE)
- $(call MAKE_DEP,bl2,bl2_boot_ram,RAM_BOOT_DEBUGGER_HOOK RAM_BOOT_UART_DL)
- $(call MAKE_DEP,bl2,bl2_boot_nand_nmbm,NMBM_MAX_RATIO NMBM_MAX_RESERVED_BLOCKS NMBM_DEFAULT_LOG_LEVEL)
--- a/package/boot/arm-trusted-firmware-mediatek/patches/0006-hack-mt7987-mmc-use-4-bit-bus-width-for-eMMC.patch
+++ b/package/boot/arm-trusted-firmware-mediatek/patches/0006-hack-mt7987-mmc-use-4-bit-bus-width-for-eMMC.patch
@@ -1,24 +0,0 @@
-From 0a09912eb336bee788443b919ea5b99b195f5a91 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 4 Oct 2025 22:13:49 +0100
-Subject: [PATCH] hack: mt7987: mmc: use 4-bit bus-width for eMMC
-
-The BananaPi R4 Lite has broken DAT5 signal of the MMC bus, which
-results in 8-bit buswidth not working well for the eMMC.
-Reduce to 4-bit buswidth fixes it (and makes all other boards with
-eMMC a tiny bit slower to boot, but it's in the milliseconds).
---
- plat/mediatek/mt7987/bl2/bl2_dev_mmc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
--- a/plat/mediatek/mt7987/bl2/bl2_dev_mmc.c
-+++ b/plat/mediatek/mt7987/bl2/bl2_dev_mmc.c
-@@ -74,7 +74,7 @@ static const struct mt7987_msdc_conf {
- 	{
- 		.base = MSDC0_BASE,
- 		.top_base = MSDC0_TOP_BASE,
-		.bus_width = MMC_BUS_WIDTH_8,
-+		.bus_width = MMC_BUS_WIDTH_4,
- 		.type = MMC_IS_EMMC,
- 		.src_clk = 200000000,
- 		.dev_comp = &mt7987_msdc_compat,
--- a/package/boot/arm-trusted-firmware-mediatek/patches/0007-hack-mt7987-bl2-move-FIP-offset-to-0x100000.patch
+++ b/package/boot/arm-trusted-firmware-mediatek/patches/0007-hack-mt7987-bl2-move-FIP-offset-to-0x100000.patch
@@ -1,27 +0,0 @@
-From 6725bb3c2aa9330f37a591e1e539badf67021b47 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Sat, 4 Oct 2025 23:59:54 +0100
-Subject: [PATCH] hack: mt7987: bl2: move FIP offset to 0x100000
-
-There is no use in allocating more than 2MB to the factory partition.
-After all, even for WiFi 7 tri-band devices the calibration data is
-still in the kilobytes range.
-Move FIP offset to 0x100000 to not waste so much space on small NOR
-flash.
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
-+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
-@@ -7,7 +7,7 @@
- #include <stdint.h>
- #include <boot_spi.h>
- 
-#define FIP_BASE			0x250000
-+#define FIP_BASE			0x100000
- #define FIP_SIZE			0x80000
- 
- #define MTK_QSPI_SRC_CLK		CB_MPLL_D2
--- a/package/boot/arm-trusted-firmware-rockchip/Makefile
+++ b/package/boot/arm-trusted-firmware-rockchip/Makefile
@@ -7,10 +7,11 @@

 include $(TOPDIR)/rules.mk

-PKG_VERSION:=2.13
+PKG_VERSION:=2.12.1
 PKG_RELEASE:=1
+PKG_LTS:=1

-PKG_HASH:=afb5c408392fcec840bd30de9b02a236b0108142024f9853b542b596b0d894e3
+PKG_HASH:=c0d432a851da452d927561feaf45f569c1cde57985782beadfe29e616e260440

 PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de>

@@ -33,11 +34,6 @@ define Trusted-Firmware-A/rk3399
  PLAT:=rk3399
 endef

-define Trusted-Firmware-A/rk3576
-  BUILD_SUBTARGET:=armv8
-  PLAT:=rk3576
-endef
-
 define Trusted-Firmware-A/rk3588
  BUILD_SUBTARGET:=armv8
  PLAT:=rk3588
@@ -46,12 +42,11 @@ endef
 TFA_TARGETS:= \
 	rk3328 \
 	rk3399 \
-	rk3576 \
 	rk3588

 ifeq ($(BUILD_VARIANT),rk3399)
-  M0_GCC_NAME:=arm-gnu-toolchain
-  M0_GCC_RELEASE:=12.3.rel1
+  M0_GCC_NAME:=gcc-arm
+  M0_GCC_RELEASE:=11.2-2022.02
  M0_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi
  M0_GCC_SOURCE:=$(M0_GCC_NAME)-$(M0_GCC_RELEASE)-$(M0_GCC_VERSION).tar.xz

@@ -59,9 +54,9 @@ ifeq ($(BUILD_VARIANT),rk3399)
    FILE:=$(M0_GCC_SOURCE)
    URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(M0_GCC_RELEASE)/binrel
  ifeq ($(HOST_ARCH),aarch64)
-    HASH:=14c0487d5753f6071d24e568881f7c7e67f80dd83165dec5164b3731394af431
+    HASH:=ef1d82e5894e3908cb7ed49c5485b5b95deefa32872f79c2b5f6f5447cabf55f
  else
-    HASH:=12a2815644318ebcceaf84beabb665d0924b6e79e21048452c5331a56332b309
+    HASH:=8c5acd5ae567c0100245b0556941c237369f210bceb196edfe5a2e7532c60326
  endif
  endef

--- a/package/boot/rkbin/Makefile
+++ b/package/boot/rkbin/Makefile
@@ -9,9 +9,9 @@ PKG_RELEASE:=1

 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://github.com/rockchip-linux/rkbin.git
-PKG_SOURCE_DATE:=2025-06-13
-PKG_SOURCE_VERSION:=74213af1e952c4683d2e35952507133b61394862
-PKG_MIRROR_HASH:=4b801b1301ae297f660340617b5f398b23a3f0b43bc7f0ef42c21f0f43eb8990
+PKG_SOURCE_DATE:=2024-02-22
+PKG_SOURCE_VERSION:=a2a0b89b6c8c612dca5ed9ed8a68db8a07f68bc0
+PKG_MIRROR_HASH:=39f15e5f8fac02026065b6747b355b93f4e06202783ae448c43607763211597c

 PKG_LICENSE_FILES:=LICENSE
 PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
@@ -27,91 +27,78 @@ endef

 define Trusted-Firmware-A/rk3308
  BUILD_SUBTARGET:=armv8
-  ATF:=rk33/rk3308_bl31_v2.27.elf
-  TPL:=rk33/rk3308_ddr_589MHz_uart2_m1_v2.10.bin
+  ATF:=rk33/rk3308_bl31_v2.26.elf
+  TPL:=rk33/rk3308_ddr_589MHz_uart2_m1_v2.07.bin
 endef

-define Trusted-Firmware-A/rk3308-tpl-rock-pi-s
-  NAME:=Radxa ROCK Pi S board
+define Trusted-Firmware-A/rk3308-rock-pi-s
+  NAME:=Radxa ROCK Pi S
  BUILD_SUBTARGET:=armv8
-  TPL:=rk33/rk3308_ddr_589MHz_uart0_m0_v2.10.bin
-endef
-
-define Trusted-Firmware-A/rk3528
-  BUILD_SUBTARGET:=armv8
-  ATF:=rk35/rk3528_bl31_v1.20.elf
-  TPL:=rk35/rk3528_ddr_1056MHz_v1.11.bin
+  ATF:=rk33/rk3308_bl31_v2.26.elf
+  TPL:=rk33/rk3308_ddr_589MHz_uart0_m0_v2.07.bin
 endef

 define Trusted-Firmware-A/rk3566
  BUILD_SUBTARGET:=armv8
-  ATF:=rk35/rk3568_bl31_v1.45.elf
-  TPL:=rk35/rk3566_ddr_1056MHz_v1.23.bin
+  ATF:=rk35/rk3568_bl31_v1.44.elf
+  TPL:=rk35/rk3566_ddr_1056MHz_v1.21.bin
 endef

 define Trusted-Firmware-A/rk3568
  BUILD_SUBTARGET:=armv8
-  ATF:=rk35/rk3568_bl31_v1.45.elf
-  TPL:=rk35/rk3568_ddr_1560MHz_v1.23.bin
+  ATF:=rk35/rk3568_bl31_v1.44.elf
+  TPL:=rk35/rk3568_ddr_1560MHz_v1.21.bin
 endef

-define Trusted-Firmware-A/rk3568-tpl-e25
+define Trusted-Firmware-A/rk3568-e25
  NAME:=Radxa E25 board
  BUILD_SUBTARGET:=armv8
-  TPL:=rk35/rk3568_ddr_1560MHz_uart2_m0_115200_v1.23.bin
-endef
-
-define Trusted-Firmware-A/rk3576-tpl
-  NAME:=Rockchip RK3576 SoCs
-  BUILD_SUBTARGET:=armv8
-  TPL:=rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.09.bin
+  ATF:=rk35/rk3568_bl31_v1.44.elf
+  TPL:=rk35/rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin
 endef

 define Trusted-Firmware-A/rk3588-tpl
-  NAME:=Rockchip RK3588 SoCs
  BUILD_SUBTARGET:=armv8
-  TPL:=rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.19.bin
+  TPL:=rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
 endef

 TFA_TARGETS:= \
 	rk3308 \
-	rk3308-tpl-rock-pi-s \
-	rk3528 \
+	rk3308-rock-pi-s \
 	rk3566 \
 	rk3568 \
-	rk3568-tpl-e25 \
-	rk3576-tpl \
+	rk3568-e25 \
 	rk3588-tpl

-ifeq ($(BUILD_VARIANT),rk3308-tpl-rock-pi-s)
+ifeq ($(BUILD_VARIANT),rk3308-rock-pi-s)
+  TPL_FILE:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin
  define Download/rk3308-tpl-rock-pi-s
-    FILE:=$(notdir $(TPL))
-    URL_FILE:=$(TPL)
-    URL:=https://github.com/radxa/rkbin/raw/2b54df9d062ef91a9fffbc85472b070c9220c4cf/bin/
-    HASH:=45af030ed2cb322cc5a91c32350130fc1f1ea9508794fa4b5d309eadf70e3d04
+    FILE:=$(TPL_FILE)
+    URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk33/
+    HASH:=8a1a42df23cccb86a2dabc14a5c0e9227d64a51b9b83e9968ef5af3b30787f7d
  endef

  define Build/Prepare
 	$(eval $(call Download,rk3308-tpl-rock-pi-s))
 	$(call Build/Prepare/Default)

-	$(CP) $(DL_DIR)/$(notdir $(TPL)) $(PKG_BUILD_DIR)/bin/$(TPL)
+	$(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk33/
  endef
 endif

-ifeq ($(BUILD_VARIANT),rk3568-tpl-e25)
+ifeq ($(BUILD_VARIANT),rk3568-e25)
+  TPL_FILE:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin
  define Download/rk3568-tpl-e25
-    FILE:=$(notdir $(TPL))
-    URL_FILE:=$(TPL)
-    URL:=https://github.com/radxa/rkbin/raw/2e77c53ab0279585b09ecdaa54fe3e2bf80f9475/bin/
-    HASH:=1bb9f92a6515a70b91c0f8bd3aa4dc31432afc4317b9408f82c43ca63cb10ab6
+    FILE:=$(TPL_FILE)
+    URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk35/
+    HASH:=1815f9649dc5661a3ef184b052da39286e51453a66f6ff53cc3e345d65dfabd4
  endef

  define Build/Prepare
 	$(eval $(call Download,rk3568-tpl-e25))
 	$(call Build/Prepare/Default)

-	$(CP) $(DL_DIR)/$(notdir $(TPL)) $(PKG_BUILD_DIR)/bin/$(TPL)
+	$(CP) $(DL_DIR)/$(TPL_FILE) $(PKG_BUILD_DIR)/bin/rk35/
  endef
 endif

--- a/package/boot/uboot-airoha/Makefile
+++ b/package/boot/uboot-airoha/Makefile
@@ -1,94 +0,0 @@
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2025.07
-PKG_HASH:=0f933f6c5a426895bf306e93e6ac53c60870e4b54cda56d95211bec99e63bec7
-PKG_BUILD_DEPENDS:=arm-trusted-firmware-tools/host
-
-UBOOT_USE_INTREE_DTC:=1
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-include $(INCLUDE_DIR)/host-build.mk
-
-define U-Boot/Default
-  BUILD_TARGET:=airoha
-  FIP_COMPRESS:=1
-endef
-
-define U-Boot/an7581_rfb
-  NAME:=AN7581 Reference Board
-  UBOOT_CONFIG:=an7581_evb
-  BUILD_DEVICES:=airoha_an7581-evb
-  BUILD_SUBTARGET:=an7581
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_IMAGE:=an7581-bl2.bin
-  BL31_IMAGE:=an7581-bl31.bin
-endef
-
-define U-Boot/an7583_rfb
-  NAME:=AN7583 Reference Board
-  UBOOT_CONFIG:=an7583_evb
-  BUILD_DEVICES:=airoha_an7583-evb
-  BUILD_SUBTARGET:=an7583
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_IMAGE:=an7583-bl2.bin
-  BL31_IMAGE:=an7583-bl31.bin
-endef
-
-UBOOT_TARGETS := \
-	an7581_rfb \
-	an7583_rfb
-
-UBOOT_CUSTOMIZE_CONFIG := \
-	--disable TOOLS_KWBIMAGE \
-	--disable TOOLS_LIBCRYPTO \
-	--disable TOOLS_MKEFICAPSULE \
-	--enable SERIAL_RX_BUFFER \
-	--set-val SERIAL_RX_BUFFER_SIZE 256
-
-define Build/fip-image-bl2
-	$(STAGING_DIR_HOST)/bin/fiptool create \
-		--tb-fw files/$(BL2_IMAGE) \
-		$(PKG_BUILD_DIR)/bl2.fip
-endef
-
-define Build/fip-image
-	$(if $(FIP_COMPRESS), $(STAGING_DIR_HOST)/bin/lzma e \
-		$(PKG_BUILD_DIR)/u-boot.bin \
-		$(PKG_BUILD_DIR)/u-boot.bin.lzma)
-	$(if $(FIP_COMPRESS), $(STAGING_DIR_HOST)/bin/lzma e \
-		files/$(BL31_IMAGE) \
-		$(PKG_BUILD_DIR)/bl31.bin.lzma)
-	$(STAGING_DIR_HOST)/bin/fiptool create \
-		--soc-fw $(PKG_BUILD_DIR)/bl31.bin$(if $(FIP_COMPRESS),.lzma) \
-		--nt-fw $(PKG_BUILD_DIR)/u-boot.bin$(if $(FIP_COMPRESS),.lzma) \
-		$(PKG_BUILD_DIR)/u-boot.fip
-endef
-
-define Build/Configure
-	$(call Build/Configure/U-Boot)
-	sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config
-endef
-
-define Build/Compile
-	$(call Build/Compile/U-Boot)
-ifeq ($(UBOOT_IMAGE),u-boot.fip)
-	$(call Build/fip-image-bl2)
-	$(call Build/fip-image)
-endif
-endef
-
-# don't stage files to bindir, let target/linux/airoha/image/*.mk do that
-define Package/u-boot/install
-endef
-
-define Build/InstallDev
-	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
-ifeq ($(UBOOT_IMAGE),u-boot.fip)
-	$(INSTALL_DATA) $(PKG_BUILD_DIR)/bl2.fip $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl2.fip
-	$(INSTALL_DATA) $(PKG_BUILD_DIR)/u-boot.fip $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl31-u-boot.fip
-endif
-endef
-
-$(eval $(call BuildPackage/U-Boot))
--- a/package/boot/uboot-airoha/files/an7581-bl2.bin
+++ b/package/boot/uboot-airoha/files/an7581-bl2.bin
--- a/package/boot/uboot-airoha/files/an7581-bl31.bin
+++ b/package/boot/uboot-airoha/files/an7581-bl31.bin
--- a/package/boot/uboot-airoha/files/an7583-bl2.bin
+++ b/package/boot/uboot-airoha/files/an7583-bl2.bin
--- a/package/boot/uboot-airoha/files/an7583-bl31.bin
+++ b/package/boot/uboot-airoha/files/an7583-bl31.bin
--- a/package/boot/uboot-airoha/patches/200-linux-bitfield.h-import-FIELD_PREP_CONST-macro-from-.patch
+++ b/package/boot/uboot-airoha/patches/200-linux-bitfield.h-import-FIELD_PREP_CONST-macro-from-.patch
@@ -1,55 +0,0 @@
-From 4f1fcf5281ee4e22b1e89a62bd0417878bcbeca5 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 3 Jun 2025 10:41:18 +0200
-Subject: [PATCH 1/2] linux/bitfield.h: import FIELD_PREP_CONST macro from
- Linux Kernel
-
-Import FIELD_PREP_CONST macro from Linux Kernel to permit usage of
-FIELD_PREP with scenario where a constant value is needed.
-
-Refer to commit e2192de59e45 ("bitfield: add FIELD_PREP_CONST()") in
-Linux kernel for extensive explaination of why this is useful.
-
-This is also to better align with the Linux Kernel for easier porting of
-driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- include/linux/bitfield.h | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
--- a/include/linux/bitfield.h
-+++ b/include/linux/bitfield.h
-@@ -90,6 +90,32 @@
- 		((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask);	\
- 	})
- 
-+#define __BF_CHECK_POW2(n)	BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0)
-+
-+/**
-+ * FIELD_PREP_CONST() - prepare a constant bitfield element
-+ * @_mask: shifted mask defining the field's length and position
-+ * @_val:  value to put in the field
-+ *
-+ * FIELD_PREP_CONST() masks and shifts up the value.  The result should
-+ * be combined with other fields of the bitfield using logical OR.
-+ *
-+ * Unlike FIELD_PREP() this is a constant expression and can therefore
-+ * be used in initializers. Error checking is less comfortable for this
-+ * version, and non-constant masks cannot be used.
-+ */
-+#define FIELD_PREP_CONST(_mask, _val)					\
-+	(								\
-+		/* mask must be non-zero */				\
-+		BUILD_BUG_ON_ZERO((_mask) == 0) +			\
-+		/* check if value fits */				\
-+		BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \
-+		/* check if mask is contiguous */			\
-+		__BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) +	\
-+		/* and create the value */				\
-+		(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask))	\
-+	)
-+
- /**
-  * FIELD_GET() - extract a bitfield element
-  * @_mask: shifted mask defining the field's length and position
--- a/package/boot/uboot-airoha/patches/202-mtd-spinand-Use-the-spi-mem-dirmap-API.patch
+++ b/package/boot/uboot-airoha/patches/202-mtd-spinand-Use-the-spi-mem-dirmap-API.patch
@@ -1,320 +0,0 @@
-From f45ae9019afb838979792e4237e344003151fbf7 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 12 Nov 2023 20:57:52 +0300
-Subject: [PATCH 1/5] mtd: spinand: Use the spi-mem dirmap API
-
-Make use of the spi-mem direct mapping API to let advanced controllers
-optimize read/write operations when they support direct mapping.
-
-Based on a linux commit 981d1aa0697c ("mtd: spinand: Use the spi-mem dirmap API")
-created by Boris Brezillon <bbrezillon@kernel.org> with additional
-fixes taken from Linux 6.10.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
---
- drivers/mtd/nand/spi/core.c | 185 +++++++++++++++++-------------------
- include/linux/mtd/spinand.h |   7 ++
- 2 files changed, 95 insertions(+), 97 deletions(-)
-
-diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
-index f5ddfbf4b83..ea00cd7dcf0 100644
--- a/drivers/mtd/nand/spi/core.c
-+++ b/drivers/mtd/nand/spi/core.c
-@@ -41,21 +41,6 @@ struct spinand_plat {
- /* SPI NAND index visible in MTD names */
- static int spi_nand_idx;
- 
-static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
-					  const struct nand_page_io_req *req,
-					  u16 *column)
-{
-	struct nand_device *nand = spinand_to_nand(spinand);
-	unsigned int shift;
-
-	if (nand->memorg.planes_per_lun < 2)
-		return;
-
-	/* The plane number is passed in MSB just above the column address */
-	shift = fls(nand->memorg.pagesize);
-	*column |= req->pos.plane << shift;
-}
-
- static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
- {
- 	struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
-@@ -249,27 +234,21 @@ static int spinand_load_page_op(struct spinand_device *spinand,
- static int spinand_read_from_cache_op(struct spinand_device *spinand,
- 				      const struct nand_page_io_req *req)
- {
-	struct spi_mem_op op = *spinand->op_templates.read_cache;
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	struct mtd_info *mtd = nanddev_to_mtd(nand);
-	struct nand_page_io_req adjreq = *req;
-+	struct spi_mem_dirmap_desc *rdesc;
- 	unsigned int nbytes = 0;
- 	void *buf = NULL;
- 	u16 column = 0;
-	int ret;
-+	ssize_t ret;
- 
- 	if (req->datalen) {
-		adjreq.datalen = nanddev_page_size(nand);
-		adjreq.dataoffs = 0;
-		adjreq.databuf.in = spinand->databuf;
- 		buf = spinand->databuf;
-		nbytes = adjreq.datalen;
-+		nbytes = nanddev_page_size(nand);
-+		column = 0;
- 	}
- 
- 	if (req->ooblen) {
-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
-		adjreq.ooboffs = 0;
-		adjreq.oobbuf.in = spinand->oobbuf;
- 		nbytes += nanddev_per_page_oobsize(nand);
- 		if (!buf) {
- 			buf = spinand->oobbuf;
-@@ -277,28 +256,19 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
- 		}
- 	}
- 
-	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
-	op.addr.val = column;
-+	rdesc = spinand->dirmaps[req->pos.plane].rdesc;
- 
-	/*
-	 * Some controllers are limited in term of max RX data size. In this
-	 * case, just repeat the READ_CACHE operation after updating the
-	 * column.
-	 */
- 	while (nbytes) {
-		op.data.buf.in = buf;
-		op.data.nbytes = nbytes;
-		ret = spi_mem_adjust_op_size(spinand->slave, &op);
-		if (ret)
-+		ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
-+		if (ret < 0)
- 			return ret;
- 
-		ret = spi_mem_exec_op(spinand->slave, &op);
-		if (ret)
-			return ret;
-+		if (!ret || ret > nbytes)
-+			return -EIO;
- 
-		buf += op.data.nbytes;
-		nbytes -= op.data.nbytes;
-		op.addr.val += op.data.nbytes;
-+		nbytes -= ret;
-+		column += ret;
-+		buf += ret;
- 	}
- 
- 	if (req->datalen)
-@@ -322,14 +292,12 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
- static int spinand_write_to_cache_op(struct spinand_device *spinand,
- 				     const struct nand_page_io_req *req)
- {
-	struct spi_mem_op op = *spinand->op_templates.write_cache;
- 	struct nand_device *nand = spinand_to_nand(spinand);
- 	struct mtd_info *mtd = nanddev_to_mtd(nand);
-	struct nand_page_io_req adjreq = *req;
-	unsigned int nbytes = 0;
-	void *buf = NULL;
-	u16 column = 0;
-	int ret;
-+	struct spi_mem_dirmap_desc *wdesc;
-+	unsigned int nbytes, column = 0;
-+	void *buf = spinand->databuf;
-+	ssize_t ret;
- 
- 	/*
- 	 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
-@@ -338,19 +306,12 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
- 	 * the data portion of the page, otherwise we might corrupt the BBM or
- 	 * user data previously programmed in OOB area.
- 	 */
-	memset(spinand->databuf, 0xff,
-	       nanddev_page_size(nand) +
-	       nanddev_per_page_oobsize(nand));
-+	nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
-+	memset(spinand->databuf, 0xff, nbytes);
- 
-	if (req->datalen) {
-+	if (req->datalen)
- 		memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
- 		       req->datalen);
-		adjreq.dataoffs = 0;
-		adjreq.datalen = nanddev_page_size(nand);
-		adjreq.databuf.out = spinand->databuf;
-		nbytes = adjreq.datalen;
-		buf = spinand->databuf;
-	}
- 
- 	if (req->ooblen) {
- 		if (req->mode == MTD_OPS_AUTO_OOB)
-@@ -361,52 +322,21 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
- 		else
- 			memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
- 			       req->ooblen);
-
-		adjreq.ooblen = nanddev_per_page_oobsize(nand);
-		adjreq.ooboffs = 0;
-		nbytes += nanddev_per_page_oobsize(nand);
-		if (!buf) {
-			buf = spinand->oobbuf;
-			column = nanddev_page_size(nand);
-		}
- 	}
- 
-	spinand_cache_op_adjust_colum(spinand, &adjreq, &column);
-
-	op = *spinand->op_templates.write_cache;
-	op.addr.val = column;
-+	wdesc = spinand->dirmaps[req->pos.plane].wdesc;
- 
-	/*
-	 * Some controllers are limited in term of max TX data size. In this
-	 * case, split the operation into one LOAD CACHE and one or more
-	 * LOAD RANDOM CACHE.
-	 */
- 	while (nbytes) {
-		op.data.buf.out = buf;
-		op.data.nbytes = nbytes;
-
-		ret = spi_mem_adjust_op_size(spinand->slave, &op);
-		if (ret)
-			return ret;
-
-		ret = spi_mem_exec_op(spinand->slave, &op);
-		if (ret)
-+		ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
-+		if (ret < 0)
- 			return ret;
- 
-		buf += op.data.nbytes;
-		nbytes -= op.data.nbytes;
-		op.addr.val += op.data.nbytes;
-+		if (!ret || ret > nbytes)
-+			return -EIO;
- 
-		/*
-		 * We need to use the RANDOM LOAD CACHE operation if there's
-		 * more than one iteration, because the LOAD operation resets
-		 * the cache to 0xff.
-		 */
-		if (nbytes) {
-			column = op.addr.val;
-			op = *spinand->op_templates.update_cache;
-			op.addr.val = column;
-		}
-+		nbytes -= ret;
-+		column += ret;
-+		buf += ret;
- 	}
- 
- 	return 0;
-@@ -819,6 +749,59 @@ static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
- 	return ret;
- }
- 
-+static int spinand_create_dirmap(struct spinand_device *spinand,
-+				 unsigned int plane)
-+{
-+	struct nand_device *nand = spinand_to_nand(spinand);
-+	struct spi_mem_dirmap_info info = {
-+		.length = nanddev_page_size(nand) +
-+			  nanddev_per_page_oobsize(nand),
-+	};
-+	struct spi_mem_dirmap_desc *desc;
-+
-+	/* The plane number is passed in MSB just above the column address */
-+	info.offset = plane << fls(nand->memorg.pagesize);
-+
-+	info.op_tmpl = *spinand->op_templates.update_cache;
-+	desc = spi_mem_dirmap_create(spinand->slave, &info);
-+	if (IS_ERR(desc))
-+		return PTR_ERR(desc);
-+
-+	spinand->dirmaps[plane].wdesc = desc;
-+
-+	info.op_tmpl = *spinand->op_templates.read_cache;
-+	desc = spi_mem_dirmap_create(spinand->slave, &info);
-+	if (IS_ERR(desc)) {
-+		spi_mem_dirmap_destroy(spinand->dirmaps[plane].wdesc);
-+		return PTR_ERR(desc);
-+	}
-+
-+	spinand->dirmaps[plane].rdesc = desc;
-+
-+	return 0;
-+}
-+
-+static int spinand_create_dirmaps(struct spinand_device *spinand)
-+{
-+	struct nand_device *nand = spinand_to_nand(spinand);
-+	int i, ret;
-+
-+	spinand->dirmaps = devm_kzalloc(spinand->slave->dev,
-+					sizeof(*spinand->dirmaps) *
-+					nand->memorg.planes_per_lun,
-+					GFP_KERNEL);
-+	if (!spinand->dirmaps)
-+		return -ENOMEM;
-+
-+	for (i = 0; i < nand->memorg.planes_per_lun; i++) {
-+		ret = spinand_create_dirmap(spinand, i);
-+		if (ret)
-+			return ret;
-+	}
-+
-+	return 0;
-+}
-+
- static const struct nand_ops spinand_ops = {
- 	.erase = spinand_erase,
- 	.markbad = spinand_markbad,
-@@ -1116,6 +1099,14 @@ static int spinand_init(struct spinand_device *spinand)
- 		goto err_free_bufs;
- 	}
- 
-+	ret = spinand_create_dirmaps(spinand);
-+	if (ret) {
-+		dev_err(spinand->slave->dev,
-+			"Failed to create direct mappings for read/write operations (err = %d)\n",
-+			ret);
-+		goto err_manuf_cleanup;
-+	}
-+
- 	/* After power up, all blocks are locked, so unlock them here. */
- 	for (i = 0; i < nand->memorg.ntargets; i++) {
- 		ret = spinand_select_target(spinand, i);
-diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
-index 6fe6fd520a4..163269313f6 100644
--- a/include/linux/mtd/spinand.h
-+++ b/include/linux/mtd/spinand.h
-@@ -363,6 +363,11 @@ struct spinand_info {
- 		__VA_ARGS__						\
- 	}
- 
-+struct spinand_dirmap {
-+	struct spi_mem_dirmap_desc *wdesc;
-+	struct spi_mem_dirmap_desc *rdesc;
-+};
-+
- /**
-  * struct spinand_device - SPI NAND device instance
-  * @base: NAND device instance
-@@ -406,6 +411,8 @@ struct spinand_device {
- 		const struct spi_mem_op *update_cache;
- 	} op_templates;
- 
-+	struct spinand_dirmap *dirmaps;
-+
- 	int (*select_target)(struct spinand_device *spinand,
- 			     unsigned int target);
- 	unsigned int cur_target;
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/203-spi-airoha-remove-unnecessary-operation-adjust_op_si.patch
+++ b/package/boot/uboot-airoha/patches/203-spi-airoha-remove-unnecessary-operation-adjust_op_si.patch
@@ -1,51 +0,0 @@
-From 1e29cf13c183ee457ed70055f5cbff60ff56a726 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 7 Jun 2025 07:18:12 +0300
-Subject: [PATCH 2/5] spi: airoha: remove unnecessary operation adjust_op_size
-
-This operation is not needed because airoha_snand_write_data() and
-airoha_snand_read_data() will properly handle data transfers above
-SPI_MAX_TRANSFER_SIZE.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 16 ----------------
- 1 file changed, 16 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 3ea25b293d1..4eb01038404 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -525,21 +525,6 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
- 				  SPI_NFI_CUS_SEC_SIZE, val);
- }
- 
-static int airoha_snand_adjust_op_size(struct spi_slave *slave,
-				       struct spi_mem_op *op)
-{
-	size_t max_len;
-
-	max_len = 1 + op->addr.nbytes + op->dummy.nbytes;
-	if (max_len >= 160)
-		return -EOPNOTSUPP;
-
-	if (op->data.nbytes > 160 - max_len)
-		op->data.nbytes = 160 - max_len;
-
-	return 0;
-}
-
- static bool airoha_snand_supports_op(struct spi_slave *slave,
- 				     const struct spi_mem_op *op)
- {
-@@ -691,7 +676,6 @@ static int airoha_snand_nfi_setup(struct spi_slave *slave,
- }
- 
- static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
-	.adjust_op_size = airoha_snand_adjust_op_size,
- 	.supports_op = airoha_snand_supports_op,
- 	.exec_op = airoha_snand_exec_op,
- };
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/204-spi-airoha-add-support-of-dual-quad-wires-spi-modes-.patch
+++ b/package/boot/uboot-airoha/patches/204-spi-airoha-add-support-of-dual-quad-wires-spi-modes-.patch
@@ -1,262 +0,0 @@
-From fe8c32af9d8c8ff8875efece82001680fc300ad5 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sat, 7 Jun 2025 09:09:38 +0300
-Subject: [PATCH 3/5] spi: airoha: add support of dual/quad wires spi modes
- to exec_op() handler
-
-Booting without this patch and disabled dirmap support results in
-
-[    2.980719] spi-nand spi0.0: Micron SPI NAND was found.
-[    2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
-[    2.994709] 2 fixed-partitions partitions found on MTD device spi0.0
-[    3.001075] Creating 2 MTD partitions on "spi0.0":
-[    3.005862] 0x000000000000-0x000000020000 : "bl2"
-[    3.011272] 0x000000020000-0x000010000000 : "ubi"
-...
-[    6.195594] ubi0: attaching mtd1
-[   13.338398] ubi0: scanning is finished
-[   13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found
-[   13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
-[   13.356897] UBI error: cannot attach mtd1
-
-If dirmap is disabled or not supported in the spi driver, the dirmap requests
-will be executed via exec_op() handler. Thus, if the hardware supports
-dual/quad spi modes, then corresponding requests will be sent to exec_op()
-handler. Current driver does not support such requests, so error is arrised.
-As result the flash can't be read/write.
-
-This patch adds support of dual and quad wires spi modes to exec_op() handler.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 143 +++++++++++++++++++++++++++-------
- 1 file changed, 117 insertions(+), 26 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 4eb01038404..7cd409ba44a 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -186,6 +186,14 @@
- #define SPI_NAND_OP_RESET			0xff
- #define SPI_NAND_OP_DIE_SELECT			0xc2
- 
-+/* SNAND FIFO commands */
-+#define SNAND_FIFO_TX_BUSWIDTH_SINGLE		0x08
-+#define SNAND_FIFO_TX_BUSWIDTH_DUAL		0x09
-+#define SNAND_FIFO_TX_BUSWIDTH_QUAD		0x0a
-+#define SNAND_FIFO_RX_BUSWIDTH_SINGLE		0x0c
-+#define SNAND_FIFO_RX_BUSWIDTH_DUAL		0x0e
-+#define SNAND_FIFO_RX_BUSWIDTH_QUAD		0x0f
-+
- #define SPI_NAND_CACHE_SIZE			(SZ_4K + SZ_256)
- #define SPI_MAX_TRANSFER_SIZE			511
- 
-@@ -380,10 +388,26 @@ static int airoha_snand_set_mode(struct airoha_snand_priv *priv,
- 	return regmap_write(priv->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
- }
- 
-static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
-				   const u8 *data, int len)
-+static int airoha_snand_write_data(struct airoha_snand_priv *priv,
-+				   const u8 *data, int len, int buswidth)
- {
- 	int i, data_len;
-+	u8 cmd;
-+
-+	switch (buswidth) {
-+	case 0:
-+	case 1:
-+		cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
-+		break;
-+	case 2:
-+		cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
-+		break;
-+	case 4:
-+		cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
- 
- 	for (i = 0; i < len; i += data_len) {
- 		int err;
-@@ -402,16 +426,32 @@ static int airoha_snand_write_data(struct airoha_snand_priv *priv, u8 cmd,
- 	return 0;
- }
- 
-static int airoha_snand_read_data(struct airoha_snand_priv *priv, u8 *data,
-				  int len)
-+static int airoha_snand_read_data(struct airoha_snand_priv *priv,
-+				  u8 *data, int len, int buswidth)
- {
- 	int i, data_len;
-+	u8 cmd;
-+
-+	switch (buswidth) {
-+	case 0:
-+	case 1:
-+		cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
-+		break;
-+	case 2:
-+		cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
-+		break;
-+	case 4:
-+		cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
- 
- 	for (i = 0; i < len; i += data_len) {
- 		int err;
- 
- 		data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
-		err = airoha_snand_set_fifo_op(priv, 0xc, data_len);
-+		err = airoha_snand_set_fifo_op(priv, cmd, data_len);
- 		if (err)
- 			return err;
- 
-@@ -525,6 +565,38 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
- 				  SPI_NFI_CUS_SEC_SIZE, val);
- }
- 
-+static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
-+{
-+	if (op->addr.nbytes != 2)
-+		return false;
-+
-+	if (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&
-+	    op->addr.buswidth != 4)
-+		return false;
-+
-+	switch (op->data.dir) {
-+	case SPI_MEM_DATA_IN:
-+		if (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth > 0xf)
-+			return false;
-+
-+		/* quad in / quad out */
-+		if (op->addr.buswidth == 4)
-+			return op->data.buswidth == 4;
-+
-+		if (op->addr.buswidth == 2)
-+			return op->data.buswidth == 2;
-+
-+		/* standard spi */
-+		return op->data.buswidth == 4 || op->data.buswidth == 2 ||
-+		       op->data.buswidth == 1;
-+	case SPI_MEM_DATA_OUT:
-+		return !op->dummy.nbytes && op->addr.buswidth == 1 &&
-+		       (op->data.buswidth == 4 || op->data.buswidth == 1);
-+	default:
-+		return false;
-+	}
-+}
-+
- static bool airoha_snand_supports_op(struct spi_slave *slave,
- 				     const struct spi_mem_op *op)
- {
-@@ -534,6 +606,9 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
- 	if (op->cmd.buswidth != 1)
- 		return false;
- 
-+	if (airoha_snand_is_page_ops(op))
-+		return true;
-+
- 	return (!op->addr.nbytes || op->addr.buswidth == 1) &&
- 	       (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
- 	       (!op->data.nbytes || op->data.buswidth == 1);
-@@ -542,13 +617,29 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
- static int airoha_snand_exec_op(struct spi_slave *slave,
- 				const struct spi_mem_op *op)
- {
-	u8 data[8], cmd, opcode = op->cmd.opcode;
- 	struct udevice *bus = slave->dev->parent;
- 	struct airoha_snand_priv *priv;
-+	int op_len, addr_len, dummy_len;
-+	u8 buf[20], *data;
- 	int i, err;
- 
- 	priv = dev_get_priv(bus);
- 
-+	op_len = op->cmd.nbytes;
-+	addr_len = op->addr.nbytes;
-+	dummy_len = op->dummy.nbytes;
-+
-+	if (op_len + dummy_len + addr_len > sizeof(buf))
-+		return -EIO;
-+
-+	data = buf;
-+	for (i = 0; i < op_len; i++)
-+		*data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
-+	for (i = 0; i < addr_len; i++)
-+		*data++ = op->addr.val >> (8 * (addr_len - i - 1));
-+	for (i = 0; i < dummy_len; i++)
-+		*data++ = 0xff;
-+
- 	/* switch to manual mode */
- 	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
- 	if (err < 0)
-@@ -559,40 +650,40 @@ static int airoha_snand_exec_op(struct spi_slave *slave,
- 		return err;
- 
- 	/* opcode */
-	err = airoha_snand_write_data(priv, 0x8, &opcode, sizeof(opcode));
-+	data = buf;
-+	err = airoha_snand_write_data(priv, data, op_len,
-+				      op->cmd.buswidth);
- 	if (err)
- 		return err;
- 
- 	/* addr part */
-	cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
-	put_unaligned_be64(op->addr.val, data);
-
-	for (i = ARRAY_SIZE(data) - op->addr.nbytes;
-	     i < ARRAY_SIZE(data); i++) {
-		err = airoha_snand_write_data(priv, cmd, &data[i],
-					      sizeof(data[0]));
-+	data += op_len;
-+	if (addr_len) {
-+		err = airoha_snand_write_data(priv, data, addr_len,
-+					      op->addr.buswidth);
- 		if (err)
- 			return err;
- 	}
- 
- 	/* dummy */
-	data[0] = 0xff;
-	for (i = 0; i < op->dummy.nbytes; i++) {
-		err = airoha_snand_write_data(priv, 0x8, &data[0],
-					      sizeof(data[0]));
-+	data += addr_len;
-+	if (dummy_len) {
-+		err = airoha_snand_write_data(priv, data, dummy_len,
-+					      op->dummy.buswidth);
- 		if (err)
- 			return err;
- 	}
- 
- 	/* data */
-	if (op->data.dir == SPI_MEM_DATA_IN) {
-		err = airoha_snand_read_data(priv, op->data.buf.in,
-					     op->data.nbytes);
-		if (err)
-			return err;
-	} else {
-		err = airoha_snand_write_data(priv, 0x8, op->data.buf.out,
-					      op->data.nbytes);
-+	if (op->data.nbytes) {
-+		if (op->data.dir == SPI_MEM_DATA_IN)
-+			err = airoha_snand_read_data(priv, op->data.buf.in,
-+						     op->data.nbytes,
-+						     op->data.buswidth);
-+		else
-+			err = airoha_snand_write_data(priv, op->data.buf.out,
-+						      op->data.nbytes,
-+						      op->data.buswidth);
- 		if (err)
- 			return err;
- 	}
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/205-spi-airoha-add-dma-support.patch
+++ b/package/boot/uboot-airoha/patches/205-spi-airoha-add-dma-support.patch
@@ -1,378 +0,0 @@
-From f1fe2f174f26eb98af35862caea083439e08a344 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 8 Jun 2025 05:30:22 +0300
-Subject: [PATCH 4/5] spi: airoha: add dma support
-
-This patch speed up cache reading/writing/updating opearions.
-It was tested on en7523/an7581 and some other Airoha chips.
-
-It will speed up
- * page reading/writing without oob
- * page reading/writing with oob
- * oob reading/writing (significant for UBI scanning)
-
-The only know issue appears in a very specific conditions for en7523 family
-chips only.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 309 ++++++++++++++++++++++++++++++++++
- 1 file changed, 309 insertions(+)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 7cd409ba44a..f72d11f5b19 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -141,12 +141,14 @@
- #define SPI_NFI_CUS_SEC_SIZE_EN			BIT(16)
- 
- #define REG_SPI_NFI_RD_CTL2			0x0510
-+
- #define REG_SPI_NFI_RD_CTL3			0x0514
- 
- #define REG_SPI_NFI_PG_CTL1			0x0524
- #define SPI_NFI_PG_LOAD_CMD			GENMASK(15, 8)
- 
- #define REG_SPI_NFI_PG_CTL2			0x0528
-+
- #define REG_SPI_NFI_NOR_PROG_ADDR		0x052c
- #define REG_SPI_NFI_NOR_RD_ADDR			0x0534
- 
-@@ -219,6 +221,8 @@ struct airoha_snand_priv {
- 		u8 sec_num;
- 		u8 spare_size;
- 	} nfi_cfg;
-+
-+	u8 *txrx_buf;
- };
- 
- static int airoha_snand_set_fifo_op(struct airoha_snand_priv *priv,
-@@ -614,6 +618,302 @@ static bool airoha_snand_supports_op(struct spi_slave *slave,
- 	       (!op->data.nbytes || op->data.buswidth == 1);
- }
- 
-+static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
-+{
-+	struct spi_slave *slave = desc->slave;
-+	struct udevice *bus = slave->dev->parent;
-+	struct airoha_snand_priv *priv = dev_get_priv(bus);
-+
-+	if (!priv->txrx_buf)
-+		return -EINVAL;
-+
-+	if (desc->info.offset + desc->info.length > U32_MAX)
-+		return -EINVAL;
-+
-+	if (!airoha_snand_supports_op(desc->slave, &desc->info.op_tmpl))
-+		return -EOPNOTSUPP;
-+
-+	return 0;
-+}
-+
-+static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
-+					u64 offs, size_t len, void *buf)
-+{
-+	struct spi_mem_op *op = &desc->info.op_tmpl;
-+	struct spi_slave *slave = desc->slave;
-+	struct udevice *bus = slave->dev->parent;
-+	struct airoha_snand_priv *priv = dev_get_priv(bus);
-+	u8 *txrx_buf = priv->txrx_buf;
-+	dma_addr_t dma_addr;
-+	u32 val, rd_mode;
-+	int err;
-+
-+	switch (op->cmd.opcode) {
-+	case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
-+		rd_mode = 1;
-+		break;
-+	case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
-+		rd_mode = 2;
-+		break;
-+	default:
-+		rd_mode = 0;
-+		break;
-+	}
-+
-+	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
-+	if (err < 0)
-+		return err;
-+
-+	err = airoha_snand_nfi_config(priv);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
-+				  DMA_FROM_DEVICE);
-+
-+	/* set dma addr */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
-+			   dma_addr);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set cust sec size */
-+	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
-+	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
-+	err = regmap_update_bits(priv->regmap_nfi,
-+				 REG_SPI_NFI_SNF_MISC_CTL2,
-+				 SPI_NFI_READ_DATA_BYTE_NUM, val);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set read command */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
-+			   op->cmd.opcode);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set read mode */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
-+			   FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set read addr: zero page offset + descriptor read offset */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL3,
-+			   desc->info.offset);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set nfi read */
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+				 SPI_NFI_OPMODE,
-+				 FIELD_PREP(SPI_NFI_OPMODE, 6));
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+			      SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* trigger dma reading */
-+	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+				SPI_NFI_RD_TRIG);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+			      SPI_NFI_RD_TRIG);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_read_poll_timeout(priv->regmap_nfi,
-+				       REG_SPI_NFI_SNF_STA_CTL1, val,
-+				       (val & SPI_NFI_READ_FROM_CACHE_DONE),
-+				       0, 1 * MSEC_PER_SEC);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/*
-+	 * SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
-+	 * of dirmap_read operation even if it is already set.
-+	 */
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
-+				 SPI_NFI_READ_FROM_CACHE_DONE,
-+				 SPI_NFI_READ_FROM_CACHE_DONE);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
-+				       val, (val & SPI_NFI_AHB_DONE), 0,
-+				       1 * MSEC_PER_SEC);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* DMA read need delay for data ready from controller to DRAM */
-+	udelay(1);
-+
-+	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
-+
-+	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
-+	if (err < 0)
-+		return err;
-+
-+	memcpy(buf, txrx_buf + offs, len);
-+
-+	return len;
-+
-+error_dma_unmap:
-+	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_FROM_DEVICE);
-+error_dma_mode_off:
-+	airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
-+	return err;
-+}
-+
-+static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
-+					 u64 offs, size_t len, const void *buf)
-+{
-+	struct spi_slave *slave = desc->slave;
-+	struct udevice *bus = slave->dev->parent;
-+	struct airoha_snand_priv *priv = dev_get_priv(bus);
-+	u8 *txrx_buf = priv->txrx_buf;
-+	dma_addr_t dma_addr;
-+	u32 wr_mode, val, opcode;
-+	int err;
-+
-+	opcode = desc->info.op_tmpl.cmd.opcode;
-+	switch (opcode) {
-+	case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
-+	case SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE:
-+		wr_mode = 0;
-+		break;
-+	case SPI_NAND_OP_PROGRAM_LOAD_QUAD:
-+	case SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD:
-+		wr_mode = 2;
-+		break;
-+	default:
-+		/* unknown opcode */
-+		return -EOPNOTSUPP;
-+	}
-+
-+	memcpy(txrx_buf + offs, buf, len);
-+
-+	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
-+	if (err < 0)
-+		return err;
-+
-+	err = airoha_snand_nfi_config(priv);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	dma_addr = dma_map_single(txrx_buf, SPI_NAND_CACHE_SIZE,
-+				  DMA_TO_DEVICE);
-+
-+	/* set dma addr */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_STRADDR,
-+			   dma_addr);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
-+			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
-+	err = regmap_update_bits(priv->regmap_nfi,
-+				 REG_SPI_NFI_SNF_MISC_CTL2,
-+				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set write command */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL1,
-+			   FIELD_PREP(SPI_NFI_PG_LOAD_CMD, opcode));
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set write mode */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
-+			   FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* set write addr: zero page offset + descriptor write offset */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_PG_CTL2,
-+			   desc->info.offset);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+				SPI_NFI_READ_MODE);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+				 SPI_NFI_OPMODE,
-+				 FIELD_PREP(SPI_NFI_OPMODE, 3));
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+			      SPI_NFI_DMA_MODE);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/* trigger dma writing */
-+	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+				SPI_NFI_WR_TRIG);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+			      SPI_NFI_WR_TRIG);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_read_poll_timeout(priv->regmap_nfi, REG_SPI_NFI_INTR,
-+				       val, (val & SPI_NFI_AHB_DONE), 0,
-+				       1 * MSEC_PER_SEC);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	err = regmap_read_poll_timeout(priv->regmap_nfi,
-+				       REG_SPI_NFI_SNF_STA_CTL1, val,
-+				       (val & SPI_NFI_LOAD_TO_CACHE_DONE),
-+				       0, 1 * MSEC_PER_SEC);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	/*
-+	 * SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
-+	 * of dirmap_write operation even if it is already set.
-+	 */
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SNF_STA_CTL1,
-+				 SPI_NFI_LOAD_TO_CACHE_DONE,
-+				 SPI_NFI_LOAD_TO_CACHE_DONE);
-+	if (err)
-+		goto error_dma_unmap;
-+
-+	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
-+
-+	err = airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
-+	if (err < 0)
-+		return err;
-+
-+	return len;
-+
-+error_dma_unmap:
-+	dma_unmap_single(dma_addr, SPI_NAND_CACHE_SIZE, DMA_TO_DEVICE);
-+error_dma_mode_off:
-+	airoha_snand_set_mode(priv, SPI_MODE_MANUAL);
-+	return err;
-+}
-+
- static int airoha_snand_exec_op(struct spi_slave *slave,
- 				const struct spi_mem_op *op)
- {
-@@ -696,6 +996,12 @@ static int airoha_snand_probe(struct udevice *dev)
- 	struct airoha_snand_priv *priv = dev_get_priv(dev);
- 	int ret;
- 
-+	priv->txrx_buf = memalign(ARCH_DMA_MINALIGN, SPI_NAND_CACHE_SIZE);
-+	if (!priv->txrx_buf) {
-+		dev_err(dev, "failed to alloacate memory for dirmap\n");
-+		return -ENOMEM;
-+	}
-+
- 	ret = regmap_init_mem_index(dev_ofnode(dev), &priv->regmap_ctrl, 0);
- 	if (ret) {
- 		dev_err(dev, "failed to init spi ctrl regmap\n");
-@@ -769,6 +1075,9 @@ static int airoha_snand_nfi_setup(struct spi_slave *slave,
- static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
- 	.supports_op = airoha_snand_supports_op,
- 	.exec_op = airoha_snand_exec_op,
-+	.dirmap_create = airoha_snand_dirmap_create,
-+	.dirmap_read = airoha_snand_dirmap_read,
-+	.dirmap_write = airoha_snand_dirmap_write,
- };
- 
- static const struct dm_spi_ops airoha_snfi_spi_ops = {
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/206-spi-airoha-support-of-dualio-quadio-flash-reading-co.patch
+++ b/package/boot/uboot-airoha/patches/206-spi-airoha-support-of-dualio-quadio-flash-reading-co.patch
@@ -1,94 +0,0 @@
-From 2ebbccfa053993d0fe90bee523020a8f796e8988 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Sun, 8 Jun 2025 05:30:22 +0300
-Subject: [PATCH 5/5] spi: airoha: support of dualio/quadio flash reading
- commands
-
-Airoha snfi spi controller supports acceleration of DUAL/QUAD
-operations, but does not supports DUAL_IO/QUAD_IO operations.
-Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
-so we can issue corresponding DUAL/QUAD operation instead of
-DUAL_IO/QUAD_IO one.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 27 +++++++++++++++++++++------
- 1 file changed, 21 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index f72d11f5b19..7cafa900bbc 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -141,6 +141,7 @@
- #define SPI_NFI_CUS_SEC_SIZE_EN			BIT(16)
- 
- #define REG_SPI_NFI_RD_CTL2			0x0510
-+#define SPI_NFI_DATA_READ_CMD			GENMASK(7, 0)
- 
- #define REG_SPI_NFI_RD_CTL3			0x0514
- 
-@@ -175,7 +176,9 @@
- #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE	0x03
- #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST	0x0b
- #define SPI_NAND_OP_READ_FROM_CACHE_DUAL	0x3b
-+#define SPI_NAND_OP_READ_FROM_CACHE_DUALIO	0xbb
- #define SPI_NAND_OP_READ_FROM_CACHE_QUAD	0x6b
-+#define SPI_NAND_OP_READ_FROM_CACHE_QUADIO	0xeb
- #define SPI_NAND_OP_WRITE_ENABLE		0x06
- #define SPI_NAND_OP_WRITE_DISABLE		0x04
- #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE		0x02
-@@ -639,25 +642,37 @@ static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
- static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 					u64 offs, size_t len, void *buf)
- {
-	struct spi_mem_op *op = &desc->info.op_tmpl;
- 	struct spi_slave *slave = desc->slave;
- 	struct udevice *bus = slave->dev->parent;
- 	struct airoha_snand_priv *priv = dev_get_priv(bus);
- 	u8 *txrx_buf = priv->txrx_buf;
- 	dma_addr_t dma_addr;
-	u32 val, rd_mode;
-+	u32 val, rd_mode, opcode;
- 	int err;
- 
-	switch (op->cmd.opcode) {
-+	/*
-+	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
-+	 * replace them with supported opcodes.
-+	 */
-+	opcode = desc->info.op_tmpl.cmd.opcode;
-+	switch (opcode) {
-+	case SPI_NAND_OP_READ_FROM_CACHE_SINGLE:
-+	case SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST:
-+		rd_mode = 0;
-+		break;
- 	case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
-+	case SPI_NAND_OP_READ_FROM_CACHE_DUALIO:
-+		opcode = SPI_NAND_OP_READ_FROM_CACHE_DUAL;
- 		rd_mode = 1;
- 		break;
- 	case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
-+	case SPI_NAND_OP_READ_FROM_CACHE_QUADIO:
-+		opcode = SPI_NAND_OP_READ_FROM_CACHE_QUAD;
- 		rd_mode = 2;
- 		break;
- 	default:
-		rd_mode = 0;
-		break;
-+		/* unknown opcode */
-+		return -EOPNOTSUPP;
- 	}
- 
- 	err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
-@@ -688,7 +703,7 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 
- 	/* set read command */
- 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
-			   op->cmd.opcode);
-+			   FIELD_PREP(SPI_NFI_DATA_READ_CMD, opcode));
- 	if (err)
- 		goto error_dma_unmap;
- 
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/207-spi-airoha-avoid-setting-of-page-oob-sizes-in-REG_SP.patch
+++ b/package/boot/uboot-airoha/patches/207-spi-airoha-avoid-setting-of-page-oob-sizes-in-REG_SP.patch
@@ -1,67 +0,0 @@
-From 073de6579cf8c7599d925852bb0fc7fa50378dd3 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Thu, 14 Aug 2025 18:00:32 +0300
-Subject: [PATCH 1/4] spi: airoha: avoid setting of page/oob sizes in
- REG_SPI_NFI_PAGEFMT
-
-spi-airoha-snfi uses custom sector size in REG_SPI_NFI_SECCUS_SIZE
-register, so setting of page/oob sizes in REG_SPI_NFI_PAGEFMT is not
-required.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 38 -----------------------------------
- 1 file changed, 38 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 7cafa900bbc..71e4fc13924 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -514,44 +514,6 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
- 	if (err)
- 		return err;
- 
-	/* page format */
-	switch (priv->nfi_cfg.spare_size) {
-	case 26:
-		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x1);
-		break;
-	case 27:
-		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x2);
-		break;
-	case 28:
-		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x3);
-		break;
-	default:
-		val = FIELD_PREP(SPI_NFI_SPARE_SIZE, 0x0);
-		break;
-	}
-
-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
-				 SPI_NFI_SPARE_SIZE, val);
-	if (err)
-		return err;
-
-	switch (priv->nfi_cfg.page_size) {
-	case 2048:
-		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x1);
-		break;
-	case 4096:
-		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x2);
-		break;
-	default:
-		val = FIELD_PREP(SPI_NFI_PAGE_SIZE, 0x0);
-		break;
-	}
-
-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_PAGEFMT,
-				 SPI_NFI_PAGE_SIZE, val);
-	if (err)
-		return err;
-
- 	/* sec num */
- 	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/208-spi-airoha-reduce-the-number-of-modification-of-REG_.patch
+++ b/package/boot/uboot-airoha/patches/208-spi-airoha-reduce-the-number-of-modification-of-REG_.patch
@@ -1,200 +0,0 @@
-From 3bd6ca4ddaae4f0a667a9359c8092d2271006687 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Thu, 14 Aug 2025 18:49:34 +0300
-Subject: [PATCH 2/4] spi: airoha: reduce the number of modification of
- REG_SPI_NFI_CNFG and REG_SPI_NFI_SECCUS_SIZE registers
-
-This just reduce the number of modification of REG_SPI_NFI_CNFG and
-REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation.
-
-This patch is a necessary step to avoid usage of flash specific
-parameters.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 134 +++++++++++++++++++++++++---------
- 1 file changed, 101 insertions(+), 33 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 71e4fc13924..1fcf5dd89e9 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -641,7 +641,47 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	if (err < 0)
- 		return err;
- 
-	err = airoha_snand_nfi_config(priv);
-+	/* NFI reset */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
-+			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	/* NFI configure:
-+	 *   - No AutoFDM (custom sector size (SECCUS) register will be used)
-+	 *   - No SoC's hardware ECC (flash internal ECC will be used)
-+	 *   - Use burst mode (faster, but requires 16 byte alignment for addresses)
-+	 *   - Setup for reading (SPI_NFI_READ_MODE)
-+	 *   - Setup reading command: FIELD_PREP(SPI_NFI_OPMODE, 6)
-+	 *   - Use DMA instead of PIO for data reading
-+	 *   - Use AHB bus for DMA transfer
-+	 */
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+				 SPI_NFI_DMA_MODE |
-+				 SPI_NFI_READ_MODE |
-+				 SPI_NFI_DMA_BURST_EN |
-+				 SPI_NFI_HW_ECC_EN |
-+				 SPI_NFI_AUTO_FDM_EN |
-+				 SPI_NFI_OPMODE,
-+				 SPI_NFI_DMA_MODE |
-+				 SPI_NFI_READ_MODE |
-+				 SPI_NFI_DMA_BURST_EN |
-+				 FIELD_PREP(SPI_NFI_OPMODE, 6));
-+
-+	/* Set number of sector will be read */
-+	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+				 SPI_NFI_SEC_NUM, val);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	/* Set custom sector size */
-+	val = priv->nfi_cfg.sec_size;
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
-+				 SPI_NFI_CUS_SEC_SIZE |
-+				 SPI_NFI_CUS_SEC_SIZE_EN,
-+				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
-+				 SPI_NFI_CUS_SEC_SIZE_EN);
- 	if (err)
- 		goto error_dma_mode_off;
- 
-@@ -654,7 +694,14 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	if (err)
- 		goto error_dma_unmap;
- 
-	/* set cust sec size */
-+	/*
-+	 * Setup transfer length
-+	 * ---------------------
-+	 * The following rule MUST be met:
-+	 *     transfer_length =
-+	 *        = NFI_SNF_MISC_CTL2.read_data_byte_number =
-+	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
-+	 */
- 	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
- 	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
- 	err = regmap_update_bits(priv->regmap_nfi,
-@@ -681,18 +728,6 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	if (err)
- 		goto error_dma_unmap;
- 
-	/* set nfi read */
-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-				 SPI_NFI_OPMODE,
-				 FIELD_PREP(SPI_NFI_OPMODE, 6));
-	if (err)
-		goto error_dma_unmap;
-
-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-			      SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
-	if (err)
-		goto error_dma_unmap;
-
- 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
- 	if (err)
- 		goto error_dma_unmap;
-@@ -783,7 +818,48 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	if (err < 0)
- 		return err;
- 
-	err = airoha_snand_nfi_config(priv);
-+	/* NFI reset */
-+	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
-+			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	/*
-+	 * NFI configure:
-+	 *   - No AutoFDM (custom sector size (SECCUS) register will be used)
-+	 *   - No SoC's hardware ECC (flash internal ECC will be used)
-+	 *   - Use burst mode (faster, but requires 16 byte alignment for addresses)
-+	 *   - Setup for writing (SPI_NFI_READ_MODE bit is cleared)
-+	 *   - Setup writing command: FIELD_PREP(SPI_NFI_OPMODE, 3)
-+	 *   - Use DMA instead of PIO for data writing
-+	 */
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-+				 SPI_NFI_DMA_MODE |
-+				 SPI_NFI_READ_MODE |
-+				 SPI_NFI_DMA_BURST_EN |
-+				 SPI_NFI_HW_ECC_EN |
-+				 SPI_NFI_AUTO_FDM_EN |
-+				 SPI_NFI_OPMODE,
-+				 SPI_NFI_DMA_MODE |
-+				 SPI_NFI_DMA_BURST_EN |
-+				 FIELD_PREP(SPI_NFI_OPMODE, 3));
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	/* Set number of sector will be written */
-+	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-+				 SPI_NFI_SEC_NUM, val);
-+	if (err)
-+		goto error_dma_mode_off;
-+
-+	/* Set custom sector size */
-+	val = priv->nfi_cfg.sec_size;
-+	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
-+				 SPI_NFI_CUS_SEC_SIZE |
-+				 SPI_NFI_CUS_SEC_SIZE_EN,
-+				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
-+				 SPI_NFI_CUS_SEC_SIZE_EN);
- 	if (err)
- 		goto error_dma_mode_off;
- 
-@@ -796,8 +872,16 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	if (err)
- 		goto error_dma_unmap;
- 
-	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
-			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
-+	/*
-+	 * Setup transfer length
-+	 * ---------------------
-+	 * The following rule MUST be met:
-+	 *     transfer_length =
-+	 *        = NFI_SNF_MISC_CTL2.write_data_byte_number =
-+	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
-+	 */
-+	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
-+	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
- 	err = regmap_update_bits(priv->regmap_nfi,
- 				 REG_SPI_NFI_SNF_MISC_CTL2,
- 				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
-@@ -822,22 +906,6 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	if (err)
- 		goto error_dma_unmap;
- 
-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-				SPI_NFI_READ_MODE);
-	if (err)
-		goto error_dma_unmap;
-
-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-				 SPI_NFI_OPMODE,
-				 FIELD_PREP(SPI_NFI_OPMODE, 3));
-	if (err)
-		goto error_dma_unmap;
-
-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-			      SPI_NFI_DMA_MODE);
-	if (err)
-		goto error_dma_unmap;
-
- 	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
- 	if (err)
- 		goto error_dma_unmap;
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/209-spi-airoha-set-custom-sector-size-equal-to-flash-pag.patch
+++ b/package/boot/uboot-airoha/patches/209-spi-airoha-set-custom-sector-size-equal-to-flash-pag.patch
@@ -1,140 +0,0 @@
-From 8e6cba428ce48005b5b8be64c2a08c98d04865e9 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Thu, 14 Aug 2025 22:47:17 +0300
-Subject: [PATCH 3/4] spi: airoha: set custom sector size equal to flash page
- size
-
-Set custom sector size equal to flash page size including oob. Thus we
-will always read a single sector. The maximum custom sector size is
-8187, so all possible flash sector sizes are supported.
-
-This patch is a necessary step to avoid usage of flash specific
-parameters.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 35 +++++++++++++++++++----------------
- 1 file changed, 19 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index 1fcf5dd89e9..c9feef83f89 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -515,7 +515,7 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
- 		return err;
- 
- 	/* sec num */
-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
-+	val = FIELD_PREP(SPI_NFI_SEC_NUM, 1);
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
- 				 SPI_NFI_SEC_NUM, val);
- 	if (err)
-@@ -528,7 +528,8 @@ static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
- 		return err;
- 
- 	/* set cust sec size */
-	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, priv->nfi_cfg.sec_size);
-+	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE,
-+			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
- 	return regmap_update_bits(priv->regmap_nfi,
- 				  REG_SPI_NFI_SECCUS_SIZE,
- 				  SPI_NFI_CUS_SEC_SIZE, val);
-@@ -610,8 +611,11 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	u8 *txrx_buf = priv->txrx_buf;
- 	dma_addr_t dma_addr;
- 	u32 val, rd_mode, opcode;
-+	size_t bytes;
- 	int err;
- 
-+	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
-+
- 	/*
- 	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
- 	 * replace them with supported opcodes.
-@@ -669,18 +673,17 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 				 FIELD_PREP(SPI_NFI_OPMODE, 6));
- 
- 	/* Set number of sector will be read */
-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-				 SPI_NFI_SEC_NUM, val);
-+				 SPI_NFI_SEC_NUM,
-+				 FIELD_PREP(SPI_NFI_SEC_NUM, 1));
- 	if (err)
- 		goto error_dma_mode_off;
- 
- 	/* Set custom sector size */
-	val = priv->nfi_cfg.sec_size;
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
- 				 SPI_NFI_CUS_SEC_SIZE |
- 				 SPI_NFI_CUS_SEC_SIZE_EN,
-				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
-+				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, bytes) |
- 				 SPI_NFI_CUS_SEC_SIZE_EN);
- 	if (err)
- 		goto error_dma_mode_off;
-@@ -702,11 +705,10 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	 *        = NFI_SNF_MISC_CTL2.read_data_byte_number =
- 	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
- 	 */
-	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
-	val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
- 	err = regmap_update_bits(priv->regmap_nfi,
- 				 REG_SPI_NFI_SNF_MISC_CTL2,
-				 SPI_NFI_READ_DATA_BYTE_NUM, val);
-+				 SPI_NFI_READ_DATA_BYTE_NUM,
-+				 FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, bytes));
- 	if (err)
- 		goto error_dma_unmap;
- 
-@@ -795,8 +797,11 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	u8 *txrx_buf = priv->txrx_buf;
- 	dma_addr_t dma_addr;
- 	u32 wr_mode, val, opcode;
-+	size_t bytes;
- 	int err;
- 
-+	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
-+
- 	opcode = desc->info.op_tmpl.cmd.opcode;
- 	switch (opcode) {
- 	case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
-@@ -847,18 +852,17 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 		goto error_dma_mode_off;
- 
- 	/* Set number of sector will be written */
-	val = FIELD_PREP(SPI_NFI_SEC_NUM, priv->nfi_cfg.sec_num);
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-				 SPI_NFI_SEC_NUM, val);
-+				 SPI_NFI_SEC_NUM,
-+				 FIELD_PREP(SPI_NFI_SEC_NUM, 1));
- 	if (err)
- 		goto error_dma_mode_off;
- 
- 	/* Set custom sector size */
-	val = priv->nfi_cfg.sec_size;
- 	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
- 				 SPI_NFI_CUS_SEC_SIZE |
- 				 SPI_NFI_CUS_SEC_SIZE_EN,
-				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
-+				 FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, bytes) |
- 				 SPI_NFI_CUS_SEC_SIZE_EN);
- 	if (err)
- 		goto error_dma_mode_off;
-@@ -880,11 +884,10 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	 *        = NFI_SNF_MISC_CTL2.write_data_byte_number =
- 	 *        = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
- 	 */
-	val = priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num;
-	val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
- 	err = regmap_update_bits(priv->regmap_nfi,
- 				 REG_SPI_NFI_SNF_MISC_CTL2,
-				 SPI_NFI_PROG_LOAD_BYTE_NUM, val);
-+				 SPI_NFI_PROG_LOAD_BYTE_NUM,
-+				 FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, bytes));
- 	if (err)
- 		goto error_dma_unmap;
- 
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/210-spi-airoha-avoid-usage-of-flash-specific-parameters.patch
+++ b/package/boot/uboot-airoha/patches/210-spi-airoha-avoid-usage-of-flash-specific-parameters.patch
@@ -1,175 +0,0 @@
-From f015b0211a36bf818023c82ab44644631987d23c Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Thu, 14 Aug 2025 23:56:24 +0300
-Subject: [PATCH 4/4] spi: airoha: avoid usage of flash specific parameters
-
-The spinand driver do 3 type of dirmap requests:
- * read/write whole flash page without oob
-   (offs = 0, len = page_size)
- * read/write whole flash page including oob
-   (offs = 0, len = page_size + oob_size)
- * read/write oob area only
-   (offs = page_size, len = oob_size)
-
-The trick is:
- * read/write a single "sector"
- * set a custom sector size equal to offs + len. It's a bit safer to
-   round up "sector size" value 64.
- * set the transfer length equal to custom sector size
-
-And it works!
-
-Thus we can find all data directly from dirmap request, so flash specific
-parameters is not needed anymore. Also
- * airoha_snand_nfi_config(),
- * airoha_snand_nfi_setup()
-functions becomes unnecessary.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/spi/airoha_snfi_spi.c | 94 ++---------------------------------
- 1 file changed, 4 insertions(+), 90 deletions(-)
-
-diff --git a/drivers/spi/airoha_snfi_spi.c b/drivers/spi/airoha_snfi_spi.c
-index c9feef83f89..37fee0c6655 100644
--- a/drivers/spi/airoha_snfi_spi.c
-+++ b/drivers/spi/airoha_snfi_spi.c
-@@ -218,13 +218,6 @@ struct airoha_snand_priv {
- 	struct regmap *regmap_nfi;
- 	struct clk *spi_clk;
- 
-	struct {
-		size_t page_size;
-		size_t sec_size;
-		u8 sec_num;
-		u8 spare_size;
-	} nfi_cfg;
-
- 	u8 *txrx_buf;
- };
- 
-@@ -486,55 +479,6 @@ static int airoha_snand_nfi_init(struct airoha_snand_priv *priv)
- 				  SPI_NFI_ALL_IRQ_EN, SPI_NFI_AHB_DONE_EN);
- }
- 
-static int airoha_snand_nfi_config(struct airoha_snand_priv *priv)
-{
-	int err;
-	u32 val;
-
-	err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_CON,
-			   SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
-	if (err)
-		return err;
-
-	/* auto FDM */
-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-				SPI_NFI_AUTO_FDM_EN);
-	if (err)
-		return err;
-
-	/* HW ECC */
-	err = regmap_clear_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-				SPI_NFI_HW_ECC_EN);
-	if (err)
-		return err;
-
-	/* DMA Burst */
-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_CNFG,
-			      SPI_NFI_DMA_BURST_EN);
-	if (err)
-		return err;
-
-	/* sec num */
-	val = FIELD_PREP(SPI_NFI_SEC_NUM, 1);
-	err = regmap_update_bits(priv->regmap_nfi, REG_SPI_NFI_CON,
-				 SPI_NFI_SEC_NUM, val);
-	if (err)
-		return err;
-
-	/* enable cust sec size */
-	err = regmap_set_bits(priv->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
-			      SPI_NFI_CUS_SEC_SIZE_EN);
-	if (err)
-		return err;
-
-	/* set cust sec size */
-	val = FIELD_PREP(SPI_NFI_CUS_SEC_SIZE,
-			 priv->nfi_cfg.sec_size * priv->nfi_cfg.sec_num);
-	return regmap_update_bits(priv->regmap_nfi,
-				  REG_SPI_NFI_SECCUS_SIZE,
-				  SPI_NFI_CUS_SEC_SIZE, val);
-}
-
- static bool airoha_snand_is_page_ops(const struct spi_mem_op *op)
- {
- 	if (op->addr.nbytes != 2)
-@@ -614,7 +558,8 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
- 	size_t bytes;
- 	int err;
- 
-	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
-+	/* minimum oob size is 64 */
-+	bytes = round_up(offs + len, 64);
- 
- 	/*
- 	 * DUALIO and QUADIO opcodes are not supported by the spi controller,
-@@ -800,7 +745,8 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
- 	size_t bytes;
- 	int err;
- 
-	bytes = priv->nfi_cfg.sec_num * priv->nfi_cfg.sec_size;
-+	/* minimum oob size is 64 */
-+	bytes = round_up(offs + len, 64);
- 
- 	opcode = desc->info.op_tmpl.cmd.opcode;
- 	switch (opcode) {
-@@ -1089,37 +1035,6 @@ static int airoha_snand_nfi_set_mode(struct udevice *bus, uint mode)
- 	return 0;
- }
- 
-static int airoha_snand_nfi_setup(struct spi_slave *slave,
-				  const struct spinand_info *spinand_info)
-{
-	struct udevice *bus = slave->dev->parent;
-	struct airoha_snand_priv *priv;
-	u32 sec_size, sec_num;
-	int pagesize, oobsize;
-
-	priv = dev_get_priv(bus);
-
-	pagesize = spinand_info->memorg.pagesize;
-	oobsize = spinand_info->memorg.oobsize;
-
-	if (pagesize == 2 * 1024)
-		sec_num = 4;
-	else if (pagesize == 4 * 1024)
-		sec_num = 8;
-	else
-		sec_num = 1;
-
-	sec_size = (pagesize + oobsize) / sec_num;
-
-	/* init default value */
-	priv->nfi_cfg.sec_size = sec_size;
-	priv->nfi_cfg.sec_num = sec_num;
-	priv->nfi_cfg.page_size = round_down(sec_size * sec_num, 1024);
-	priv->nfi_cfg.spare_size = 16;
-
-	return airoha_snand_nfi_config(priv);
-}
-
- static const struct spi_controller_mem_ops airoha_snand_mem_ops = {
- 	.supports_op = airoha_snand_supports_op,
- 	.exec_op = airoha_snand_exec_op,
-@@ -1132,7 +1047,6 @@ static const struct dm_spi_ops airoha_snfi_spi_ops = {
- 	.mem_ops = &airoha_snand_mem_ops,
- 	.set_speed = airoha_snand_nfi_set_speed,
- 	.set_mode = airoha_snand_nfi_set_mode,
-	.setup_for_spinand = airoha_snand_nfi_setup,
- };
- 
- static const struct udevice_id airoha_snand_ids[] = {
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch
+++ b/package/boot/uboot-airoha/patches/300-airoha-add-support-for-Airoha-AN7583-SoC.patch
@@ -1,729 +0,0 @@
-From 0ee8053a17e6f4d6dbde0828e775309cba38c171 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 29 Apr 2025 13:06:59 +0200
-Subject: [PATCH 1/3] airoha: add support for Airoha AN7583 SoC
-
-Add support for Airoha AN7583 SoC. This adds the Kconfig and Makefile
-entry for the SoC, DTSI and initial config for it. Also add the code for
-CPU and RAM initialization. Everything is mostly based on AN7581 that
-share lots of common piece.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- arch/arm/dts/an7583-evb.dts          |  67 +++++
- arch/arm/dts/an7583.dtsi             | 387 +++++++++++++++++++++++++++
- arch/arm/mach-airoha/Kconfig         |  14 +
- arch/arm/mach-airoha/Makefile        |   1 +
- arch/arm/mach-airoha/an7583/Makefile |   3 +
- arch/arm/mach-airoha/an7583/init.c   |  47 ++++
- board/airoha/an7583/MAINTAINERS      |   5 +
- board/airoha/an7583/Makefile         |   3 +
- board/airoha/an7583/an7583_rfb.c     |  16 ++
- configs/an7583_evb_defconfig         |  83 ++++++
- include/configs/an7583.h             |  19 ++
- 11 files changed, 645 insertions(+)
- create mode 100644 arch/arm/dts/an7583-evb.dts
- create mode 100644 arch/arm/dts/an7583.dtsi
- create mode 100644 arch/arm/mach-airoha/an7583/Makefile
- create mode 100644 arch/arm/mach-airoha/an7583/init.c
- create mode 100644 board/airoha/an7583/MAINTAINERS
- create mode 100644 board/airoha/an7583/Makefile
- create mode 100644 board/airoha/an7583/an7583_rfb.c
- create mode 100644 configs/an7583_evb_defconfig
- create mode 100644 include/configs/an7583.h
-
--- /dev/null
-+++ b/arch/arm/dts/an7583-evb.dts
-@@ -0,0 +1,67 @@
-+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+/dts-v1/;
-+
-+/* Bootloader installs ATF here */
-+/memreserve/ 0x80000000 0x200000;
-+
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include "an7583.dtsi"
-+
-+/ {
-+	model = "Airoha AN7583 Evaluation Board";
-+	compatible = "airoha,an7583-evb", "airoha,an7583", "airoha,en7583";
-+
-+	aliases {
-+		serial0 = &uart1;
-+	};
-+
-+	chosen {
-+		bootargs = "console=ttyS0,115200 earlycon";
-+		stdout-path = "serial0:115200n8";
-+		linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
-+	};
-+
-+	/* When running as a first-stage bootloader this isn't filled in automatically */
-+	memory@80000000 {
-+		device_type = "memory";
-+		reg = <0x0 0x80000000 0x0 0x20000000>;
-+	};
-+};
-+
-+&an7583_pinctrl {
-+	pcie0_rst_pins: pcie0-rst-pins {
-+		conf {
-+			pins = "pcie_reset0";
-+			drive-open-drain = <1>;
-+		};
-+	};
-+
-+	pcie1_rst_pins: pcie1-rst-pins {
-+		conf {
-+			pins = "pcie_reset1";
-+			drive-open-drain = <1>;
-+		};
-+	};
-+};
-+
-+&pcie0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie0_rst_pins>;
-+	status = "okay";
-+};
-+
-+&pcie1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&pcie1_rst_pins>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+};
-+
-+&snfi {
-+	status = "okay";
-+};
--- /dev/null
-+++ b/arch/arm/dts/an7583.dtsi
-@@ -0,0 +1,387 @@
-+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/en7523-clk.h>
-+#include <dt-bindings/reset/airoha,an7583-reset.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/thermal/thermal.h>
-+
-+/ {
-+	interrupt-parent = <&gic>;
-+	#address-cells = <2>;
-+	#size-cells = <2>;
-+
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		atf-reserved-memory@80000000 {
-+			no-map;
-+			reg = <0x0 0x80000000 0x0 0x40000>;
-+		};
-+
-+		npu-binary@84000000 {
-+			no-map;
-+			reg = <0x0 0x84000000 0x0 0xa00000>;
-+		};
-+
-+		npu-flag@84b0000 {
-+			no-map;
-+			reg = <0x0 0x84b00000 0x0 0x100000>;
-+		};
-+
-+		npu-pkt@85000000 {
-+			no-map;
-+			reg = <0x0 0x85000000 0x0 0x1a00000>;
-+		};
-+
-+		npu-phyaddr@86b00000 {
-+			no-map;
-+			reg = <0x0 0x86b00000 0x0 0x100000>;
-+		};
-+
-+		npu-rxdesc@86d00000 {
-+			no-map;
-+			reg = <0x0 0x86d00000 0x0 0x100000>;
-+		};
-+	};
-+
-+	psci {
-+		compatible = "arm,psci-1.0";
-+		method = "smc";
-+	};
-+
-+	cpus {
-+		#address-cells = <1>;
-+		#size-cells = <0>;
-+
-+		cpu-map {
-+			cluster0 {
-+				core0 {
-+					cpu = <&cpu0>;
-+				};
-+
-+				core1 {
-+					cpu = <&cpu1>;
-+				};
-+			};
-+		};
-+
-+		cpu0: cpu@0 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x0>;
-+			enable-method = "psci";
-+			next-level-cache = <&l2>;
-+			#cooling-cells = <2>;
-+		};
-+
-+		cpu1: cpu@1 {
-+			device_type = "cpu";
-+			compatible = "arm,cortex-a53";
-+			reg = <0x1>;
-+			enable-method = "psci";
-+			next-level-cache = <&l2>;
-+			#cooling-cells = <2>;
-+		};
-+
-+		l2: l2-cache {
-+			compatible = "cache";
-+			cache-size = <0x80000>;
-+			cache-line-size = <64>;
-+			cache-level = <2>;
-+			cache-unified;
-+		};
-+	};
-+
-+	timer {
-+		compatible = "arm,armv8-timer";
-+		interrupt-parent = <&gic>;
-+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-+	};
-+
-+	soc {
-+		compatible = "simple-bus";
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		gic: interrupt-controller@9000000 {
-+			compatible = "arm,gic-v3";
-+			interrupt-controller;
-+			#interrupt-cells = <3>;
-+			#address-cells = <1>;
-+			#size-cells = <1>;
-+			reg = <0x0 0x09000000 0x0 0x20000>,
-+			      <0x0 0x09080000 0x0 0x80000>,
-+			      <0x0 0x09400000 0x0 0x2000>,
-+			      <0x0 0x09500000 0x0 0x2000>,
-+			      <0x0 0x09600000 0x0 0x20000>;
-+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
-+		};
-+
-+		chip_scu: syscon@1fa20000 {
-+			compatible = "airoha,en7581-chip-scu", "syscon";
-+			reg = <0x0 0x1fa20000 0x0 0x388>;
-+		};
-+
-+		syscon@1fbe3400 {
-+			compatible = "airoha,en7581-pbus-csr", "syscon";
-+			reg = <0x0 0x1fbe3400 0x0 0xff>;
-+		};
-+
-+		system-controller@1fa20000 {
-+			compatible = "syscon", "simple-mfd";
-+			reg = <0x0 0x1fb00000 0x0 0x970>;
-+
-+			scuclk: scuclk {
-+				compatible = "airoha,an7583-scu";
-+				#clock-cells = <1>;
-+				#reset-cells = <1>;
-+			};
-+
-+			mdio_0: mdio-0 {
-+				compatible = "airoha,an7583-mdio";
-+				resets = <&scuclk AN7583_MDIO0>;
-+
-+				airoha,bus-id = <0>;
-+			};
-+
-+			mdio_1: mdio-1 {
-+				compatible = "airoha,an7583-mdio";
-+				resets = <&scuclk AN7583_MDIO1>;
-+
-+				airoha,bus-id = <1>;
-+			};
-+		};
-+
-+		system-controller@1fbf0200 {
-+			compatible = "syscon", "simple-mfd";
-+			reg = <0x0 0x1fbf0200 0x0 0xc0>;
-+
-+			an7583_pinctrl: pinctrl {
-+				compatible = "airoha,en7583-pinctrl";
-+
-+				interrupt-parent = <&gic>;
-+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-+
-+				gpio-controller;
-+				#gpio-cells = <2>;
-+
-+				interrupt-controller;
-+				#interrupt-cells = <2>;
-+			};
-+		};
-+
-+		i2cclock: i2cclock@0 {
-+			#clock-cells = <0>;
-+			compatible = "fixed-clock";
-+
-+			/* 20 MHz */
-+			clock-frequency = <20000000>;
-+		};
-+
-+		i2c0: i2c0@1fbf8000 {
-+			compatible = "mediatek,mt7621-i2c";
-+			reg = <0x0 0x1fbf8000 0x0 0x100>;
-+
-+			clocks = <&i2cclock>;
-+
-+			/* 100 kHz */
-+			clock-frequency = <100000>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "disable";
-+		};
-+
-+		i2c1: i2c1@1fbf8100 {
-+			compatible = "mediatek,mt7621-i2c";
-+			reg = <0x0 0x1fbf8100 0x0 0x100>;
-+
-+			clocks = <&i2cclock>;
-+
-+			/* 100 kHz */
-+			clock-frequency = <100000>;
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "disable";
-+		};
-+
-+		snfi: spi@1fa10000 {
-+			compatible = "airoha,en7581-snand";
-+			reg = <0x0 0x1fa10000 0x0 0x140>,
-+			      <0x0 0x1fa11000 0x0 0x600>;
-+
-+			clocks = <&scuclk EN7523_CLK_SPI>;
-+			clock-names = "spi";
-+
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			status = "disabled";
-+
-+			spi_nand: nand@0 {
-+				compatible = "spi-nand";
-+				reg = <0>;
-+				spi-max-frequency = <50000000>;
-+				spi-tx-bus-width = <1>;
-+				spi-rx-bus-width = <2>;
-+			};
-+		};
-+
-+		uart1: serial@1fbf0000 {
-+			compatible = "ns16550";
-+			reg = <0x0 0x1fbf0000 0x0 0x30>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-frequency = <1843200>;
-+			bootph-all;
-+		};
-+
-+		uart2: serial@1fbf0300 {
-+			compatible = "airoha,en7523-uart";
-+			reg = <0x0 0x1fbf0300 0x0 0x30>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-frequency = <7372800>;
-+
-+			status = "disabled";
-+		};
-+
-+		hsuart3: serial@1fbe1000 {
-+			compatible = "airoha,en7523-uart";
-+			reg = <0x0 0x1fbe1000 0x0 0x40>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-frequency = <7372800>;
-+
-+			status = "disabled";
-+		};
-+
-+		uart4: serial@1fbf0600 {
-+			compatible = "airoha,en7523-uart";
-+			reg = <0x0 0x1fbf0600 0x0 0x30>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-frequency = <7372800>;
-+
-+			status = "disabled";
-+		};
-+
-+		uart5: serial@1fbf0700 {
-+			compatible = "airoha,en7523-uart";
-+			reg = <0x0 0x1fbf0700 0x0 0x30>;
-+			reg-io-width = <4>;
-+			reg-shift = <2>;
-+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+			clock-frequency = <7372800>;
-+
-+			status = "disabled";
-+		};
-+
-+		pciephy: phy@1fa5a000 {
-+			compatible = "airoha,en7581-pcie-phy";
-+			reg = <0x0 0x1fa5a000 0x0 0xfff>,
-+			      <0x0 0x1fa5b000 0x0 0xfff>,
-+			      <0x0 0x1fa5c000 0x0 0xfff>,
-+			      <0x0 0x1fc10044 0x0 0x4>,
-+			      <0x0 0x1fc30044 0x0 0x4>,
-+			      <0x0 0x1fc15030 0x0 0x104>;
-+			reg-names = "csr-2l", "pma0", "pma1",
-+				    "p0-xr-dtime", "p1-xr-dtime",
-+				    "rx-aeq";
-+			#phy-cells = <0>;
-+		};
-+
-+		pcie0: pcie@1fc00000 {
-+			compatible = "airoha,an7583-pcie";
-+			device_type = "pci";
-+			linux,pci-domain = <0>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+
-+			reg = <0x0 0x1fc20000 0x0 0x1670>;
-+			reg-names = "pcie-mac";
-+
-+			clocks = <&scuclk EN7523_CLK_PCIE>;
-+			clock-names = "sys-ck";
-+
-+			phys = <&pciephy>;
-+			phy-names = "pcie-phy";
-+
-+			ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
-+
-+			resets = <&scuclk AN7583_PCIE0_RST>,
-+				 <&scuclk AN7583_PCIE1_RST>;
-+			reset-names = "phy-lane0", "phy-lane1";
-+
-+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-+			bus-range = <0x00 0xff>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
-+					<0 0 0 2 &pcie_intc0 1>,
-+					<0 0 0 3 &pcie_intc0 2>,
-+					<0 0 0 4 &pcie_intc0 3>;
-+
-+			status = "disabled";
-+
-+			pcie_intc0: interrupt-controller {
-+				interrupt-controller;
-+				#address-cells = <0>;
-+				#interrupt-cells = <1>;
-+			};
-+		};
-+
-+		pcie1: pcie@1fc20000 {
-+			compatible = "airoha,an7583-pcie";
-+			device_type = "pci";
-+			linux,pci-domain = <1>;
-+			#address-cells = <3>;
-+			#size-cells = <2>;
-+
-+			reg = <0x0 0x1fa92000 0x0 0x1670>;
-+			reg-names = "pcie-mac";
-+
-+			clocks = <&scuclk EN7523_CLK_PCIE>;
-+			clock-names = "sys-ck";
-+
-+			phys = <&pciephy>;
-+			phy-names = "pcie-phy";
-+
-+			ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
-+
-+			resets = <&scuclk AN7583_PCIE0_RST>,
-+				 <&scuclk AN7583_PCIE1_RST>;
-+			reset-names = "phy-lane0", "phy-lane1";
-+
-+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-+			bus-range = <0x00 0xff>;
-+			#interrupt-cells = <1>;
-+			interrupt-map-mask = <0 0 0 7>;
-+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
-+					<0 0 0 2 &pcie_intc1 1>,
-+					<0 0 0 3 &pcie_intc1 2>,
-+					<0 0 0 4 &pcie_intc1 3>;
-+
-+			status = "disabled";
-+
-+			pcie_intc1: interrupt-controller {
-+				interrupt-controller;
-+				#address-cells = <0>;
-+				#interrupt-cells = <1>;
-+			};
-+		};
-+	};
-+};
--- a/arch/arm/mach-airoha/Kconfig
-+++ b/arch/arm/mach-airoha/Kconfig
-@@ -17,16 +17,30 @@ config TARGET_AN7581
- 	  Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
- 	  I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
- 
-+config TARGET_AN7583
-+	bool "Airoha AN7583 SoC"
-+	select ARM64
-+	help
-+	  The Airoha AN7583 is a ARM-based SoC with a quad-core Cortex-A7
-+	  including NEON and GPU, Mali-450 graphics, several DDR3 options,
-+	  crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
-+	  video interfaces supporting HDMI and MIPI, and video codec support.
-+	  Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
-+	  I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
-+
- endchoice
- 
- config SYS_SOC
- 	default "an7581" if TARGET_AN7581
-+	default "an7583" if TARGET_AN7583
- 
- config SYS_BOARD
- 	default "an7581" if TARGET_AN7581
-+	default "an7583" if TARGET_AN7583
- 
- config SYS_CONFIG_NAME
- 	default "an7581" if TARGET_AN7581
-+	default "an7583" if TARGET_AN7583
- 
- endif
- 
--- a/arch/arm/mach-airoha/Makefile
-+++ b/arch/arm/mach-airoha/Makefile
-@@ -3,3 +3,4 @@
- obj-y	+= cpu.o
- 
- obj-$(CONFIG_TARGET_AN7581) += an7581/
-+obj-$(CONFIG_TARGET_AN7583) += an7583/
--- /dev/null
-+++ b/arch/arm/mach-airoha/an7583/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y += init.o
--- /dev/null
-+++ b/arch/arm/mach-airoha/an7583/init.c
-@@ -0,0 +1,47 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <fdtdec.h>
-+#include <init.h>
-+#include <asm/armv8/mmu.h>
-+#include <asm/system.h>
-+
-+int print_cpuinfo(void)
-+{
-+	printf("CPU:   Airoha AN7583\n");
-+	return 0;
-+}
-+
-+int dram_init(void)
-+{
-+	return fdtdec_setup_mem_size_base();
-+}
-+
-+int dram_init_banksize(void)
-+{
-+	return fdtdec_setup_memory_banksize();
-+}
-+
-+void reset_cpu(ulong addr)
-+{
-+	psci_system_reset();
-+}
-+
-+static struct mm_region an7583_mem_map[] = {
-+	{
-+		/* DDR */
-+		.virt = 0x80000000UL,
-+		.phys = 0x80000000UL,
-+		.size = 0x80000000UL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
-+	}, {
-+		.virt = 0x00000000UL,
-+		.phys = 0x00000000UL,
-+		.size = 0x20000000UL,
-+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
-+			 PTE_BLOCK_NON_SHARE |
-+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-+	}, {
-+		0,
-+	}
-+};
-+struct mm_region *mem_map = an7583_mem_map;
--- /dev/null
-+++ b/board/airoha/an7583/MAINTAINERS
-@@ -0,0 +1,5 @@
-+AN7581
-+M:	Christian Marangi <ansuelsmth@gmail.com>
-+S:	Maintained
-+N:      airoha
-+N:      an7583
--- /dev/null
-+++ b/board/airoha/an7583/Makefile
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier:	GPL-2.0
-+
-+obj-y	+= an7583_rfb.o
--- /dev/null
-+++ b/board/airoha/an7583/an7583_rfb.c
-@@ -0,0 +1,16 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Author: Christian Marangi <ansuelsmth@gmail.com>
-+ */
-+
-+#include <asm/global_data.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int board_init(void)
-+{
-+	/* address of boot parameters */
-+	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
-+
-+	return 0;
-+}
--- /dev/null
-+++ b/configs/an7583_evb_defconfig
-@@ -0,0 +1,81 @@
-+CONFIG_ARM=y
-+CONFIG_ARCH_AIROHA=y
-+CONFIG_TARGET_AN7583=y
-+CONFIG_TEXT_BASE=0x81E00000
-+CONFIG_SYS_MALLOC_F_LEN=0x4000
-+CONFIG_NR_DRAM_BANKS=1
-+CONFIG_ENV_SIZE=0x4000
-+CONFIG_ENV_OFFSET=0x7c000
-+CONFIG_DM_GPIO=y
-+CONFIG_DEFAULT_DEVICE_TREE="an7583-evb"
-+CONFIG_DM_RESET=y
-+CONFIG_SYS_LOAD_ADDR=0x81800000
-+CONFIG_BUILD_TARGET="u-boot.bin"
-+# CONFIG_EFI_LOADER is not set
-+CONFIG_FIT=y
-+CONFIG_FIT_VERBOSE=y
-+CONFIG_BOOTDELAY=3
-+CONFIG_DEFAULT_FDT_FILE="an7583-evb"
-+CONFIG_SYS_PBSIZE=1049
-+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-+# CONFIG_DISPLAY_BOARDINFO is not set
-+CONFIG_HUSH_PARSER=y
-+CONFIG_SYS_PROMPT="U-Boot> "
-+CONFIG_SYS_MAXARGS=8
-+CONFIG_CMD_BOOTZ=y
-+CONFIG_CMD_BOOTMENU=y
-+# CONFIG_CMD_ELF is not set
-+# CONFIG_CMD_XIMG is not set
-+CONFIG_CMD_BIND=y
-+CONFIG_CMD_GPIO=y
-+CONFIG_CMD_MMC=y
-+CONFIG_CMD_MTD=y
-+CONFIG_CMD_SF_TEST=y
-+CONFIG_CMD_SPI=y
-+# CONFIG_CMD_SETEXPR is not set
-+CONFIG_CMD_PING=y
-+CONFIG_CMD_EXT4=y
-+CONFIG_CMD_FAT=y
-+CONFIG_CMD_FS_GENERIC=y
-+CONFIG_CMD_MTDPARTS=y
-+CONFIG_CMD_LOG=y
-+CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-+CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_REGMAP=y
-+CONFIG_SYSCON=y
-+CONFIG_CLK=y
-+CONFIG_DMA=y
-+CONFIG_LED=y
-+CONFIG_LED_GPIO=y
-+CONFIG_MMC_HS200_SUPPORT=y
-+CONFIG_MTD=y
-+CONFIG_DM_MTD=y
-+CONFIG_MTD_SPI_NAND=y
-+CONFIG_DM_SPI_FLASH=y
-+CONFIG_SPI_FLASH_EON=y
-+CONFIG_SPI_FLASH_GIGADEVICE=y
-+CONFIG_SPI_FLASH_ISSI=y
-+CONFIG_SPI_FLASH_MACRONIX=y
-+CONFIG_SPI_FLASH_SPANSION=y
-+CONFIG_SPI_FLASH_STMICRO=y
-+CONFIG_SPI_FLASH_WINBOND=y
-+CONFIG_SPI_FLASH_MTD=y
-+CONFIG_PHYLIB=y
-+CONFIG_PHY=y
-+CONFIG_PINCTRL=y
-+CONFIG_PINCONF=y
-+CONFIG_POWER_DOMAIN=y
-+CONFIG_DM_REGULATOR=y
-+CONFIG_DM_REGULATOR_FIXED=y
-+CONFIG_RAM=y
-+CONFIG_DM_SERIAL=y
-+CONFIG_SYS_NS16550=y
-+CONFIG_SPI=y
-+CONFIG_DM_SPI=y
-+CONFIG_SHA512=y
-+CONFIG_AIROHA_ETH=y
-+CONFIG_MMC_MTK=y
-+CONFIG_AIROHA_SNFI_SPI=y
--- /dev/null
-+++ b/include/configs/an7583.h
-@@ -0,0 +1,19 @@
-+/* SPDX-License-Identifier: GPL-2.0 */
-+/*
-+ * Configuration for Airoha AN7583
-+ */
-+
-+#ifndef __AN7583_H
-+#define __AN7583_H
-+
-+#include <linux/sizes.h>
-+
-+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
-+
-+#define CFG_SYS_INIT_RAM_ADDR           CONFIG_TEXT_BASE
-+#define CFG_SYS_INIT_RAM_SIZE           SZ_2M
-+
-+/* DRAM */
-+#define CFG_SYS_SDRAM_BASE		0x80000000
-+
-+#endif
--- a/package/boot/uboot-airoha/patches/301-clk-airoha-add-support-for-Airoha-AN7583-SoC-clock.patch
+++ b/package/boot/uboot-airoha/patches/301-clk-airoha-add-support-for-Airoha-AN7583-SoC-clock.patch
@@ -1,171 +0,0 @@
-From 62ab067847b30d73d4f661bdc99e9f32ff03f338 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 29 Apr 2025 13:19:11 +0200
-Subject: [PATCH] clk: airoha: add support for Airoha AN7583 SoC clock
-
-Add support for Airoha AN7583 SoC clock that implement more base values
-for clocks compared to AN7581.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- drivers/clk/airoha/clk-airoha.c | 131 ++++++++++++++++++++++++++++++++
- 1 file changed, 131 insertions(+)
-
--- a/drivers/clk/airoha/clk-airoha.c
-+++ b/drivers/clk/airoha/clk-airoha.c
-@@ -73,6 +73,14 @@ static const u32 bus7581_base[] = { 6000
- static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
- static const u32 crypto_base[] = { 540000000, 480000000 };
- static const u32 emmc7581_base[] = { 200000000, 150000000 };
-+/* AN7583 */
-+static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
-+static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
-+static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
-+static const u32 spi7583_base[] = { 100000000, 12500000 };
-+static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
-+static const u32 crypto7583_base[] = { 540672000, 400000000 };
-+static const u32 emmc7583_base[] = { 150000000, 200000000 };
- 
- static const struct airoha_clk_desc en7581_base_clks[EN7581_MAX_CLKS] = {
- 	[EN7523_CLK_GSW] = {
-@@ -186,6 +194,121 @@ static const struct airoha_clk_desc en75
- 	}
- };
- 
-+static const struct airoha_clk_desc an7583_base_clks[EN7581_MAX_CLKS] = {
-+	[EN7523_CLK_GSW] = {
-+		.id = EN7523_CLK_GSW,
-+		.name = "gsw",
-+
-+		.base_reg = REG_GSW_CLK_DIV_SEL,
-+		.base_bits = 2,
-+		.base_shift = 8,
-+		.base_values = gsw7583_base,
-+		.n_base_values = ARRAY_SIZE(gsw7583_base),
-+
-+		.div_bits = 3,
-+		.div_shift = 0,
-+		.div_step = 1,
-+		.div_offset = 1,
-+	},
-+	[EN7523_CLK_EMI] = {
-+		.id = EN7523_CLK_EMI,
-+		.name = "emi",
-+
-+		.base_reg = REG_EMI_CLK_DIV_SEL,
-+		.base_bits = 2,
-+		.base_shift = 8,
-+		.base_values = emi7583_base,
-+		.n_base_values = ARRAY_SIZE(emi7583_base),
-+
-+		.div_bits = 3,
-+		.div_shift = 0,
-+		.div_step = 1,
-+		.div_offset = 1,
-+	},
-+	[EN7523_CLK_BUS] = {
-+		.id = EN7523_CLK_BUS,
-+		.name = "bus",
-+
-+		.base_reg = REG_BUS_CLK_DIV_SEL,
-+		.base_bits = 2,
-+		.base_shift = 8,
-+		.base_values = bus7583_base,
-+		.n_base_values = ARRAY_SIZE(bus7583_base),
-+
-+		.div_bits = 3,
-+		.div_shift = 0,
-+		.div_step = 1,
-+		.div_offset = 1,
-+	},
-+	[EN7523_CLK_SLIC] = {
-+		.id = EN7523_CLK_SLIC,
-+		.name = "slic",
-+
-+		.base_reg = REG_SPI_CLK_FREQ_SEL,
-+		.base_bits = 1,
-+		.base_shift = 0,
-+		.base_values = slic_base,
-+		.n_base_values = ARRAY_SIZE(slic_base),
-+
-+		.div_reg = REG_SPI_CLK_DIV_SEL,
-+		.div_bits = 5,
-+		.div_shift = 24,
-+		.div_val0 = 20,
-+		.div_step = 2,
-+	},
-+	[EN7523_CLK_SPI] = {
-+		.id = EN7523_CLK_SPI,
-+		.name = "spi",
-+
-+		.base_reg = REG_SPI_CLK_FREQ_SEL,
-+		.base_bits = 1,
-+		.base_shift = 1,
-+		.base_values = spi7583_base,
-+		.n_base_values = ARRAY_SIZE(spi7583_base),
-+
-+		.div_reg = REG_SPI_CLK_DIV_SEL,
-+		.div_bits = 5,
-+		.div_shift = 8,
-+		.div_val0 = 40,
-+		.div_step = 2,
-+	},
-+	[EN7523_CLK_NPU] = {
-+		.id = EN7523_CLK_NPU,
-+		.name = "npu",
-+
-+		.base_reg = REG_NPU_CLK_DIV_SEL,
-+		.base_bits = 2,
-+		.base_shift = 9,
-+		.base_values = npu7583_base,
-+		.n_base_values = ARRAY_SIZE(npu7583_base),
-+
-+		.div_bits = 3,
-+		.div_shift = 0,
-+		.div_step = 1,
-+		.div_offset = 1,
-+	},
-+	[EN7523_CLK_CRYPTO] = {
-+		.id = EN7523_CLK_CRYPTO,
-+		.name = "crypto",
-+
-+		.base_reg = REG_CRYPTO_CLKSRC2,
-+		.base_bits = 1,
-+		.base_shift = 0,
-+		.base_values = crypto7583_base,
-+		.n_base_values = ARRAY_SIZE(crypto7583_base),
-+	},
-+	[EN7581_CLK_EMMC] = {
-+		.id = EN7581_CLK_EMMC,
-+		.name = "emmc",
-+
-+		.base_reg = REG_CRYPTO_CLKSRC2,
-+		.base_bits = 1,
-+		.base_shift = 13,
-+		.base_values = emmc7583_base,
-+		.n_base_values = ARRAY_SIZE(emmc7583_base),
-+	}
-+};
-+
- static u32 airoha_clk_get_base_rate(const struct airoha_clk_desc *desc, u32 val)
- {
- 	if (!desc->base_bits)
-@@ -436,10 +559,18 @@ static const struct airoha_clk_soc_data
- 	.descs = en7581_base_clks,
- };
- 
-+static const struct airoha_clk_soc_data an7583_data = {
-+	.num_clocks = ARRAY_SIZE(an7583_base_clks),
-+	.descs = an7583_base_clks,
-+};
-+
- static const struct udevice_id airoha_clk_ids[] = {
- 	{ .compatible = "airoha,en7581-scu",
- 	  .data = (ulong)&en7581_data,
- 	},
-+	{ .compatible = "airoha,an7583-scu",
-+	  .data = (ulong)&an7583_data,
-+	},
- 	{ }
- };
- 
--- a/package/boot/uboot-airoha/patches/302-reset-airoha-convert-to-regmap-API.patch
+++ b/package/boot/uboot-airoha/patches/302-reset-airoha-convert-to-regmap-API.patch
@@ -1,90 +0,0 @@
-From 7daf0565460e548eb766a0bcc171c34e02dd6eba Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 19 May 2025 14:22:55 +0200
-Subject: [PATCH 3/6] reset: airoha: convert to regmap API
-
-In preparation for support for Airoha AN7583, convert the driver to
-regmap API. This is needed as Airoha AN7583 will use syscon to access
-reset registers.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- drivers/reset/reset-airoha.c | 35 ++++++++++++++++++-----------------
- 1 file changed, 18 insertions(+), 17 deletions(-)
-
--- a/drivers/reset/reset-airoha.c
-+++ b/drivers/reset/reset-airoha.c
-@@ -10,6 +10,7 @@
- #include <dm.h>
- #include <linux/io.h>
- #include <reset-uclass.h>
-+#include <regmap.h>
- 
- #include <dt-bindings/reset/airoha,en7581-reset.h>
- 
-@@ -21,7 +22,7 @@
- struct airoha_reset_priv {
- 	const u16 *bank_ofs;
- 	const u16 *idx_map;
-	void __iomem *base;
-+	struct regmap *map;
- };
- 
- static const u16 en7581_rst_ofs[] = {
-@@ -90,17 +91,11 @@ static const u16 en7581_rst_map[] = {
- static int airoha_reset_update(struct airoha_reset_priv *priv,
- 			       unsigned long id, bool assert)
- {
-	void __iomem *addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
-	u32 val;
-
-	val = readl(addr);
-	if (assert)
-		val |= BIT(id % RST_NR_PER_BANK);
-	else
-		val &= ~BIT(id % RST_NR_PER_BANK);
-	writel(val, addr);
-+	u16 offset = priv->bank_ofs[id / RST_NR_PER_BANK];
- 
-	return 0;
-+	return regmap_update_bits(priv->map, offset,
-+				  BIT(id % RST_NR_PER_BANK),
-+				  assert ? BIT(id % RST_NR_PER_BANK) : 0);
- }
- 
- static int airoha_reset_assert(struct reset_ctl *reset_ctl)
-@@ -123,11 +118,16 @@ static int airoha_reset_status(struct re
- {
- 	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- 	int id = reset_ctl->id;
-	void __iomem *addr;
-+	u16 offset;
-+	u32 val;
-+	int ret;
- 
-	addr = priv->base + priv->bank_ofs[id / RST_NR_PER_BANK];
-+	offset = priv->bank_ofs[id / RST_NR_PER_BANK];
-+	ret = regmap_read(priv->map, offset, &val);
-+	if (ret)
-+		return ret;
- 
-	return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
-+	return !!(val & BIT(id % RST_NR_PER_BANK));
- }
- 
- static int airoha_reset_xlate(struct reset_ctl *reset_ctl,
-@@ -153,10 +153,11 @@ static struct reset_ops airoha_reset_ops
- static int airoha_reset_probe(struct udevice *dev)
- {
- 	struct airoha_reset_priv *priv = dev_get_priv(dev);
-+	int ret;
- 
-	priv->base = dev_remap_addr(dev);
-	if (!priv->base)
-		return -ENOMEM;
-+	ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
-+	if (ret)
-+		return ret;
- 
- 	priv->bank_ofs = en7581_rst_ofs;
- 	priv->idx_map = en7581_rst_map;
--- a/package/boot/uboot-airoha/patches/303-reset-airoha-Add-support-for-Airoha-AN7583-reset.patch
+++ b/package/boot/uboot-airoha/patches/303-reset-airoha-Add-support-for-Airoha-AN7583-reset.patch
@@ -1,225 +0,0 @@
-From 23031ad51d55361be507b83307f55995e0204188 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 29 Apr 2025 13:33:35 +0200
-Subject: [PATCH 4/6] reset: airoha: Add support for Airoha AN7583 reset
-
-Adapt the Airoha reset driver to support Airoha AN7583 node structure.
-In AN7583 the register is exposed by the parent syscon hence a different
-logic needs to be applied. Also the reset line differ from AN7581 hence
-a dedicated table is needed.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- drivers/reset/reset-airoha.c                  | 94 ++++++++++++++++++-
- .../dt-bindings/reset/airoha,an7583-reset.h   | 61 ++++++++++++
- 2 files changed, 153 insertions(+), 2 deletions(-)
- create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
-
--- a/drivers/reset/reset-airoha.c
-+++ b/drivers/reset/reset-airoha.c
-@@ -11,8 +11,10 @@
- #include <linux/io.h>
- #include <reset-uclass.h>
- #include <regmap.h>
-+#include <syscon.h>
- 
- #include <dt-bindings/reset/airoha,en7581-reset.h>
-+#include <dt-bindings/reset/airoha,an7583-reset.h>
- 
- #define RST_NR_PER_BANK			32
- 
-@@ -22,6 +24,7 @@
- struct airoha_reset_priv {
- 	const u16 *bank_ofs;
- 	const u16 *idx_map;
-+	int num_rsts;
- 	struct regmap *map;
- };
- 
-@@ -88,6 +91,59 @@ static const u16 en7581_rst_map[] = {
- 	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
- };
- 
-+static const u16 an7583_rst_map[] = {
-+	/* RST_CTRL2 */
-+	[AN7583_XPON_PHY_RST]		= 0,
-+	[AN7583_GPON_OLT_RST]		= 1,
-+	[AN7583_CPU_TIMER2_RST]		= 2,
-+	[AN7583_HSUART_RST]		= 3,
-+	[AN7583_UART4_RST]		= 4,
-+	[AN7583_UART5_RST]		= 5,
-+	[AN7583_I2C2_RST]		= 6,
-+	[AN7583_XSI_MAC_RST]		= 7,
-+	[AN7583_XSI_PHY_RST]		= 8,
-+	[AN7583_NPU_RST]		= 9,
-+	[AN7583_TRNG_MSTART_RST]	= 12,
-+	[AN7583_DUAL_HSI0_RST]		= 13,
-+	[AN7583_DUAL_HSI1_RST]		= 14,
-+	[AN7583_DUAL_HSI0_MAC_RST]	= 16,
-+	[AN7583_DUAL_HSI1_MAC_RST]	= 17,
-+	[AN7583_WDMA_RST]		= 19,
-+	[AN7583_WOE0_RST]		= 20,
-+	[AN7583_HSDMA_RST]		= 22,
-+	[AN7583_TDMA_RST]		= 24,
-+	[AN7583_EMMC_RST]		= 25,
-+	[AN7583_SOE_RST]		= 26,
-+	[AN7583_XFP_MAC_RST]		= 28,
-+	[AN7583_MDIO0]			= 30,
-+	[AN7583_MDIO1]			= 31,
-+	/* RST_CTRL1 */
-+	[AN7583_PCM1_ZSI_ISI_RST]	= RST_NR_PER_BANK + 0,
-+	[AN7583_FE_PDMA_RST]		= RST_NR_PER_BANK + 1,
-+	[AN7583_FE_QDMA_RST]		= RST_NR_PER_BANK + 2,
-+	[AN7583_PCM_SPIWP_RST]		= RST_NR_PER_BANK + 4,
-+	[AN7583_CRYPTO_RST]		= RST_NR_PER_BANK + 6,
-+	[AN7583_TIMER_RST]		= RST_NR_PER_BANK + 8,
-+	[AN7583_PCM1_RST]		= RST_NR_PER_BANK + 11,
-+	[AN7583_UART_RST]		= RST_NR_PER_BANK + 12,
-+	[AN7583_GPIO_RST]		= RST_NR_PER_BANK + 13,
-+	[AN7583_GDMA_RST]		= RST_NR_PER_BANK + 14,
-+	[AN7583_I2C_MASTER_RST]		= RST_NR_PER_BANK + 16,
-+	[AN7583_PCM2_ZSI_ISI_RST]	= RST_NR_PER_BANK + 17,
-+	[AN7583_SFC_RST]		= RST_NR_PER_BANK + 18,
-+	[AN7583_UART2_RST]		= RST_NR_PER_BANK + 19,
-+	[AN7583_GDMP_RST]		= RST_NR_PER_BANK + 20,
-+	[AN7583_FE_RST]			= RST_NR_PER_BANK + 21,
-+	[AN7583_USB_HOST_P0_RST]	= RST_NR_PER_BANK + 22,
-+	[AN7583_GSW_RST]		= RST_NR_PER_BANK + 23,
-+	[AN7583_SFC2_PCM_RST]		= RST_NR_PER_BANK + 25,
-+	[AN7583_PCIE0_RST]		= RST_NR_PER_BANK + 26,
-+	[AN7583_PCIE1_RST]		= RST_NR_PER_BANK + 27,
-+	[AN7583_CPU_TIMER_RST]		= RST_NR_PER_BANK + 28,
-+	[AN7583_PCIE_HB_RST]		= RST_NR_PER_BANK + 29,
-+	[AN7583_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
-+};
-+
- static int airoha_reset_update(struct airoha_reset_priv *priv,
- 			       unsigned long id, bool assert)
- {
-@@ -135,7 +191,7 @@ static int airoha_reset_xlate(struct res
- {
- 	struct airoha_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- 
-	if (args->args[0] >= ARRAY_SIZE(en7581_rst_map))
-+	if (args->args[0] >= priv->num_rsts)
- 		return -EINVAL;
- 
- 	reset_ctl->id = priv->idx_map[args->args[0]];
-@@ -150,7 +206,7 @@ static struct reset_ops airoha_reset_ops
- 	.rst_status = airoha_reset_status,
- };
- 
-static int airoha_reset_probe(struct udevice *dev)
-+static int an7581_reset_probe(struct udevice *dev)
- {
- 	struct airoha_reset_priv *priv = dev_get_priv(dev);
- 	int ret;
-@@ -161,10 +217,44 @@ static int airoha_reset_probe(struct ude
- 
- 	priv->bank_ofs = en7581_rst_ofs;
- 	priv->idx_map = en7581_rst_map;
-+	priv->num_rsts = ARRAY_SIZE(en7581_rst_map);
- 
- 	return 0;
- }
- 
-+static int an7583_reset_probe(struct udevice *dev)
-+{
-+	struct airoha_reset_priv *priv = dev_get_priv(dev);
-+	ofnode pnode, scu_node = dev_ofnode(dev);
-+
-+	pnode = ofnode_get_parent(scu_node);
-+	if (!ofnode_valid(pnode))
-+		return -EINVAL;
-+
-+	priv->map = syscon_node_to_regmap(pnode);
-+	if (IS_ERR(priv->map))
-+		return PTR_ERR(priv->map);
-+
-+	priv->bank_ofs = en7581_rst_ofs;
-+	priv->idx_map = an7583_rst_map;
-+	priv->num_rsts = ARRAY_SIZE(an7583_rst_map);
-+
-+	return 0;
-+}
-+
-+static int airoha_reset_probe(struct udevice *dev)
-+{
-+	if (ofnode_device_is_compatible(dev_ofnode(dev),
-+					"airoha,en7581-scu"))
-+		return an7581_reset_probe(dev);
-+
-+	if (ofnode_device_is_compatible(dev_ofnode(dev),
-+					"airoha,an7583-scu"))
-+		return an7583_reset_probe(dev);
-+
-+	return -ENODEV;
-+}
-+
- U_BOOT_DRIVER(airoha_reset) = {
- 	.name = "airoha-reset",
- 	.id = UCLASS_RESET,
--- /dev/null
-+++ b/include/dt-bindings/reset/airoha,an7583-reset.h
-@@ -0,0 +1,61 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (c) 2024 AIROHA Inc
-+ * Author: Christian Marangi <ansuelsmth@gmail.com>
-+ */
-+
-+#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
-+#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_
-+
-+/* RST_CTRL2 */
-+#define AN7583_XPON_PHY_RST		 0
-+#define AN7583_GPON_OLT_RST		 1
-+#define AN7583_CPU_TIMER2_RST		 2
-+#define AN7583_HSUART_RST		 3
-+#define AN7583_UART4_RST		 4
-+#define AN7583_UART5_RST		 5
-+#define AN7583_I2C2_RST			 6
-+#define AN7583_XSI_MAC_RST		 7
-+#define AN7583_XSI_PHY_RST		 8
-+#define AN7583_NPU_RST			 9
-+#define AN7583_TRNG_MSTART_RST		10
-+#define AN7583_DUAL_HSI0_RST		11
-+#define AN7583_DUAL_HSI1_RST		12
-+#define AN7583_DUAL_HSI0_MAC_RST	13
-+#define AN7583_DUAL_HSI1_MAC_RST	14
-+#define AN7583_WDMA_RST			15
-+#define AN7583_WOE0_RST			16
-+#define AN7583_HSDMA_RST		17
-+#define AN7583_TDMA_RST			18
-+#define AN7583_EMMC_RST			19
-+#define AN7583_SOE_RST			20
-+#define AN7583_XFP_MAC_RST		21
-+#define AN7583_MDIO0    		22
-+#define AN7583_MDIO1            	23
-+/* RST_CTRL1 */
-+#define AN7583_PCM1_ZSI_ISI_RST		24
-+#define AN7583_FE_PDMA_RST		25
-+#define AN7583_FE_QDMA_RST		26
-+#define AN7583_PCM_SPIWP_RST		27
-+#define AN7583_CRYPTO_RST		28
-+#define AN7583_TIMER_RST		29
-+#define AN7583_PCM1_RST			30
-+#define AN7583_UART_RST			31
-+#define AN7583_GPIO_RST			32
-+#define AN7583_GDMA_RST			33
-+#define AN7583_I2C_MASTER_RST		34
-+#define AN7583_PCM2_ZSI_ISI_RST		35
-+#define AN7583_SFC_RST			36
-+#define AN7583_UART2_RST		37
-+#define AN7583_GDMP_RST			38
-+#define AN7583_FE_RST			39
-+#define AN7583_USB_HOST_P0_RST		40
-+#define AN7583_GSW_RST			41
-+#define AN7583_SFC2_PCM_RST		42
-+#define AN7583_PCIE0_RST		43
-+#define AN7583_PCIE1_RST		44
-+#define AN7583_CPU_TIMER_RST		45
-+#define AN7583_PCIE_HB_RST		46
-+#define AN7583_XPON_MAC_RST		47
-+
-+#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_AN7583_H_ */
--- a/package/boot/uboot-airoha/patches/304-net-airoha-add-support-for-Airoha-AN7583.patch
+++ b/package/boot/uboot-airoha/patches/304-net-airoha-add-support-for-Airoha-AN7583.patch
@@ -1,279 +0,0 @@
-From 289503869e5580658035e82d91b02a43c775f1a1 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 19 May 2025 14:29:53 +0200
-Subject: [PATCH 1/4] net: airoha: add support for Airoha AN7583
-
-Add support for Ethernet controller present in Airoha AN7583. This
-follow the same implementation of Airoha AN7581 with the only difference
-of having a different reset number and a different logic to reach the
-SCU node.
-
-Generalize the driver for these 2 part to account for these minor
-difference.
-
-The switch init part also required some care as the Switch Internal PHY
-enable BMCR_PDOWN by default and tweak to GEPHY_CONN_CFG is also needed.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- drivers/net/airoha_eth.c | 168 ++++++++++++++++++++++++++++++++++-----
- 1 file changed, 147 insertions(+), 21 deletions(-)
-
--- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -20,6 +20,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/io.h>
- #include <linux/iopoll.h>
-+#include <linux/mii.h>
- #include <linux/time.h>
- 
- #define AIROHA_MAX_NUM_GDM_PORTS	1
-@@ -27,6 +28,11 @@
- #define AIROHA_MAX_NUM_RSTS		3
- #define AIROHA_MAX_NUM_XSI_RSTS		4
- 
-+#define AIROHA_MAX_NUM_SWITCH_PORT	4
-+#define AIROHA_MAX_PBUS_TRY		10
-+#define AIROHA_PBUS_SLEEP		100
-+#define AIROHA_PBUS_C22_MASK		0x800000
-+
- #define AIROHA_MAX_PACKET_SIZE		2048
- #define AIROHA_NUM_TX_RING		1
- #define AIROHA_NUM_RX_RING		1
-@@ -77,6 +83,19 @@
- #define   SWITCH_PHY_PRE_EN		BIT(15)
- #define   SWITCH_PHY_END_ADDR		GENMASK(12, 8)
- #define   SWITCH_PHY_ST_ADDR		GENMASK(4, 0)
-+#define SWITCH_GEPHY_CONN_CFG		0x7c14
-+#define   SWITCH_DPHY_CKIN_SEL		BIT(31)
-+#define   SWITCH_PHY_CORE_REG_CLK_SEL	BIT(30)
-+#define   SWITCH_ETHER_AFE_PWD		GENMASK(28, 24)
-+#define SWITCH_PBUS_PHY_IAC		0x7c20
-+#define   SWITCH_PBUS_PHY_START		BIT(31)
-+#define   SWITCH_PBUS_PHY_CMD		BIT(30)
-+#define   SWITCH_PBUS_PHY_CMD_READ	FIELD_PREP(SWITCH_PBUS_PHY_CMD, 0x0)
-+#define   SWITCH_PBUS_PHY_CMD_WRITE	FIELD_PREP(SWITCH_PBUS_PHY_CMD, 0x1)
-+#define   SWITCH_PBUS_PHY_PORTADDR	GENMASK(28, 24)
-+#define   SWITCH_PBUS_PHY_REGADDR	GENMASK(23, 0)
-+#define SWITCH_PBUS_PHY_IAWD		0x7c24
-+#define SWITCH_PBUS_PHY_IARD		0x7c28
- 
- /* FE */
- #define PSE_BASE			0x0100
-@@ -311,6 +330,26 @@ struct airoha_eth {
- 	struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
- };
- 
-+struct airoha_eth_soc_data {
-+	int num_xsi_rsts;
-+	const char * const *xsi_rsts_names;
-+	ofnode (*get_scu_node)(struct udevice *dev);
-+	const char *switch_compatible;
-+};
-+
-+static const char * const en7581_xsi_rsts_names[] = {
-+	"hsi0-mac",
-+	"hsi1-mac",
-+	"hsi-mac",
-+	"xfp-mac",
-+};
-+
-+static const char * const an7583_xsi_rsts_names[] = {
-+	"hsi0-mac",
-+	"hsi1-mac",
-+	"xfp-mac",
-+};
-+
- static u32 airoha_rr(void __iomem *base, u32 offset)
- {
- 	return readl(base + offset);
-@@ -351,8 +390,12 @@ static u32 airoha_rmw(void __iomem *base
- #define airoha_qdma_clear(qdma, offset, val)			\
- 	airoha_rmw((qdma)->regs, (offset), (val), 0)
- 
-+#define airoha_switch_rr(eth, offset)				\
-+	airoha_rr((eth)->switch_regs, (offset))
- #define airoha_switch_wr(eth, offset, val)			\
- 	airoha_wr((eth)->switch_regs, (offset), (val))
-+#define airoha_switch_rmw(eth, offset, mask, val)		\
-+	airoha_rmw((eth)->switch_regs, (offset), (mask), (val))
- 
- static void airoha_fe_maccr_init(struct airoha_eth *eth)
- {
-@@ -652,10 +695,12 @@ static int airoha_hw_init(struct udevice
- 
- static int airoha_switch_init(struct udevice *dev, struct airoha_eth *eth)
- {
-+	struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev);
- 	ofnode switch_node;
- 	fdt_addr_t addr;
- 
-	switch_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-switch");
-+	switch_node = ofnode_by_compatible(ofnode_null(),
-+					   data->switch_compatible);
- 	if (!ofnode_valid(switch_node))
- 		return -EINVAL;
- 
-@@ -687,17 +732,71 @@ static int airoha_switch_init(struct ude
- 			 FIELD_PREP(SWITCH_PHY_END_ADDR, 0xc) |
- 			 FIELD_PREP(SWITCH_PHY_ST_ADDR, 0x8));
- 
-+	/* AN7583 require tweak to GEPHY_CONN_CFG and clear PHY BMCR_PDOWN */
-+	if (!strcmp(data->switch_compatible, "airoha,an7583-switch")) {
-+		int i;
-+
-+		airoha_switch_rmw(eth, SWITCH_GEPHY_CONN_CFG,
-+				  SWITCH_DPHY_CKIN_SEL |
-+				  SWITCH_PHY_CORE_REG_CLK_SEL |
-+				  SWITCH_ETHER_AFE_PWD,
-+				  SWITCH_DPHY_CKIN_SEL |
-+				  SWITCH_PHY_CORE_REG_CLK_SEL |
-+				  FIELD_PREP(SWITCH_ETHER_AFE_PWD, 0));
-+
-+		/* Disable BMCR_PDOWN for every PHY */
-+		for (i = 0; i < AIROHA_MAX_NUM_SWITCH_PORT; i++) {
-+			int try;
-+			u32 val;
-+
-+			airoha_switch_wr(eth, SWITCH_PBUS_PHY_IAC,
-+					 SWITCH_PBUS_PHY_START |
-+					 SWITCH_PBUS_PHY_CMD_READ |
-+					 FIELD_PREP(SWITCH_PBUS_PHY_PORTADDR, i) |
-+					 FIELD_PREP(SWITCH_PBUS_PHY_REGADDR,
-+						    AIROHA_PBUS_C22_MASK | MII_BMCR));
-+
-+			for (try = 0; try < AIROHA_MAX_PBUS_TRY; try++) {
-+				val = airoha_switch_rr(eth, SWITCH_PBUS_PHY_IAC);
-+				if (!(val & SWITCH_PBUS_PHY_START))
-+					break;
-+
-+				udelay(AIROHA_PBUS_SLEEP);
-+			}
-+
-+			val = airoha_switch_rr(eth, SWITCH_PBUS_PHY_IARD);
-+			val &= ~BMCR_PDOWN;
-+
-+			airoha_switch_wr(eth, SWITCH_PBUS_PHY_IAWD, val);
-+			airoha_switch_wr(eth, SWITCH_PBUS_PHY_IAC,
-+					 SWITCH_PBUS_PHY_START |
-+					 SWITCH_PBUS_PHY_CMD_WRITE |
-+					 FIELD_PREP(SWITCH_PBUS_PHY_PORTADDR, i) |
-+					 FIELD_PREP(SWITCH_PBUS_PHY_REGADDR,
-+						    AIROHA_PBUS_C22_MASK | MII_BMCR));
-+
-+			for (try = 0; try < AIROHA_MAX_PBUS_TRY; try++) {
-+				val = airoha_switch_rr(eth, SWITCH_PBUS_PHY_IAC);
-+				if (!(val & SWITCH_PBUS_PHY_START))
-+					break;
-+
-+				udelay(AIROHA_PBUS_SLEEP);
-+			}
-+		}
-+	}
-+
- 	return 0;
- }
- 
- static int airoha_eth_probe(struct udevice *dev)
- {
-+	struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev);
- 	struct airoha_eth *eth = dev_get_priv(dev);
- 	struct regmap *scu_regmap;
- 	ofnode scu_node;
-	int ret;
-+	int i, ret;
- 
-	scu_node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu");
-+	scu_node = data->get_scu_node(dev);
- 	if (!ofnode_valid(scu_node))
- 		return -EINVAL;
- 
-@@ -721,11 +820,11 @@ static int airoha_eth_probe(struct udevi
- 		return -ENOMEM;
- 	eth->rsts.count = AIROHA_MAX_NUM_RSTS;
- 
-	eth->xsi_rsts.resets = devm_kcalloc(dev, AIROHA_MAX_NUM_XSI_RSTS,
-+	eth->xsi_rsts.resets = devm_kcalloc(dev, data->num_xsi_rsts,
- 					    sizeof(struct reset_ctl), GFP_KERNEL);
- 	if (!eth->xsi_rsts.resets)
- 		return -ENOMEM;
-	eth->xsi_rsts.count = AIROHA_MAX_NUM_XSI_RSTS;
-+	eth->xsi_rsts.count = data->num_xsi_rsts;
- 
- 	ret = reset_get_by_name(dev, "fe", &eth->rsts.resets[0]);
- 	if (ret)
-@@ -739,21 +838,12 @@ static int airoha_eth_probe(struct udevi
- 	if (ret)
- 		return ret;
- 
-	ret = reset_get_by_name(dev, "hsi0-mac", &eth->xsi_rsts.resets[0]);
-	if (ret)
-		return ret;
-
-	ret = reset_get_by_name(dev, "hsi1-mac", &eth->xsi_rsts.resets[1]);
-	if (ret)
-		return ret;
-
-	ret = reset_get_by_name(dev, "hsi-mac", &eth->xsi_rsts.resets[2]);
-	if (ret)
-		return ret;
-
-	ret = reset_get_by_name(dev, "xfp-mac", &eth->xsi_rsts.resets[3]);
-	if (ret)
-		return ret;
-+	for (i = 0; i < data->num_xsi_rsts; i++) {
-+		ret = reset_get_by_name(dev, data->xsi_rsts_names[i],
-+					&eth->xsi_rsts.resets[i]);
-+		if (ret)
-+			return ret;
-+	}
- 
- 	ret = airoha_hw_init(dev, eth);
- 	if (ret)
-@@ -924,8 +1014,44 @@ static int arht_eth_write_hwaddr(struct
- 	return 0;
- }
- 
-+
-+static ofnode en7581_get_scu_node(struct udevice *dev)
-+{
-+	return ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu");
-+}
-+
-+static ofnode an7583_get_scu_node(struct udevice *dev)
-+{
-+	ofnode scu_node;
-+
-+	scu_node = ofnode_by_compatible(ofnode_null(), "airoha,an7583-scu");
-+	if (!ofnode_valid(scu_node))
-+		return scu_node;
-+
-+	return ofnode_get_parent(scu_node);
-+}
-+
-+static const struct airoha_eth_soc_data en7581_data = {
-+	.xsi_rsts_names = en7581_xsi_rsts_names,
-+	.num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names),
-+	.get_scu_node = en7581_get_scu_node,
-+	.switch_compatible = "airoha,en7581-switch",
-+};
-+
-+static const struct airoha_eth_soc_data an7583_data = {
-+	.xsi_rsts_names = an7583_xsi_rsts_names,
-+	.num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names),
-+	.get_scu_node = an7583_get_scu_node,
-+	.switch_compatible = "airoha,an7583-switch",
-+};
-+
- static const struct udevice_id airoha_eth_ids[] = {
-	{ .compatible = "airoha,en7581-eth" },
-+	{ .compatible = "airoha,en7581-eth",
-+	  .data = (ulong)&en7581_data,
-+	},
-+	{ .compatible = "airoha,an7583-eth",
-+	  .data = (ulong)&an7583_data,
-+	},
- };
- 
- static const struct eth_ops airoha_eth_ops = {
--- a/package/boot/uboot-airoha/patches/305-airoha-add-Ethernet-node-in-AN7583-dtsi.patch
+++ b/package/boot/uboot-airoha/patches/305-airoha-add-Ethernet-node-in-AN7583-dtsi.patch
@@ -1,45 +0,0 @@
-From 613d695d0939cbbe6b66933267e3a4be263e1c7b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 19 May 2025 14:31:59 +0200
-Subject: [PATCH 2/4] airoha: add Ethernet node in AN7583 dtsi
-
-Add Ethernet node in AN7583 dtsi to add support for the integrated
-Ethernet Controller.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- arch/arm/dts/an7583.dtsi | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
--- a/arch/arm/dts/an7583.dtsi
-+++ b/arch/arm/dts/an7583.dtsi
-@@ -130,6 +130,29 @@
- 			reg = <0x0 0x1fa20000 0x0 0x388>;
- 		};
- 
-+		eth: ethernet@1fb50000 {
-+			compatible = "airoha,an7583-eth";
-+			reg = <0 0x1fb50000 0 0x2600>,
-+				<0 0x1fb54000 0 0x2000>,
-+				<0 0x1fb56000 0 0x2000>;
-+			reg-names = "fe", "qdma0", "qdma1";
-+
-+			resets = <&scuclk AN7583_FE_RST>,
-+				 <&scuclk AN7583_FE_PDMA_RST>,
-+				 <&scuclk AN7583_FE_QDMA_RST>,
-+				 <&scuclk AN7583_DUAL_HSI0_MAC_RST>,
-+				 <&scuclk AN7583_DUAL_HSI1_MAC_RST>,
-+				 <&scuclk AN7583_XFP_MAC_RST>;
-+			reset-names = "fe", "pdma", "qdma",
-+				      "hsi0-mac", "hsi1-mac",
-+				      "xfp-mac";
-+		};
-+
-+		switch: switch@1fb58000 {
-+			compatible = "airoha,an7583-switch";
-+			reg = <0 0x1fb58000 0 0x8000>;
-+		};
-+
- 		syscon@1fbe3400 {
- 			compatible = "airoha,en7581-pbus-csr", "syscon";
- 			reg = <0x0 0x1fbe3400 0x0 0xff>;
--- a/package/boot/uboot-airoha/patches/306-airoha-add-MMC-node-for-Airoha-AN7583.patch
+++ b/package/boot/uboot-airoha/patches/306-airoha-add-MMC-node-for-Airoha-AN7583.patch
@@ -1,65 +0,0 @@
-From 1a3039c1e3a194b3f1e72b4506f8bdcd5b10fbbf Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Mon, 19 May 2025 14:52:26 +0200
-Subject: [PATCH] airoha: add MMC node for Airoha AN7583
-
-Add MMC node for Airoha AN7583. These follow the same node of Airoha
-AN7581.
-
-Similar to Airoha AN7581, add the fixed regulator and fixed clock for
-MMC.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- arch/arm/dts/an7583.dtsi | 33 +++++++++++++++++++++++++++++++++
- 1 file changed, 33 insertions(+)
-
--- a/arch/arm/dts/an7583.dtsi
-+++ b/arch/arm/dts/an7583.dtsi
-@@ -105,6 +105,21 @@
- 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- 	};
- 
-+	clk25m: oscillator {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <25000000>;
-+		clock-output-names = "clkxtal";
-+	};
-+
-+	vmmc_3v3: regulator-vmmc-3v3 {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vmmc";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		regulator-always-on;
-+	};
-+
- 	soc {
- 		compatible = "simple-bus";
- 		#address-cells = <2>;
-@@ -259,6 +274,24 @@
- 			};
- 		};
- 
-+		mmc0: mmc@1fa0e000 {
-+			compatible = "mediatek,mt7622-mmc";
-+			reg = <0x0 0x1fa0e000 0x0 0x1000>,
-+				<0x0 0x1fa0c000 0x0 0x60>;
-+			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
-+			clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>;
-+			clock-names = "source", "hclk";
-+			bus-width = <4>;
-+			max-frequency = <52000000>;
-+			vmmc-supply = <&vmmc_3v3>;
-+			disable-wp;
-+			cap-mmc-highspeed;
-+			non-removable;
-+
-+			assigned-clocks = <&scuclk EN7581_CLK_EMMC>;
-+			assigned-clock-rates = <200000000>;
-+		};
-+
- 		uart1: serial@1fbf0000 {
- 			compatible = "ns16550";
- 			reg = <0x0 0x1fbf0000 0x0 0x30>;
--- a/package/boot/uboot-airoha/patches/500-drivers-net-airoha_eth-add-missing-terminator-for-co.patch
+++ b/package/boot/uboot-airoha/patches/500-drivers-net-airoha_eth-add-missing-terminator-for-co.patch
@@ -1,32 +0,0 @@
-From a11420dac873fbd5b8a81192571d914f01bee26d Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 9 Jul 2025 12:28:07 +0300
-Subject: [PATCH 1/5] drivers/net/airoha_eth: add missing terminator for
- compatible devices list
-
-Compatible device list must have a terminator. If terminator is missed
-the u-boot driver subsystem will access random data placed after the
-list in the memory.
-
-The issue can be observed with the "dm compat" command.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/net/airoha_eth.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index b3fd1ab9064..db34ec48c81 100644
--- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -1052,6 +1052,7 @@ static const struct udevice_id airoha_eth_ids[] = {
- 	{ .compatible = "airoha,an7583-eth",
- 	  .data = (ulong)&an7583_data,
- 	},
-+	{ }
- };
- 
- static const struct eth_ops airoha_eth_ops = {
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/501-drivers-net-airoha_eth-fix-packet-transmission-error.patch
+++ b/package/boot/uboot-airoha/patches/501-drivers-net-airoha_eth-fix-packet-transmission-error.patch
@@ -1,107 +0,0 @@
-From 8fce1cfe775e1f3b5d7cecb8bdcc8271bf9f799c Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 9 Jul 2025 12:28:08 +0300
-Subject: [PATCH 2/5] drivers/net/airoha_eth: fix packet transmission errors
-
-The dma_map_single() function calls one of the functions
-  * invalidate_dcache_range(),
-  * flush_dcache_range().
-Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN
-boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they
-might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing
-(or invalidating) might do nothing in this case.
-
-The same applies to dma_unmap_single() function.
-
-In the TX path case the issue might prevent package transmission (filled
-TX descriptor was not flushed).
-
-To fix an issue a special wrappers for
-  * dma_map_single(),
-  * dma_unmap_single()
-functions were created. The patch fix flushing/invalidatiog for the
-RX path as well.
-
-The bug appears on 32-bit airoha platform, but should be present on
-64-bit as well.
-
-The code was tested both on 32-bit and 64-bit airoha boards.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/net/airoha_eth.c | 33 +++++++++++++++++++++++++++------
- 1 file changed, 27 insertions(+), 6 deletions(-)
-
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index db34ec48c81..aae6922f3c7 100644
--- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -397,6 +397,27 @@ static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
- #define airoha_switch_rmw(eth, offset, mask, val)		\
- 	airoha_rmw((eth)->switch_regs, (offset), (mask), (val))
- 
-+static inline dma_addr_t dma_map_unaligned(void *vaddr, size_t len,
-+					   enum dma_data_direction dir)
-+{
-+	uintptr_t start, end;
-+
-+	start = ALIGN_DOWN((uintptr_t)vaddr, ARCH_DMA_MINALIGN);
-+	end = ALIGN((uintptr_t)(vaddr + len), ARCH_DMA_MINALIGN);
-+
-+	return dma_map_single((void *)start, end - start, dir);
-+}
-+
-+static inline void dma_unmap_unaligned(dma_addr_t addr, size_t len,
-+				       enum dma_data_direction dir)
-+{
-+	uintptr_t start, end;
-+
-+	start = ALIGN_DOWN((uintptr_t)addr, ARCH_DMA_MINALIGN);
-+	end = ALIGN((uintptr_t)(addr + len), ARCH_DMA_MINALIGN);
-+	dma_unmap_single(start, end - start, dir);
-+}
-+
- static void airoha_fe_maccr_init(struct airoha_eth *eth)
- {
- 	int p;
-@@ -434,7 +455,7 @@ static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index,
- 	val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN);
- 	WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
- 
-	dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
-+	dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE);
- }
- 
- static void airoha_qdma_init_rx_desc(struct airoha_queue *q)
-@@ -916,14 +937,14 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length)
- 	WRITE_ONCE(desc->msg1, cpu_to_le32(msg1));
- 	WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff));
- 
-	dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
-+	dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE);
- 
- 	airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
- 			FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
- 
- 	for (i = 0; i < 100; i++) {
-		dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
-				 DMA_FROM_DEVICE);
-+		dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc),
-+				    DMA_FROM_DEVICE);
- 		if (desc->ctrl & QDMA_DESC_DONE_MASK)
- 			break;
- 
-@@ -954,8 +975,8 @@ static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp)
- 	q = &qdma->q_rx[qid];
- 	desc = &q->desc[q->head];
- 
-	dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
-			 DMA_FROM_DEVICE);
-+	dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc),
-+			    DMA_FROM_DEVICE);
- 
- 	if (!(desc->ctrl & QDMA_DESC_DONE_MASK))
- 		return -EAGAIN;
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/502-drivers-net-airoha_eth-fix-stalling-in-package-recei.patch
+++ b/package/boot/uboot-airoha/patches/502-drivers-net-airoha_eth-fix-stalling-in-package-recei.patch
@@ -1,135 +0,0 @@
-From 352c071bc18855238565cc6417a4c15a4e24bad8 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 9 Jul 2025 12:28:09 +0300
-Subject: [PATCH 3/5] drivers/net/airoha_eth: fix stalling in package
- receiving
-
-ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX
-descriptors are 32 bytes long. So they may not be aligned on an
-ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the
-following problem
-
-1) Assume that a packet has arrived and the EVEN rx descriptor has been
-   updated with the incoming data. The driver will invalidate and check
-   the corresponding rx descriptor.
-
-2) Now suppose the next descriptor (ODD) has not yet completed.
-
-   Please note that all even descriptors starts on 64-byte boundary,
-   and the odd ones are NOT aligned on 64-byte boundary.
-
-   Inspecting even descriptor, we will read the entire CPU cache line
-   (64 bytes). So we read and sore in CPU cache also the next (odd)
-   descriptor.
-
-3) Now suppose the next packet (for the odd rx descriptor) arrived
-   while the first packet was being processed. So we have new data
-   in memory but old data in cache.
-
-4) After packet processing (in arht_eth_free_pkt() function) we will
-   cleanup the descriptor and put it back to rx queue.
-
-   This will call flush_dcache_range() function for the even descriptor,
-   so the odd one will be flushed as well (it is in the same cache line).
-   So the old data will be written to the next rx descriptor.
-
-5) We get a freeze. The next descriptor is empty (so the driver is
-   waiting for packets), but the hardware will continue to receive
-   packets on other available descriptors. This will continue until
-   the last available rx descriptor is full. Then the hardware will
-   also freeze.
-
-The problem will be solved if:
-  * do nothing in even descriptor case,
-  * return 2 descriptor to the queue (current and previous) in the odd
-    descriptor case.
-
-If the current descriptor is even nothing will be done, so no issue
-will arrise.
-
-If the current descriptor is odd, then the previous descriptor is on
-the same cache line. Both (current and previous) descriptors are not
-currently in use, so issue will not arrise as well.
-
-WARNING: The following restrictions on PKTBUFSRX must be held:
-  * PKTBUFSRX is even,
-  * PKTBUFSRX >= 4. Observations shows that PKTBUFSRX must be at least 8.
-
-The bug appears on 32-bit airoha platform, but should be present on
-64-bit as well.
-
-The code was tested both on 32-bit and 64-bit airoha boards.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/net/airoha_eth.c | 33 ++++++++++++++++++++++++++-------
- 1 file changed, 26 insertions(+), 7 deletions(-)
-
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index aae6922f3c7..44d4773bc5d 100644
--- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -435,13 +435,14 @@ static int airoha_fe_init(struct airoha_eth *eth)
- 	return 0;
- }
- 
-static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index,
-				      uchar *rx_packet)
-+static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index)
- {
- 	struct airoha_qdma_desc *desc;
-+	uchar *rx_packet;
- 	u32 val;
- 
- 	desc = &q->desc[index];
-+	rx_packet = net_rx_packets[index];
- 	index = (index + 1) % q->ndesc;
- 
- 	dma_map_single(rx_packet, PKTSIZE_ALIGN, DMA_TO_DEVICE);
-@@ -463,7 +464,7 @@ static void airoha_qdma_init_rx_desc(struct airoha_queue *q)
- 	int i;
- 
- 	for (i = 0; i < q->ndesc; i++)
-		airoha_qdma_reset_rx_desc(q, i, net_rx_packets[i]);
-+		airoha_qdma_reset_rx_desc(q, i);
- }
- 
- static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
-@@ -1003,12 +1004,30 @@ static int arht_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
- 	qid = 0;
- 	q = &qdma->q_rx[qid];
- 
-	dma_map_single(packet, length, DMA_TO_DEVICE);
-+	/*
-+	 * Due to cpu cache issue the airoha_qdma_reset_rx_desc() function
-+	 * will always touch 2 descriptors placed on the same cacheline:
-+	 *   - if current descriptor is even, then current and next
-+	 *     descriptors will be touched
-+	 *   - if current descriptor is odd, then current and previous
-+	 *     descriptors will be touched
-+	 *
-+	 * Thus, to prevent possible destroying of rx queue, we should:
-+	 *   - do nothing in the even descriptor case,
-+	 *   - utilize 2 descriptors (current and previous one) in the
-+	 *     odd descriptor case.
-+	 *
-+	 * WARNING: Observations shows that PKTBUFSRX must be even and
-+	 *          larger than 7 for reliable driver operations.
-+	 */
-+	if (q->head & 0x01) {
-+		airoha_qdma_reset_rx_desc(q, q->head - 1);
-+		airoha_qdma_reset_rx_desc(q, q->head);
- 
-	airoha_qdma_reset_rx_desc(q, q->head, packet);
-+		airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
-+				FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
-+	}
- 
-	airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK,
-			FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head));
- 	q->head = (q->head + 1) % q->ndesc;
- 
- 	return 0;
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/503-drivers-net-airoha_eth-enable-hw-padding-of-short-tx.patch
+++ b/package/boot/uboot-airoha/patches/503-drivers-net-airoha_eth-enable-hw-padding-of-short-tx.patch
@@ -1,64 +0,0 @@
-From dc0ae3455f4344403e293c9b385653ad3fddb0b1 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Wed, 9 Jul 2025 12:28:10 +0300
-Subject: [PATCH 4/5] drivers/net/airoha_eth: enable hw padding of short tx
- packets
-
-Transmission of short packets does not work good for XFI (GDM2) and
-HSGMII (GDM3) interfaces. The issue can be solved with:
-
- - padding of short packets to 60 bytes
- - setting of PAD_EN bit in the corresponding REG_GDM_FWD_CFG(n)
-   register.
-
-The issue should present for the lan switch (GDM1) as well, but it does
-does not appear due to unknown reason.
-
-This patch set PAD_EN bit for the used GDM.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- drivers/net/airoha_eth.c | 13 +++++++++++--
- 1 file changed, 11 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
-index 53c722379c9..b2f73c7dbb7 100644
--- a/drivers/net/airoha_eth.c
-+++ b/drivers/net/airoha_eth.c
-@@ -116,6 +116,7 @@
- 	 (_n) == 2 ? GDM2_BASE : GDM1_BASE)
- 
- #define REG_GDM_FWD_CFG(_n)		GDM_BASE(_n)
-+#define GDM_PAD_EN			BIT(28)
- #define GDM_DROP_CRC_ERR		BIT(23)
- #define GDM_IP4_CKSUM			BIT(22)
- #define GDM_TCP_CKSUM			BIT(21)
-@@ -423,8 +424,11 @@ static void airoha_fe_maccr_init(struct airoha_eth *eth)
- 	int p;
- 
- 	for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) {
-		/* Disable any kind of CRC drop or offload */
-		airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), 0);
-+		/*
-+		 * Disable any kind of CRC drop or offload.
-+		 * Enable padding of short TX packets to 60 bytes.
-+		 */
-+		airoha_fe_wr(eth, REG_GDM_FWD_CFG(p), GDM_PAD_EN);
- 	}
- }
- 
-@@ -920,6 +924,11 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length)
- 	u32 val;
- 	int i;
- 
-+	/*
-+	 * There is no need to pad short TX packets to 60 bytes since the
-+	 * GDM_PAD_EN bit set in the corresponding REG_GDM_FWD_CFG(n) register.
-+	 */
-+
- 	dma_addr = dma_map_single(packet, length, DMA_TO_DEVICE);
- 
- 	qid = 0;
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/504-net-airoha-increase-the-number-of-rx-network-buffers.patch
+++ b/package/boot/uboot-airoha/patches/504-net-airoha-increase-the-number-of-rx-network-buffers.patch
@@ -1,42 +0,0 @@
-From 75d82c8878b2ffff489fbc7a5c0381f8f6484ec2 Mon Sep 17 00:00:00 2001
-From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
-Date: Fri, 3 Oct 2025 05:28:41 +0300
-Subject: [PATCH 5/5] net: airoha: increase the number of rx network buffers
-
-According to commit 997786bbf473 ("drivers/net/airoha_eth: fix stalling
-in package receiving") the minimal possible value of SYS_RX_ETH_BUFFER
-is 4. Unfortunately it's too small for reliable ping.
-
-Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
---
- configs/an7581_evb_defconfig | 1 +
- configs/an7583_evb_defconfig | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig
-index c74247e13db..aa1a30aad6a 100644
--- a/configs/an7581_evb_defconfig
-+++ b/configs/an7581_evb_defconfig
-@@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y
- CONFIG_SYS_RELOC_GD_ENV_ADDR=y
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
- CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_SYS_RX_ETH_BUFFER=8
- CONFIG_REGMAP=y
- CONFIG_SYSCON=y
- CONFIG_CLK=y
-diff --git a/configs/an7583_evb_defconfig b/configs/an7583_evb_defconfig
-index 057104b93af..c67444ae8bf 100644
--- a/configs/an7583_evb_defconfig
-+++ b/configs/an7583_evb_defconfig
-@@ -44,6 +44,7 @@ CONFIG_ENV_IS_IN_MMC=y
- CONFIG_SYS_RELOC_GD_ENV_ADDR=y
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
- CONFIG_NET_RANDOM_ETHADDR=y
-+CONFIG_SYS_RX_ETH_BUFFER=8
- CONFIG_REGMAP=y
- CONFIG_SYSCON=y
- CONFIG_CLK=y
-- 
-2.51.0
-
--- a/package/boot/uboot-airoha/patches/900-airoha-enable-UBI-support-and-define-default-partiti.patch
+++ b/package/boot/uboot-airoha/patches/900-airoha-enable-UBI-support-and-define-default-partiti.patch
@@ -1,113 +0,0 @@
-From 28a72d957b897e7f7212c11f99052a32b0f6abc4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 28 May 2025 03:10:53 +0200
-Subject: [PATCH 1/2] airoha: enable UBI support and define default partition
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- arch/arm/dts/an7581-u-boot.dtsi | 16 ++++++++++++++++
- arch/arm/dts/an7583-evb.dts     | 22 ++++++++++++++++++++++
- configs/an7581_evb_defconfig    | 16 ++++++++++++++++
- configs/an7583_evb_defconfig    | 16 ++++++++++++++++
- 4 files changed, 70 insertions(+)
-
--- a/arch/arm/dts/an7581-u-boot.dtsi
-+++ b/arch/arm/dts/an7581-u-boot.dtsi
-@@ -76,6 +76,22 @@
- 				spi-max-frequency = <50000000>;
- 				spi-tx-bus-width = <1>;
- 				spi-rx-bus-width = <2>;
-+
-+				partitions {
-+					compatible = "fixed-partitions";
-+					#address-cells = <1>;
-+					#size-cells = <1>;
-+
-+					bl2@0 {
-+						label = "bl2";
-+						reg = <0x0 0x20000>;
-+					};
-+
-+					ubi@20000 {
-+						label = "ubi";
-+						reg = <0x20000 0x0>;
-+					};
-+				};
- 			};
- 		};
- 
--- a/arch/arm/dts/an7583-evb.dts
-+++ b/arch/arm/dts/an7583-evb.dts
-@@ -46,6 +46,28 @@
- 	};
- };
- 
-+&snfi {
-+	status = "okay";
-+};
-+
-+&spi_nand {
-+	partitions {
-+		compatible = "fixed-partitions";
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+
-+		bl2@0 {
-+			label = "bl2";
-+			reg = <0x0 0x20000>;
-+		};
-+
-+		ubi@20000 {
-+			label = "ubi";
-+			reg = <0x20000 0x0>;
-+		};
-+	};
-+};
-+
- &pcie0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&pcie0_rst_pins>;
--- a/configs/an7581_evb_defconfig
-+++ b/configs/an7581_evb_defconfig
-@@ -77,3 +77,19 @@ CONFIG_SPI=y
- CONFIG_DM_SPI=y
- CONFIG_AIROHA_SNFI_SPI=y
- CONFIG_SHA512=y
-+CONFIG_CMD_UBI=y
-+# CONFIG_CMD_UBI_RENAME is not set
-+CONFIG_CMD_UBIFS=y
-+CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_UBI_PART="ubi"
-+CONFIG_ENV_UBI_VOLUME="ubootenv"
-+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_UBI_VID_OFFSET=0
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_MODULE=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_LIMIT=20
-+# CONFIG_MTD_UBI_FASTMAP is not set
-+CONFIG_UBI_BLOCK=y
-+# CONFIG_UBIFS_SILENCE_MSG is not set
-+# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
--- a/configs/an7583_evb_defconfig
-+++ b/configs/an7583_evb_defconfig
-@@ -79,3 +79,19 @@ CONFIG_SHA512=y
- CONFIG_AIROHA_ETH=y
- CONFIG_MMC_MTK=y
- CONFIG_AIROHA_SNFI_SPI=y
-+CONFIG_CMD_UBI=y
-+# CONFIG_CMD_UBI_RENAME is not set
-+CONFIG_CMD_UBIFS=y
-+CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_UBI_PART="ubi"
-+CONFIG_ENV_UBI_VOLUME="ubootenv"
-+CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_UBI_VID_OFFSET=0
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_MODULE=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_LIMIT=20
-+# CONFIG_MTD_UBI_FASTMAP is not set
-+CONFIG_UBI_BLOCK=y
-+# CONFIG_UBIFS_SILENCE_MSG is not set
-+# CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
--- a/package/boot/uboot-airoha/patches/901-airoha-add-default-configuration.patch
+++ b/package/boot/uboot-airoha/patches/901-airoha-add-default-configuration.patch
@@ -1,45 +0,0 @@
-From f85e675d7be222d88246bfdb42a1faac92f1eb63 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 28 May 2025 03:18:32 +0200
-Subject: [PATCH 2/2] airoha: add default configuration
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
- configs/an7581_evb_defconfig | 2 ++
- configs/an7583_evb_defconfig | 2 ++
- defenvs/an7581_rfb_env       | 3 +++
- defenvs/an7583_rfb_env       | 3 +++
- 4 files changed, 10 insertions(+)
- create mode 100644 defenvs/an7581_rfb_env
- create mode 100644 defenvs/an7583_rfb_env
-
--- a/configs/an7581_evb_defconfig
-+++ b/configs/an7581_evb_defconfig
-@@ -93,3 +93,5 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
- CONFIG_UBI_BLOCK=y
- # CONFIG_UBIFS_SILENCE_MSG is not set
- # CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_DEFAULT_ENV_FILE="defenvs/an7581_rfb_env"
--- a/configs/an7583_evb_defconfig
-+++ b/configs/an7583_evb_defconfig
-@@ -95,3 +95,5 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
- CONFIG_UBI_BLOCK=y
- # CONFIG_UBIFS_SILENCE_MSG is not set
- # CONFIG_UBIFS_SILENCE_DEBUG_DUMP is not set
-+CONFIG_USE_DEFAULT_ENV_FILE=y
-+CONFIG_DEFAULT_ENV_FILE="defenvs/an7583_rfb_env"
--- /dev/null
-+++ b/defenvs/an7581_rfb_env
-@@ -0,0 +1,4 @@
-+loadaddr=0x81800000
-+ipaddr=192.168.1.1
-+serverip=192.168.1.10
-+bootargs=ubi.mtd=ubi root=/dev/ubiblock0_5 rootwait
--- /dev/null
-+++ b/defenvs/an7583_rfb_env
-@@ -0,0 +1,4 @@
-+loadaddr=0x81800000
-+ipaddr=192.168.1.1
-+serverip=192.168.1.10
-+bootargs=ubi.mtd=ubi root=/dev/ubiblock0_5 rootwait
--- a/package/boot/uboot-ath79/Makefile
+++ b/package/boot/uboot-ath79/Makefile
@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk

-PKG_VERSION:=2025.10
-PKG_HASH:=b4f032848e56cc8f213ad59f9132c084dbbb632bc29176d024e58220e0efdf4a
+PKG_VERSION:=2025.04
+PKG_HASH:=439d3bef296effd54130be6a731c5b118be7fddd7fcc663ccbc5fb18294d8718

 UBOOT_USE_INTREE_DTC:=1

--- a/package/boot/uboot-ath79/patches/400-ath79-add-support-for-NEC-AR9344-Aterm-series.patch
+++ b/package/boot/uboot-ath79/patches/400-ath79-add-support-for-NEC-AR9344-Aterm-series.patch
@@ -22,7 +22,7 @@ Subject: [PATCH] ath79: add support for NEC AR9344 Aterm series

 --- a/arch/mips/dts/Makefile
 +++ b/arch/mips/dts/Makefile
-@@ -23,6 +23,7 @@ dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY
+@@ -24,6 +24,7 @@ dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY
 dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
 dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
 dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
--- a/package/boot/uboot-ath79/patches/401-mips-ath79-add-support-for-NEC-QCA9558-Aterm-series.patch
+++ b/package/boot/uboot-ath79/patches/401-mips-ath79-add-support-for-NEC-QCA9558-Aterm-series.patch
@@ -23,7 +23,7 @@ mips: ath79: cleanup defconfig for NEC QCA9558 Aterm series

 --- a/arch/mips/dts/Makefile
 +++ b/arch/mips/dts/Makefile
-@@ -24,6 +24,7 @@ dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) +=
+@@ -25,6 +25,7 @@ dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) +=
 dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
 dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
 dtb-$(CONFIG_BOARD_NEC_AR9344_ATERM) += nec,ar9344-aterm.dtb
--- a/package/boot/uboot-bcm53xx/Makefile
+++ b/package/boot/uboot-bcm53xx/Makefile
@@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk

 PKG_VERSION:=2024.01
 PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
-PKG_RELEASE:=2
+PKG_RELEASE:=$(AUTORELEASE)

 include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk
--- a/package/boot/uboot-bmips/Makefile
+++ b/package/boot/uboot-bmips/Makefile
@@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk

 PKG_VERSION:=2024.04
 PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
-PKG_RELEASE:=1
+PKG_RELEASE:=$(AUTORELEASE)

 include $(INCLUDE_DIR)/u-boot.mk
 include $(INCLUDE_DIR)/package.mk
--- a/package/boot/uboot-d1/patches/310-fix-swig-4-3-0-SWIG_AppendOutput-keeps-signature.patch
+++ b/package/boot/uboot-d1/patches/310-fix-swig-4-3-0-SWIG_AppendOutput-keeps-signature.patch
@@ -1,57 +0,0 @@
-From a63456b9191fae2fe49f4b121e025792022e3950 Mon Sep 17 00:00:00 2001
-From: Markus Volk <f_l_k@t-online.de>
-Date: Wed, 30 Oct 2024 06:07:16 +0100
-Subject: [PATCH] scripts/dtc/pylibfdt/libfdt.i_shipped: Use SWIG_AppendOutput
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Swig has changed language specific AppendOutput functions. The helper
-macro SWIG_AppendOutput remains unchanged. Use that instead
-of SWIG_Python_AppendOutput, which would require an extra parameter
-since swig 4.3.0.
-
-/home/flk/poky/build-test/tmp/work/qemux86_64-poky-linux/u-boot/2024.10/git/arch/x86/cpu/u-boot-64.lds
-| scripts/dtc/pylibfdt/libfdt_wrap.c: In function ‘_wrap_fdt_next_node’:
-| scripts/dtc/pylibfdt/libfdt_wrap.c:5581:17: error: too few arguments to function ‘SWIG_Python_AppendOutput’
-|  5581 |     resultobj = SWIG_Python_AppendOutput(resultobj, val);
-|       |                 ^~~~~~~~~~~~~~~~~~~~~~~~
-
-Signed-off-by: Markus Volk <f_l_k@t-online.de>
-Reported-by: Rudi Heitbaum <rudi@heitbaum.com>
-Link: https://github.com/dgibson/dtc/pull/154
---
- scripts/dtc/pylibfdt/libfdt.i_shipped | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped
-index 56cc5d48f4f9..e4659489a96a 100644
--- a/scripts/dtc/pylibfdt/libfdt.i_shipped
-+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped
-@@ -1037,7 +1037,7 @@ typedef uint32_t fdt32_t;
- 			fdt_string(fdt1, fdt32_to_cpu($1->nameoff)));
- 		buff = PyByteArray_FromStringAndSize(
- 			(const char *)($1 + 1), fdt32_to_cpu($1->len));
-		resultobj = SWIG_Python_AppendOutput(resultobj, buff);
-+		resultobj = SWIG_AppendOutput(resultobj, buff);
- 	}
- }
- 
-@@ -1076,7 +1076,7 @@ typedef uint32_t fdt32_t;
- 
- %typemap(argout) int *depth {
-         PyObject *val = Py_BuildValue("i", *arg$argnum);
-        resultobj = SWIG_Python_AppendOutput(resultobj, val);
-+        resultobj = SWIG_AppendOutput(resultobj, val);
- }
- 
- %apply int *depth { int *depth };
-@@ -1092,7 +1092,7 @@ typedef uint32_t fdt32_t;
-            if (PyTuple_GET_SIZE(resultobj) == 0)
-               resultobj = val;
-            else
-              resultobj = SWIG_Python_AppendOutput(resultobj, val);
-+              resultobj = SWIG_AppendOutput(resultobj, val);
-         }
- }
- 
--- a/package/boot/uboot-layerscape/Makefile
+++ b/package/boot/uboot-layerscape/Makefile
@@ -151,9 +151,6 @@ UBOOT_TARGETS := \
  fsl_ls1021a-twr-sdboot \
  fsl_ls1021a-iot-sdboot

-UBOOT_CUSTOMIZE_CONFIG := \
-	--disable TOOLS_MKEFICAPSULE
-
 define Build/InstallDev
 	$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
 	$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) \
--- a/package/boot/uboot-mediatek/Makefile
+++ b/package/boot/uboot-mediatek/Makefile
@@ -1,8 +1,8 @@
 include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk

-PKG_VERSION:=2025.10
-PKG_HASH:=b4f032848e56cc8f213ad59f9132c084dbbb632bc29176d024e58220e0efdf4a
+PKG_VERSION:=2025.07
+PKG_HASH:=0f933f6c5a426895bf306e93e6ac53c60870e4b54cda56d95211bec99e63bec7
 PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host

 UBOOT_USE_INTREE_DTC:=1
@@ -243,19 +243,7 @@ define U-Boot/mt7981_cmcc_a10
  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
 endef

-define U-Boot/mt7981_cmcc_rax3000m-emmc-ddr3
-  NAME:=CMCC RAX3000M
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=cmcc_rax3000m
-  UBOOT_CONFIG:=mt7981_cmcc_rax3000m-emmc
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=emmc
-  BL2_SOC:=mt7981
-  BL2_DDRTYPE:=ddr3-1866mhz
-  DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr3-1866mhz
-endef
-
-define U-Boot/mt7981_cmcc_rax3000m-emmc-ddr4
+define U-Boot/mt7981_cmcc_rax3000m-emmc
  NAME:=CMCC RAX3000M
  BUILD_SUBTARGET:=filogic
  BUILD_DEVICES:=cmcc_rax3000m
@@ -267,19 +255,7 @@ define U-Boot/mt7981_cmcc_rax3000m-emmc-ddr4
  DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr4
 endef

-define U-Boot/mt7981_cmcc_rax3000m-nand-ddr3
-  NAME:=CMCC RAX3000M
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=cmcc_rax3000m
-  UBOOT_CONFIG:=mt7981_cmcc_rax3000m-nand
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
-  BL2_SOC:=mt7981
-  BL2_DDRTYPE:=ddr3-1866mhz
-  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3-1866mhz
-endef
-
-define U-Boot/mt7981_cmcc_rax3000m-nand-ddr4
+define U-Boot/mt7981_cmcc_rax3000m-nand
  NAME:=CMCC RAX3000M
  BUILD_SUBTARGET:=filogic
  BUILD_DEVICES:=cmcc_rax3000m
@@ -291,18 +267,6 @@ define U-Boot/mt7981_cmcc_rax3000m-nand-ddr4
  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr4
 endef

-define U-Boot/mt7981_comfast_cf-wr632ax
-  NAME:=COMFAST CF-WR632AX
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=comfast_cf-wr632ax-ubootmod
-  UBOOT_CONFIG:=mt7981_comfast_cf-wr632ax
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
-  BL2_SOC:=mt7981
-  BL2_DDRTYPE:=ddr3
-  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
-endef
-
 define U-Boot/mt7981_cudy_tr3000-v1
  NAME:=Cudy TR3000 v1
  BUILD_SUBTARGET:=filogic
@@ -374,18 +338,6 @@ define U-Boot/mt7981_jcg_q30-pro
  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
 endef

-define U-Boot/mt7981_konka_komi-a31
-  NAME:=Konka KOMI A31
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=konka_komi-a31
-  UBOOT_CONFIG:=mt7981_konka_komi-a31
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
-  BL2_SOC:=mt7981
-  BL2_DDRTYPE:=ddr3
-  DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
-endef
-
 define U-Boot/mt7981_netis_nx31
  NAME:=netis NX31
  BUILD_SUBTARGET:=filogic
@@ -580,18 +532,6 @@ define U-Boot/mt7986_rfb
  DEPENDS:=+trusted-firmware-a-mt7986-sdmmc-ddr4
 endef

-define U-Boot/mt7986_acer_predator-w6x
-  NAME:=Acer Predator Connect W6x
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=acer_predator-w6x-ubootmod
-  UBOOT_CONFIG:=mt7986_acer_predator-w6x
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand
-  BL2_SOC:=mt7986
-  BL2_DDRTYPE:=ddr4
-  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4
-endef
-
 define U-Boot/mt7986_bananapi_bpi-r3-emmc
  NAME:=BananaPi BPi-R3
  BUILD_SUBTARGET:=filogic
@@ -797,55 +737,6 @@ define U-Boot/mt7986_zyxel_ex5601-t0
  DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
 endef

-define U-Boot/mt7987_bananapi_bpi-r4-lite-emmc
-  NAME:=BananaPi BPi-R4 Lite
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=bananapi_bpi-r4-lite
-  UBOOT_CONFIG:=mt7987a_bpi-r4-lite-emmc
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=emmc
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-emmc-comb
-endef
-
-define U-Boot/mt7987_bananapi_bpi-r4-lite-sdmmc
-  NAME:=BananaPi BPi-R4 Lite
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=bananapi_bpi-r4-lite
-  UBOOT_CONFIG:=mt7987a_bpi-r4-lite-sd
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=sdmmc
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-sdmmc-comb
-endef
-
-define U-Boot/mt7987_bananapi_bpi-r4-lite-snand
-  NAME:=BananaPi BPi-R4 Lite
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=bananapi_bpi-r4-lite
-  UBOOT_CONFIG:=mt7987a_bpi-r4-lite-snand
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand2-ubi
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-spim-nand2-ubi-comb
-endef
-
-define U-Boot/mt7987_bananapi_bpi-r4-lite-nor
-  NAME:=BananaPi BPi-R4 Lite
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=bananapi_bpi-r4-lite
-  UBOOT_CONFIG:=mt7987a_bpi-r4-lite-nor
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=nor
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-nor-comb
-  FIP_COMPRESS:=1
-endef
-
 define U-Boot/mt7988_arcadyan_mozart
  NAME:=Arcadyan Mozart
  BUILD_SUBTARGET:=filogic
@@ -942,42 +833,6 @@ define U-Boot/mt7988_bananapi_bpi-r4-poe-snand
  DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb
 endef

-define U-Boot/mt7987_rfb-emmc
-  NAME:=MT7987 Reference Board
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=mediatek_mt7987a-rfb
-  UBOOT_CONFIG:=mt7987_emmc_rfb
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=sdmmc
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-emmc-comb
-endef
-
-define U-Boot/mt7987_rfb-spim-nand
-  NAME:=MT7987 Reference Board
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=mediatek_mt7987a-rfb
-  UBOOT_CONFIG:=mt7987_rfb
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=spim-nand0-ubi
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-spim-nand0-ubi-comb
-endef
-
-define U-Boot/mt7987_rfb-sd
-  NAME:=MT7987 Reference Board
-  BUILD_SUBTARGET:=filogic
-  BUILD_DEVICES:=mediatek_mt7987a-rfb
-  UBOOT_CONFIG:=mt7987_sd_rfb
-  UBOOT_IMAGE:=u-boot.fip
-  BL2_BOOTDEV:=sdmmc
-  BL2_SOC:=mt7987
-  BL2_DDRTYPE:=comb
-  DEPENDS:=+trusted-firmware-a-mt7987-sdmmc-comb
-endef
-
 define U-Boot/mt7988_rfb-spim-nand
  NAME:=MT7988 Reference Board
  BUILD_SUBTARGET:=filogic
@@ -1061,11 +916,8 @@ UBOOT_TARGETS := \
 	mt7629_rfb \
 	mt7981_abt_asr3000 \
 	mt7981_cmcc_a10 \
-	mt7981_cmcc_rax3000m-emmc-ddr3 \
-	mt7981_cmcc_rax3000m-emmc-ddr4 \
-	mt7981_cmcc_rax3000m-nand-ddr3 \
-	mt7981_cmcc_rax3000m-nand-ddr4 \
-	mt7981_comfast_cf-wr632ax \
+	mt7981_cmcc_rax3000m-emmc \
+	mt7981_cmcc_rax3000m-nand \
 	mt7981_cudy_tr3000-v1 \
 	mt7981_gatonetworks_gdsp \
 	mt7981_glinet_gl-mt2500 \
@@ -1073,7 +925,6 @@ UBOOT_TARGETS := \
 	mt7981_glinet_gl-xe3000 \
 	mt7981_h3c_magic-nx30-pro \
 	mt7981_jcg_q30-pro \
-	mt7981_konka_komi-a31 \
 	mt7981_netis_nx31 \
 	mt7981_nokia_ea0326gmp \
 	mt7981_openwrt_one-snand \
@@ -1088,7 +939,6 @@ UBOOT_TARGETS := \
 	mt7981_snr_snr-cpe-ax2 \
 	mt7981_xiaomi_mi-router-ax3000t \
 	mt7981_xiaomi_mi-router-wr30u \
-	mt7986_acer_predator-w6x \
 	mt7986_bananapi_bpi-r3-emmc \
 	mt7986_bananapi_bpi-r3-sdmmc \
 	mt7986_bananapi_bpi-r3-snand \
@@ -1107,13 +957,6 @@ UBOOT_TARGETS := \
 	mt7986_xiaomi_redmi-router-ax6000 \
 	mt7986_zyxel_ex5601-t0 \
 	mt7986_rfb \
-	mt7987_bananapi_bpi-r4-lite-emmc \
-	mt7987_bananapi_bpi-r4-lite-sdmmc \
-	mt7987_bananapi_bpi-r4-lite-snand \
-	mt7987_bananapi_bpi-r4-lite-nor \
-	mt7987_rfb-emmc \
-	mt7987_rfb-sd \
-	mt7987_rfb-spim-nand \
 	mt7988_arcadyan_mozart \
 	mt7988_asus_zenwifi-bt8 \
 	mt7988_bananapi_bpi-r4-emmc \
--- a/package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch
+++ b/package/boot/uboot-mediatek/patches/001-mtd-spinand-winbond-add-Winbond-W25N04KV-flash-suppo.patch
@@ -1,7 +1,7 @@
-From 00e8038b8be74d599f7bc8078731cc2505832f57 Mon Sep 17 00:00:00 2001
+From fe37fb8214e40ea64cf03453d112527b629fb08a Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 3 Jun 2025 10:47:15 +0200
-Subject: [PATCH 2/2] mtd: spinand: winbond: add Winbond W25N04KV flash support
+Date: Sat, 7 Jun 2025 23:11:21 +0200
+Subject: [PATCH] mtd: spinand: winbond: add Winbond W25N04KV flash support

 Add Winbond W25N04KV flash support that use a different value to detect
 ECC bitflip.
@@ -25,7 +25,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 #define WINBOND_CFG_BUF_READ		BIT(3)
 
-+#define W25N04KV_STATUS_ECC_5_8_BITFLIPS FIELD_PREP_CONST(STATUS_ECC_MASK, 0x3)
+#define W25N04KV_STATUS_ECC_5_8_BITFLIPS GENMASK(5, 4)
 +
 static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
--- a/package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch
+++ b/package/boot/uboot-mediatek/patches/002-mtd-spinand-gigadevice-sync-supported-chips-with-lin.patch
@@ -0,0 +1,245 @@
+From 506ceddffdc40acf709822b678b986e2e22c5056 Mon Sep 17 00:00:00 2001
+From: Chuanhong Guo <gch981213@gmail.com>
+Date: Wed, 1 May 2024 15:45:23 +0800
+Subject: [PATCH] mtd/spinand: gigadevice: sync supported chips with linux 6.9
+
+Adding support for:
+GD5F1GQ4RExxG
+GD5F2GQ4UExxG
+GD5F2GQ4RExxG
+GD5F1GQ5RExxG
+GD5F2GQ5UExxG
+GD5F2GQ5RExxG
+GD5F4GQ6UExxG
+GD5F4GQ6RExxG
+GD5F1GM7UExxG
+GD5F1GM7RExxG
+GD5F2GM7UExxG
+GD5F2GM7RExxG
+GD5F4GM8UExxG
+GD5F4GM8RExxG
+GD5F2GQ5xExxH
+GD5F1GQ5RExxH
+GD5F1GQ4RExxH
+
+Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
+---
+ drivers/mtd/nand/spi/gigadevice.c | 188 +++++++++++++++++++++++++++++-
+ 1 file changed, 187 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
+@@ -43,6 +43,22 @@ static SPINAND_OP_VARIANTS(read_cache_va
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ 		SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+ 
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
+		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+ static SPINAND_OP_VARIANTS(write_cache_variants,
+ 		SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ 		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+@@ -329,6 +345,36 @@ static const struct spinand_info gigadev
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ4RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ4UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ4RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+ 	SPINAND_INFO("GD5F1GQ4UFxxG",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+@@ -343,12 +389,152 @@ static const struct spinand_info gigadev
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
+ 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+ 		     NAND_ECCREQ(4, 512),
+-		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+ 		     SPINAND_HAS_QE_BIT,
+ 		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ 				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ5RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GQ6UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GQ6RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq5xexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GM7UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GM7RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GM7UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GM7RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GM8UExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F4GM8RExxG",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
+		     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F2GQ5xExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ5RExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+	SPINAND_INFO("GD5F1GQ4RExxH",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9),
+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(4, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_QE_BIT,
+		     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+				     gd5fxgq4uexxg_ecc_get_status)),
+ };
+ 
+ static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
--- a/package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch
+++ b/package/boot/uboot-mediatek/patches/003-net-mediatek-correct-the-AN8855-TPID-value-in-port-i.patch
@@ -0,0 +1,26 @@
+From dc495442ba610b190775122a31f958ad74229262 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Tue, 8 Jul 2025 17:53:48 +0800
+Subject: [PATCH] net: mediatek: correct the AN8855 TPID value in port
+ isolation settings
+
+The TPID value should be 0x9100 instead of 0x8100 according to the
+datasheet.
+
+Fixes: cedafee9ff3 (net: mediatek: add support for Airoha AN8855 ethernet switch)
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/net/mtk_eth/an8855.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/mtk_eth/an8855.c
+++ b/drivers/net/mtk_eth/an8855.c
+@@ -909,7 +909,7 @@ static void an8855_port_isolation(struct
+ 
+ 		/* Set port mode to user port */
+ 		an8855_reg_write(priv, AN8855_PVC(i),
+-				 (0x8100 << AN8855_STAG_VPID_S) |
+				 (0x9100 << AN8855_STAG_VPID_S) |
+ 				 (VLAN_ATTR_USER << AN8855_VLAN_ATTR_S));
+ 	}
+ }
--- a/package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch
+++ b/package/boot/uboot-mediatek/patches/004-01-serial-mediatek-fix-register-names-and-offsets.patch
@@ -0,0 +1,44 @@
+From 6e15d3f91aa698798578d39a6d9e292fcc5c577f Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Fri, 23 May 2025 17:25:55 +0800
+Subject: [PATCH] serial: mediatek: fix register names and offsets
+
+Fix UART register names and offsets according to the programming
+guide to allow implementing some enhanced features.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/serial/serial_mtk.c | 17 ++++++++++++-----
+ 1 file changed, 12 insertions(+), 5 deletions(-)
+
+--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
+@@ -30,16 +30,23 @@ struct mtk_serial_regs {
+ 	u32 mcr;
+ 	u32 lsr;
+ 	u32 msr;
+-	u32 spr;
+-	u32 mdr1;
+	u32 scr;
+	u32 autobaud_en;
+ 	u32 highspeed;
+ 	u32 sample_count;
+ 	u32 sample_point;
+	u32 autobaud_reg;
+	u32 ratefix_ad;
+	u32 autobaud_sample;
+	u32 guard;
+	u32 escape_dat;
+	u32 escape_en;
+	u32 sleep_en;
+	u32 dma_en;
+	u32 rxtri_ad;
+ 	u32 fracdiv_l;
+ 	u32 fracdiv_m;
+-	u32 escape_en;
+-	u32 guard;
+-	u32 rx_sel;
+	u32 fcr_rd;
+ };
+ 
+ #define thr rbr
--- a/package/boot/uboot-mediatek/patches/004-02-serial-mediatek-enable-baudrate-accuracy-compensatio.patch
+++ b/package/boot/uboot-mediatek/patches/004-02-serial-mediatek-enable-baudrate-accuracy-compensatio.patch
@@ -0,0 +1,81 @@
+From 6952209ef220138189dd261d06441e1b2d50e994 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Fri, 23 May 2025 17:26:02 +0800
+Subject: [PATCH] serial: mediatek: enable baudrate accuracy compensation
+
+The high-speed UART from MediaTek supports baudrate accuracy
+compensation when using high-speed mode 3.
+
+This is done by calculating the first digit of the fraction part of
+sample count value. The fraction value will be then used as the
+reference to insert 0 to 10 sample cycle(s) to one frame (assume
+that frame format is 8n1, i.e. 10 bits per frame).
+
+The fracdiv_[l/m] registers are used to determine whether a bit in one frame
+should be inserted with one sample cycle.
+
+With typical 40MHz source clock, the actual baudrates with/without
+accuracy compensation are:
+
+Ideal    w/o compensation w/ compensation
+======== ================ ===============
+9600     9603             9600
+115200   114942           115207
+921600   930232           921659
+3000000  3076923          3007519
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/serial/serial_mtk.c | 24 +++++++++++++++++++++---
+ 1 file changed, 21 insertions(+), 3 deletions(-)
+
+--- a/drivers/serial/serial_mtk.c
+++ b/drivers/serial/serial_mtk.c
+@@ -99,10 +99,18 @@ struct mtk_serial_priv {
+ 	bool upstream_highspeed_logic;
+ };
+ 
+static const unsigned short fraction_l_mapping[] = {
+	0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF
+};
+
+static const unsigned short fraction_m_mapping[] = {
+	0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3
+};
+
+ static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud,
+ 			       uint clk_rate)
+ {
+-	u32 quot, realbaud, samplecount = 1;
+	u32 quot, realbaud, samplecount = 1, fraction, frac_l = 0, frac_m = 0;
+ 
+ 	/* Special case for low baud clock */
+ 	if (baud <= 115200 && clk_rate == 12000000) {
+@@ -147,7 +155,13 @@ use_hs3:
+ 		writel(3, &priv->regs->highspeed);
+ 
+ 		quot = DIV_ROUND_UP(clk_rate, 256 * baud);
+-		samplecount = DIV_ROUND_CLOSEST(clk_rate, quot * baud);
+		samplecount = clk_rate / (quot * baud);
+
+		fraction = ((clk_rate * 100) / quot / baud) % 100;
+		fraction = DIV_ROUND_CLOSEST(fraction, 10);
+
+		frac_l = fraction_l_mapping[fraction];
+		frac_m = fraction_m_mapping[fraction];
+ 	}
+ 
+ set_baud:
+@@ -159,7 +173,11 @@ set_baud:
+ 
+ 	/* set highspeed mode sample count & point */
+ 	writel(samplecount - 1, &priv->regs->sample_count);
+-	writel((samplecount - 2) >> 1, &priv->regs->sample_point);
+	writel((samplecount >> 1) - 1, &priv->regs->sample_point);
+
+	/* set baudrate fraction compensation */
+	writel(frac_l, &priv->regs->fracdiv_l);
+	writel(frac_m, &priv->regs->fracdiv_m);
+ }
+ 
+ static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
--- a/package/boot/uboot-mediatek/patches/005-clk-mediatek-add-dummy-clk-enable-disable-ops-for-ap.patch
+++ b/package/boot/uboot-mediatek/patches/005-clk-mediatek-add-dummy-clk-enable-disable-ops-for-ap.patch
@@ -0,0 +1,114 @@
+From 1bf212129768d65a47145209c65bf37b6082d718 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Tue, 6 May 2025 16:12:20 +0800
+Subject: [PATCH] clk: mediatek: add dummy clk enable/disable ops for
+ apmixedsys clocks
+
+Starting from commit ac30d90f336 (clk: Ensure the parent clocks are enabled
+while reparenting), MediaTek filogic platforms will crash on booting when
+initializing mmc devices.
+
+The root cause is that to simplify the code, we reused the topckgen ops for
+apmixedsys clocks as they share the get_rate with topckgen clocks while the
+clk enable/disable ops are not available for apmixedsys clocks.
+
+Now that a clock will be enabled first before reparenting, we have to add
+dummy enable/disable ops for apmixedsys to avoid unexpected behavior when
+apmixedsys clocks are the parent clock of the to-be-reparenting clocks.
+
+Fixes: 40746bf429d (clk: mediatek: add clock driver support for MediaTek MT7981 SoC)
+Fixes: 37d5a9a29dc (clk: mediatek: add clock driver support for MediaTek MT7986 SoC)
+Fixes: ece4e5804f5 (clk: mediatek: add clock driver support for MediaTek MT7987 SoC)
+Fixes: 421436981a2 (clk: mediatek: add clock driver support for MediaTek MT7988 SoC)
+Signed-off-by: Sam Shih <sam.shih@mediatek.com>
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/clk/mediatek/clk-mt7981.c |  2 +-
+ drivers/clk/mediatek/clk-mt7986.c |  2 +-
+ drivers/clk/mediatek/clk-mt7987.c |  2 +-
+ drivers/clk/mediatek/clk-mt7988.c |  2 +-
+ drivers/clk/mediatek/clk-mtk.c    | 11 +++++++++++
+ drivers/clk/mediatek/clk-mtk.h    |  1 +
+ 6 files changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
+@@ -566,7 +566,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ 	.of_match = mt7981_fixed_pll_compat,
+ 	.probe = mt7981_fixed_pll_probe,
+ 	.priv_auto = sizeof(struct mtk_clk_priv),
+-	.ops = &mtk_clk_topckgen_ops,
+	.ops = &mtk_clk_fixed_pll_ops,
+ 	.flags = DM_FLAG_PRE_RELOC,
+ };
+ 
+--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
+@@ -573,7 +573,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ 	.of_match = mt7986_fixed_pll_compat,
+ 	.probe = mt7986_fixed_pll_probe,
+ 	.priv_auto = sizeof(struct mtk_clk_priv),
+-	.ops = &mtk_clk_topckgen_ops,
+	.ops = &mtk_clk_fixed_pll_ops,
+ 	.flags = DM_FLAG_PRE_RELOC,
+ };
+ 
+--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
+@@ -67,7 +67,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ 	.of_match = mt7987_fixed_pll_compat,
+ 	.probe = mt7987_fixed_pll_probe,
+ 	.priv_auto = sizeof(struct mtk_clk_priv),
+-	.ops = &mtk_clk_topckgen_ops,
+	.ops = &mtk_clk_fixed_pll_ops,
+ 	.flags = DM_FLAG_PRE_RELOC,
+ };
+ 
+--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
+@@ -830,7 +830,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ 	.of_match = mt7988_fixed_pll_compat,
+ 	.probe = mt7988_fixed_pll_probe,
+ 	.priv_auto = sizeof(struct mtk_clk_priv),
+-	.ops = &mtk_clk_topckgen_ops,
+	.ops = &mtk_clk_fixed_pll_ops,
+ 	.flags = DM_FLAG_PRE_RELOC,
+ };
+ 
+--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
+@@ -47,6 +47,11 @@ static int mtk_clk_get_id(struct clk *cl
+ 	return id;
+ }
+ 
+static int mtk_dummy_enable(struct clk *clk)
+{
+	return 0;
+}
+
+ static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate)
+ {
+ 	u32 bit = BIT(gate->shift);
+@@ -752,6 +757,12 @@ const struct clk_ops mtk_clk_apmixedsys_
+ 	.get_rate = mtk_apmixedsys_get_rate,
+ };
+ 
+const struct clk_ops mtk_clk_fixed_pll_ops = {
+	.enable = mtk_dummy_enable,
+	.disable = mtk_dummy_enable,
+	.get_rate = mtk_topckgen_get_rate,
+};
+
+ const struct clk_ops mtk_clk_topckgen_ops = {
+ 	.enable = mtk_clk_mux_enable,
+ 	.disable = mtk_clk_mux_disable,
+--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
+@@ -283,6 +283,7 @@ struct mtk_cg_priv {
+ };
+ 
+ extern const struct clk_ops mtk_clk_apmixedsys_ops;
+extern const struct clk_ops mtk_clk_fixed_pll_ops;
+ extern const struct clk_ops mtk_clk_topckgen_ops;
+ extern const struct clk_ops mtk_clk_infrasys_ops;
+ extern const struct clk_ops mtk_clk_gate_ops;
--- a/package/boot/uboot-mediatek/patches/006-env-Fix-possible-out-of-bound-access-in-env_do_env_s.patch
+++ b/package/boot/uboot-mediatek/patches/006-env-Fix-possible-out-of-bound-access-in-env_do_env_s.patch
@@ -0,0 +1,55 @@
+From 0ffd456516b5f0c126c9705d6b2368a45ee2353f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 29 Jun 2025 15:21:18 +0200
+Subject: [PATCH] env: Fix possible out-of-bound access in env_do_env_set
+
+It was discovered that env_do_env_set() currently suffer from a long
+time of a possible out-of-bound access for the argv array handling.
+
+The BUG is present in the function env_do_env_set() line:
+
+name = argv[1];
+
+where the function at this point assume the argv at index 1 is always
+present and can't be NULL. Aside from the fact that it's always
+better to validate argv entry with the argc variable, situation where
+the argv[1] is NULL is actually possible and not an error condition.
+
+A example of where an out-of-bound access is triggered is with the
+command "askenv - Press ENTER to ...".
+This is a common pattern for bootmenu entry to ask the user input after
+a bootmenu command succeeded.
+
+In the context of such command, the while loop before "name = argv[1];"
+parse the "-" char as an option arg and increment the argv pointer by
+one (to make the rest of the logic code ignore the option argv) and
+decrement argc value.
+
+The while loop logic is correct but at the "name = argv[1];" line, the
+argv have only one element left (the "-" char) and accessing argv[1]
+(aka the secong element from argv pointer) cause an out-of-bound access
+(making the bootloader eventually crash with strchr searching in invalid
+data)
+
+To better handle this and prevent the out-of-bound access, actually
+check the argv entry left (with the use of the argc variable) and exit
+early before doing any kind of array access.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ env/common.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/env/common.c
+++ b/env/common.c
+@@ -82,6 +82,10 @@ int env_do_env_set(int flag, int argc, c
+ 		}
+ 	}
+ 	debug("Final value for argc=%d\n", argc);
+	/* Exit early if we don't have an env to apply */
+	if (argc < 2)
+		return 0;
+
+ 	name = argv[1];
+ 
+ 	if (strchr(name, '=')) {
--- a/package/boot/uboot-mediatek/patches/007-ARM-dts-build-DT-for-MT7987-RFB.patch
+++ b/package/boot/uboot-mediatek/patches/007-ARM-dts-build-DT-for-MT7987-RFB.patch
@@ -1,26 +0,0 @@
-From a4d4096d6b80a2b6f5bc800426380cdc60d9b037 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Thu, 2 Oct 2025 14:57:16 +0100
-Subject: [PATCH] ARM: dts: build DT for MT7987 RFB
-
-Compile the added device tree sources into blobs, which was forgotten
-when adding the source files.
-
-Fixes: 2d6962e0618 (arm: mediatek: add support for MediaTek MT7987 SoC)
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- arch/arm/dts/Makefile | 3 +++
- 1 file changed, 3 insertions(+)
-
--- a/arch/arm/dts/Makefile
-+++ b/arch/arm/dts/Makefile
-@@ -1131,6 +1131,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
- 	mt7986b-sd-rfb.dtb \
- 	mt7986a-emmc-rfb.dtb \
- 	mt7986b-emmc-rfb.dtb \
-+	mt7987a-emmc-rfb.dtb \
-+	mt7987a-rfb.dtb \
-+	mt7987a-sd-rfb.dtb \
- 	mt7988-rfb.dtb \
- 	mt7988-sd-rfb.dtb \
- 	mt8183-pumpkin.dtb \
--- a/package/boot/uboot-mediatek/patches/100-03-mtd-add-a-new-mtd-device-type-for-NMBM.patch
+++ b/package/boot/uboot-mediatek/patches/100-03-mtd-add-a-new-mtd-device-type-for-NMBM.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/mtdparts.c
 +++ b/cmd/mtdparts.c
-@@ -1055,6 +1055,9 @@ int mtd_id_parse(const char *id, const c
+@@ -1054,6 +1054,9 @@ int mtd_id_parse(const char *id, const c
 	} else if (strncmp(p, "spi-nand", 8) == 0) {
 		*dev_type = MTD_DEV_TYPE_SPINAND;
 		p += 8;
--- a/package/boot/uboot-mediatek/patches/100-06-common-board_r-add-support-to-initialize-NMBM-after-.patch
+++ b/package/boot/uboot-mediatek/patches/100-06-common-board_r-add-support-to-initialize-NMBM-after-.patch
@@ -13,7 +13,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/common/board_r.c
 +++ b/common/board_r.c
-@@ -398,6 +398,20 @@ static int initr_nand(void)
+@@ -399,6 +399,20 @@ static int initr_nand(void)
 }
 #endif
 
@@ -34,7 +34,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 #if defined(CONFIG_CMD_ONENAND)
 /* go init the NAND */
 static int initr_onenand(void)
-@@ -713,6 +727,9 @@ static void initcall_run_r(void)
+@@ -718,6 +732,9 @@ static void initcall_run_r(void)
 #if CONFIG_IS_ENABLED(CMD_ONENAND)
 	INITCALL(initr_onenand);
 #endif
--- a/package/boot/uboot-mediatek/patches/100-07-cmd-add-nmbm-command.patch
+++ b/package/boot/uboot-mediatek/patches/100-07-cmd-add-nmbm-command.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1548,6 +1548,12 @@ config CMD_NAND_WATCH
+@@ -1535,6 +1535,12 @@ config CMD_NAND_WATCH
 
 endif # CMD_NAND
 
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	depends on NVME
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -131,6 +131,7 @@ obj-y += legacy-mtd-utils.o
+@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o
 endif
 obj-$(CONFIG_CMD_MUX) += mux.o
 obj-$(CONFIG_CMD_NAND) += nand.o
--- a/package/boot/uboot-mediatek/patches/100-08-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
+++ b/package/boot/uboot-mediatek/patches/100-08-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch
@@ -20,7 +20,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>

 --- a/cmd/mtd.c
 +++ b/cmd/mtd.c
-@@ -741,6 +741,42 @@ out_put_mtd:
+@@ -728,6 +728,42 @@ out_put_mtd:
 	return CMD_RET_SUCCESS;
 }
 
@@ -63,7 +63,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 #ifdef CONFIG_AUTO_COMPLETE
 static int mtd_name_complete(int argc, char *const argv[], char last_char,
 			     int maxv, char *cmdv[])
-@@ -788,6 +824,7 @@ U_BOOT_LONGHELP(mtd,
+@@ -775,6 +811,7 @@ U_BOOT_LONGHELP(mtd,
 	"\n"
 	"Specific functions:\n"
 	"mtd bad                               <name>\n"
@@ -71,7 +71,7 @@ Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
 #if CONFIG_IS_ENABLED(CMD_MTD_OTP)
 	"mtd otpread                           <name> [u|f] <off> <size>\n"
 	"mtd otpwrite                          <name> <off> <hex string>\n"
-@@ -828,4 +865,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
+@@ -815,4 +852,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils"
 		U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase,
 					     mtd_name_complete),
 		U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad,
--- a/package/boot/uboot-mediatek/patches/100-10-cmd-add-a-new-command-for-NAND-flash-debugging.patch
+++ b/package/boot/uboot-mediatek/patches/100-10-cmd-add-a-new-command-for-NAND-flash-debugging.patch
@@ -26,7 +26,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -1548,6 +1548,14 @@ config CMD_NAND_WATCH
+@@ -1535,6 +1535,14 @@ config CMD_NAND_WATCH
 
 endif # CMD_NAND
 
@@ -43,7 +43,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 	bool "nmbm"
 --- a/cmd/Makefile
 +++ b/cmd/Makefile
-@@ -131,6 +131,7 @@ obj-y += legacy-mtd-utils.o
+@@ -130,6 +130,7 @@ obj-y += legacy-mtd-utils.o
 endif
 obj-$(CONFIG_CMD_MUX) += mux.o
 obj-$(CONFIG_CMD_NAND) += nand.o
--- a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
+++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch
@@ -18,19 +18,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -74,7 +74,8 @@ config ENV_IS_DEFAULT
+@@ -74,7 +74,7 @@ config ENV_IS_DEFAULT
 		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
 		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
 		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
-		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD && !ENV_IS_IN_SCSI
-+		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD && \
-+		     !ENV_IS_IN_NMBM && !ENV_IS_IN_SCSI
+-		     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD
+		     !ENV_IS_IN_UBI && !ENV_IS_IN_NMBM && !ENV_IS_IN_MTD
 	select ENV_IS_NOWHERE
 
 config ENV_IS_NOWHERE
-@@ -293,6 +294,21 @@ config ENV_IS_IN_SCSI
- 	  Define this if you have an SCSI device which you want to use for the
- 	  environment.
+@@ -297,6 +297,21 @@ config ENV_IS_IN_NAND
+ 	  Currently, CONFIG_ENV_OFFSET_REDUND is not supported when
+ 	  using CONFIG_ENV_OFFSET_OOB.
 
 +config ENV_IS_IN_NMBM
 +	bool "Environment in a NMBM upper MTD layer"
@@ -50,7 +49,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config ENV_RANGE
 	hex "Length of the region in which the environment can be written"
 	depends on ENV_IS_IN_NAND
-@@ -592,7 +608,7 @@ config ENV_ADDR_REDUND
+@@ -596,7 +611,7 @@ config ENV_ADDR_REDUND
 config ENV_OFFSET
 	hex "Environment offset"
 	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
@@ -71,7 +70,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o
 --- a/env/env.c
 +++ b/env/env.c
-@@ -52,6 +52,9 @@ static enum env_location env_locations[]
+@@ -49,6 +49,9 @@ static enum env_location env_locations[]
 #ifdef CONFIG_ENV_IS_IN_NAND
 	ENVL_NAND,
 #endif
--- a/package/boot/uboot-mediatek/patches/100-12-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
+++ b/package/boot/uboot-mediatek/patches/100-12-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch
@@ -114,7 +114,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
 {
 	size_t i;
-@@ -4488,6 +4582,7 @@ int spi_nor_scan(struct spi_nor *nor)
+@@ -4486,6 +4580,7 @@ int spi_nor_scan(struct spi_nor *nor)
 	nor->write = spi_nor_write_data;
 	nor->read_reg = spi_nor_read_reg;
 	nor->write_reg = spi_nor_write_reg;
--- a/package/boot/uboot-mediatek/patches/100-17-board-mt7981-add-reference-board-using-new-spi-nand-.patch
+++ b/package/boot/uboot-mediatek/patches/100-17-board-mt7981-add-reference-board-using-new-spi-nand-.patch
@@ -18,7 +18,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/arch/arm/dts/Makefile
 +++ b/arch/arm/dts/Makefile
-@@ -1121,6 +1121,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
+@@ -1119,6 +1119,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-bananapi-bpi-r64.dtb \
 	mt7623n-bananapi-bpi-r2.dtb \
 	mt7981-rfb.dtb \
@@ -163,7 +163,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +};
 --- /dev/null
 +++ b/configs/mt7981_snfi_nand_rfb_defconfig
-@@ -0,0 +1,58 @@
+@@ -0,0 +1,57 @@
 +CONFIG_ARM=y
 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_POSITION_INDEPENDENT=y
@@ -173,7 +173,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +CONFIG_NR_DRAM_BANKS=1
 +CONFIG_ENV_SIZE=0x20000
 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
-+# CONFIG_BOARD_INIT is not set
 +CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_TARGET_MT7981=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
--- a/package/boot/uboot-mediatek/patches/100-22-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
+++ b/package/boot/uboot-mediatek/patches/100-22-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch
@@ -15,7 +15,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/drivers/mmc/Kconfig
 +++ b/drivers/mmc/Kconfig
-@@ -862,6 +862,14 @@ config MMC_MTK
+@@ -879,6 +879,14 @@ config MMC_MTK
 	  This is needed if support for any SD/SDIO/MMC devices is required.
 	  If unsure, say N.
 
@@ -32,7 +32,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 config FSL_SDHC_V2_3
 --- a/drivers/mmc/Makefile
 +++ b/drivers/mmc/Makefile
-@@ -84,3 +84,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
+@@ -86,3 +86,7 @@ obj-$(CONFIG_RENESAS_SDHI)		+= tmio-comm
 obj-$(CONFIG_MMC_BCM2835)		+= bcm2835_sdhost.o
 obj-$(CONFIG_MMC_MTK)			+= mtk-sd.o
 obj-$(CONFIG_MMC_SDHCI_F_SDH30)		+= f_sdh30.o
--- a/package/boot/uboot-mediatek/patches/100-25-env-ubi-add-support-to-create-environment-volume-if-.patch
+++ b/package/boot/uboot-mediatek/patches/100-25-env-ubi-add-support-to-create-environment-volume-if-.patch
@@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

 --- a/env/Kconfig
 +++ b/env/Kconfig
-@@ -703,6 +703,12 @@ config ENV_UBI_VOLUME_REDUND
+@@ -687,6 +687,12 @@ config ENV_UBI_VOLUME_REDUND
 	help
 	  Name of the redundant volume that you want to store the environment in.
 
@@ -30,7 +30,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 --- a/env/ubi.c
 +++ b/env/ubi.c
@@ -105,6 +105,18 @@ static int env_ubi_save(void)
- #endif /* CONFIG_ENV_REDUNDANT */
+ #endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */
 #endif /* CONFIG_CMD_SAVEENV */
 
 +int __weak env_ubi_volume_create(const char *volume)
@@ -45,7 +45,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
 +			      UBI_VOL_NUM_AUTO, false);
 +}
 +
- #ifdef CONFIG_ENV_REDUNDANT
+ #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 static int env_ubi_load(void)
 {
@@ -134,6 +146,11 @@ static int env_ubi_load(void)
--- a/package/boot/uboot-mediatek/patches/103-01-mt7622-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-01-mt7622-enable-pstore.patch
@@ -21,8 +21,8 @@
 +			record-size = <0x1000>;
 +		};
 +
-+		/* 192 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */
-+		secmon@43000000 {
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon@43000000 {
 +			reg = <0x43000000 0x30000>;
 +			no-map;
 +		};
--- a/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-02-mt7981-enable-pstore.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/dts/mt7981.dtsi
 +++ b/arch/arm/dts/mt7981.dtsi
-@@ -33,6 +33,30 @@
+@@ -33,6 +33,35 @@
 		};
 	};
 
@@ -21,11 +21,16 @@
 +			record-size = <0x1000>;
 +		};
 +
-+		/* 192 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */
-+		secmon@43000000 {
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon@43000000 {
 +			reg = <0x43000000 0x30000>;
 +			no-map;
 +		};
+
+		wmcpu_emi: wmcpu-reserved@4fc00000 {
+			no-map;
+			reg = <0x4fc00000 0x00100000>;
+		};
 +	};
 +
 	gpt_clk: gpt_dummy20m {
--- a/package/boot/uboot-mediatek/patches/103-03-mt7986-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-03-mt7986-enable-pstore.patch
@@ -1,6 +1,6 @@
 --- a/arch/arm/dts/mt7986.dtsi
 +++ b/arch/arm/dts/mt7986.dtsi
-@@ -50,6 +50,30 @@
+@@ -50,6 +50,35 @@
 		};
 	};
 
@@ -21,11 +21,16 @@
 +			record-size = <0x1000>;
 +		};
 +
-+		/* 256 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */
-+		secmon@43000000 {
-+			reg = <0x43000000 0x40000>;
+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+		secmon_reserved: secmon@43000000 {
+			reg = <0x43000000 0x30000>;
 +			no-map;
 +		};
+
+		wmcpu_emi: wmcpu-reserved@4fc00000 {
+			no-map;
+			reg = <0x4fc00000 0x00100000>;
+		};
 +	};
 +
 	dummy_clk: dummy12m {
--- a/package/boot/uboot-mediatek/patches/103-04-mt7988-enable-pstore.patch
+++ b/package/boot/uboot-mediatek/patches/103-04-mt7988-enable-pstore.patch
@@ -21,8 +21,8 @@
 +			record-size = <0x1000>;
 +		};
 +
-+		/* 320 KiB reserved for ARM Trusted Firmware (BL31 + BL32) */
-+		secmon@43000000 {
+		/* 320 KiB reserved for ARM Trusted Firmware (BL31+BL32) */
+		secmon_reserved: secmon@43000000 {
 +			reg = <0 0x43000000 0 0x50000>;
 +			no-map;
 +		};
--- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7988_sd_rfb_defconfig
 +++ b/configs/mt7988_sd_rfb_defconfig
-@@ -5,38 +5,77 @@ CONFIG_ARCH_MEDIATEK=y
+@@ -5,37 +5,76 @@ CONFIG_ARCH_MEDIATEK=y
 CONFIG_TEXT_BASE=0x41e00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
@@ -28,7 +28,6 @@
 CONFIG_LOGLEVEL=7
 +CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_LOG=y
- # CONFIG_BOARD_INIT is not set
 +CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="MT7988> "
 +CONFIG_CMD_CPU=y
@@ -74,15 +73,15 @@
 +CONFIG_OF_EMBED=y
 +CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_ENV_REDUNDANT=y
-+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 +CONFIG_VERSION_VARIABLE=y
 +CONFIG_NETCONSOLE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_NETMASK=y
-@@ -45,28 +84,43 @@ CONFIG_USE_SERVERIP=y
+@@ -44,28 +83,43 @@ CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
 CONFIG_PROT_TCP=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -131,7 +130,7 @@
 CONFIG_HEXDUMP=y
 --- a/configs/mt7988_rfb_defconfig
 +++ b/configs/mt7988_rfb_defconfig
-@@ -6,37 +6,77 @@ CONFIG_TEXT_BASE=0x41e00000
+@@ -6,36 +6,76 @@ CONFIG_TEXT_BASE=0x41e00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
@@ -156,7 +155,6 @@
 CONFIG_LOGLEVEL=7
 +CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_LOG=y
- # CONFIG_BOARD_INIT is not set
 +CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="MT7988> "
 +CONFIG_CMD_CPU=y
@@ -203,18 +201,18 @@
 +CONFIG_OF_EMBED=y
 +CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 +CONFIG_ENV_UBI_PART="ubi"
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 +CONFIG_VERSION_VARIABLE=y
 +CONFIG_NETCONSOLE=y
 CONFIG_USE_IPADDR=y
 CONFIG_IPADDR="192.168.1.1"
 CONFIG_USE_NETMASK=y
-@@ -45,9 +85,13 @@ CONFIG_USE_SERVERIP=y
+@@ -44,9 +84,13 @@ CONFIG_USE_SERVERIP=y
 CONFIG_SERVERIP="192.168.1.2"
 CONFIG_PROT_TCP=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -230,7 +228,7 @@
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_MTK=y
 CONFIG_MTD=y
-@@ -65,20 +109,31 @@ CONFIG_SPI_FLASH_WINBOND=y
+@@ -64,20 +108,31 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_XMC=y
 CONFIG_SPI_FLASH_XTX=y
 CONFIG_SPI_FLASH_MTD=y
--- a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
+++ b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7981_rfb_defconfig
 +++ b/configs/mt7981_rfb_defconfig
-@@ -31,6 +31,9 @@ CONFIG_CMD_MTD=y
+@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SMC=y
@@ -18,9 +18,9 @@
 CONFIG_NR_DRAM_BANKS=1
 -CONFIG_ENV_SIZE=0x20000
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
- # CONFIG_BOARD_INIT is not set
 CONFIG_SYS_PROMPT="MT7981> "
-@@ -31,8 +30,6 @@ CONFIG_CMD_GPIO=y
+ CONFIG_TARGET_MT7981=y
+@@ -30,8 +29,6 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_MTD=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SMC=y
@@ -29,14 +29,14 @@
 CONFIG_CMD_UBI=y
 CONFIG_CMD_UBI_RENAME=y
 CONFIG_ENV_OVERWRITE=y
-@@ -56,3 +53,4 @@ CONFIG_MTK_POWER_DOMAIN=y
+@@ -55,3 +52,4 @@ CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
 CONFIG_HEXDUMP=y
 +CONFIG_LMB_MAX_REGIONS=64
 --- /dev/null
 +++ b/configs/mt7981_nor_rfb_defconfig
-@@ -0,0 +1,69 @@
+@@ -0,0 +1,68 @@
 +CONFIG_ARM=y
 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 +CONFIG_POSITION_INDEPENDENT=y
@@ -45,7 +45,6 @@
 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 +CONFIG_NR_DRAM_BANKS=1
 +CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
-+# CONFIG_BOARD_INIT is not set
 +CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_TARGET_MT7981=y
 +CONFIG_DEBUG_UART_BASE=0x11002000
--- a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
+++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch
@@ -1,6 +1,6 @@
 --- a/configs/mt7981_emmc_rfb_defconfig
 +++ b/configs/mt7981_emmc_rfb_defconfig
-@@ -8,38 +8,57 @@ CONFIG_NR_DRAM_BANKS=1
+@@ -8,37 +8,56 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x80000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-emmc-rfb"
@@ -20,7 +20,6 @@
 CONFIG_SYS_PBSIZE=1049
 CONFIG_LOGLEVEL=7
 CONFIG_LOG=y
- # CONFIG_BOARD_INIT is not set
 +CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_CMD_CPU=y
@@ -64,7 +63,7 @@
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
-@@ -47,7 +66,13 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+@@ -46,7 +65,13 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
@@ -78,7 +77,7 @@
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_MTK=y
 CONFIG_PHY_FIXED=y
-@@ -60,6 +85,7 @@ CONFIG_MTK_POWER_DOMAIN=y
+@@ -59,6 +84,7 @@ CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
@@ -88,7 +87,7 @@
 CONFIG_HEXDUMP=y
 --- a/configs/mt7981_rfb_defconfig
 +++ b/configs/mt7981_rfb_defconfig
-@@ -6,39 +6,79 @@ CONFIG_TEXT_BASE=0x41e00000
+@@ -6,38 +6,78 @@ CONFIG_TEXT_BASE=0x41e00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
@@ -107,7 +106,6 @@
 CONFIG_SYS_PBSIZE=1049
 CONFIG_LOGLEVEL=7
 CONFIG_LOG=y
- # CONFIG_BOARD_INIT is not set
 +CONFIG_BOARD_LATE_INIT=y
 +CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MT7981> "
@@ -151,11 +149,11 @@
 CONFIG_CMD_UBI_RENAME=y
 CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 +CONFIG_ENV_UBI_PART="ubi"
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
@@ -170,7 +168,7 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-@@ -63,6 +103,7 @@ CONFIG_PINCTRL_MT7981=y
+@@ -62,6 +102,7 @@ CONFIG_PINCTRL_MT7981=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
@@ -180,7 +178,7 @@
 CONFIG_DM_SPI=y
 --- a/configs/mt7981_sd_rfb_defconfig
 +++ b/configs/mt7981_sd_rfb_defconfig
-@@ -8,38 +8,57 @@ CONFIG_NR_DRAM_BANKS=1
+@@ -8,37 +8,56 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x80000
 CONFIG_ENV_OFFSET=0x300000
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-sd-rfb"
@@ -200,7 +198,6 @@
 CONFIG_SYS_PBSIZE=1049
 CONFIG_LOGLEVEL=7
 CONFIG_LOG=y
- # CONFIG_BOARD_INIT is not set
 +CONFIG_BOARD_LATE_INIT=y
 CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_CMD_CPU=y
@@ -244,7 +241,7 @@
 CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
-@@ -47,7 +66,13 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+@@ -46,7 +65,13 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
@@ -258,7 +255,7 @@
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_MMC_MTK=y
 CONFIG_PHY_FIXED=y
-@@ -60,6 +85,7 @@ CONFIG_MTK_POWER_DOMAIN=y
+@@ -59,6 +84,7 @@ CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
@@ -268,10 +265,10 @@
 CONFIG_HEXDUMP=y
 --- a/configs/mt7981_snfi_nand_rfb_defconfig
 +++ b/configs/mt7981_snfi_nand_rfb_defconfig
-@@ -7,37 +7,73 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
+@@ -6,37 +6,73 @@ CONFIG_TEXT_BASE=0x41e00000
+ CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb"
- # CONFIG_BOARD_INIT is not set
 -CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_TARGET_MT7981=y
@@ -330,11 +327,11 @@
 CONFIG_CMD_UBI_RENAME=y
 CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_UBI=y
-+CONFIG_ENV_REDUNDANT=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 +CONFIG_ENV_UBI_PART="ubi"
 +CONFIG_ENV_UBI_VOLUME="ubootenv"
 +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
-+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
@@ -349,7 +346,7 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-@@ -51,6 +87,6 @@ CONFIG_PINCTRL_MT7981=y
+@@ -50,6 +86,6 @@ CONFIG_PINCTRL_MT7981=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
@@ -359,14 +356,13 @@
 -CONFIG_LMB_MAX_REGIONS=64
 --- a/configs/mt7981_nor_rfb_defconfig
 +++ b/configs/mt7981_nor_rfb_defconfig
-@@ -5,38 +5,74 @@ CONFIG_ARCH_MEDIATEK=y
+@@ -5,37 +5,73 @@ CONFIG_ARCH_MEDIATEK=y
 CONFIG_TEXT_BASE=0x41e00000
 CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_NR_DRAM_BANKS=1
 +CONFIG_ENV_SIZE=0x4000
 +CONFIG_ENV_OFFSET=0x0
 CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
- # CONFIG_BOARD_INIT is not set
 -CONFIG_SYS_PROMPT="MT7981> "
 +CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_TARGET_MT7981=y
@@ -424,8 +420,8 @@
 +CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_OVERWRITE=y
 +CONFIG_ENV_IS_IN_MTD=y
-+CONFIG_ENV_REDUNDANT=y
-+CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 +CONFIG_ENV_MTD_DEV="u-boot-env"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
@@ -441,7 +437,7 @@
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
-@@ -61,9 +97,9 @@ CONFIG_PINCTRL_MT7981=y
+@@ -60,9 +96,9 @@ CONFIG_PINCTRL_MT7981=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
--- a/package/boot/uboot-mediatek/patches/110-mtd-spi-nand-add-support-for-FudanMicro-FM25S01A.patch
+++ b/package/boot/uboot-mediatek/patches/110-mtd-spi-nand-add-support-for-FudanMicro-FM25S01A.patch
@@ -1,76 +0,0 @@
-From c5b3dd3b860b7eb65950c077a70b2e5ad68626b0 Mon Sep 17 00:00:00 2001
-From: Mikhail Zhilkin <csharper2005@gmail.com>
-Date: Wed, 13 Aug 2025 21:54:49 +0300
-Subject: uboot-mediatek: add support for FudanMicro FM25S01A
-
-This patch adds support for FudanMicro FM25S01A SPI NAND. It's required
-for some CMCC RAX3000Me hardware revisions.
-
-The patch was partially taken from ImmortalWrt.
-Link:
-https://raw.githubusercontent.com/immortalwrt/immortalwrt/refs/heads/master/package/boot/uboot-mediatek/patches/342-mtd-spinand-Support-fmsh.patch
-
-Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
---
-
--- a/drivers/mtd/nand/spi/fudanmicro.c
-+++ b/drivers/mtd/nand/spi/fudanmicro.c
-@@ -27,6 +27,29 @@ static SPINAND_OP_VARIANTS(update_cache_
- 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
- 
-+static int fm25s01a_ooblayout_ecc(struct mtd_info *mtd, int section,
-+				  struct mtd_oob_region *region)
-+{
-+	return -ERANGE;
-+}
-+
-+static int fm25s01a_ooblayout_free(struct mtd_info *mtd, int section,
-+				   struct mtd_oob_region *region)
-+{
-+	if (section)
-+		return -ERANGE;
-+
-+	region->offset = 2;
-+	region->length = 62;
-+
-+	return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops fm25s01a_ooblayout = {
-+	.ecc = fm25s01a_ooblayout_ecc,
-+	.rfree = fm25s01a_ooblayout_free,
-+};
-+
- static int fm25s01b_ooblayout_ecc(struct mtd_info *mtd, int section,
- 				      struct mtd_oob_region *region)
- {
-@@ -83,8 +106,17 @@ static int fm25s01b_ecc_get_status(struc
- }
- 
- static const struct spinand_info fudan_spinand_table[] = {
-	SPINAND_INFO("FM25s01B",
-			 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
-+	SPINAND_INFO("FM25S01A",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
-+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
-+		     NAND_ECCREQ(1, 512),
-+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-+					      &write_cache_variants,
-+					      &update_cache_variants),
-+		     0,
-+		     SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
-+	SPINAND_INFO("FM25S01B",
-+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
- 		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- 		     NAND_ECCREQ(8, 512),
- 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
-@@ -100,7 +132,7 @@ static const struct spinand_manufacturer
- 
- const struct spinand_manufacturer fudan_spinand_manufacturer = {
- 	.id = SPINAND_MFR_FUDAN,
-	.name = "FUDAN Micron",
-+	.name = "FudanMicro",
- 	.chips = fudan_spinand_table,
- 	.nchips = ARRAY_SIZE(fudan_spinand_table),
- 	.ops = &fudan_spinand_manuf_ops,
--- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
+++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch
@@ -1,6 +1,6 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -1298,7 +1298,7 @@ quiet_cmd_pad_cat = CAT     $@
+@@ -1094,7 +1094,7 @@ quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }
 
 quiet_cmd_lzma = LZMA    $@
--- a/package/boot/uboot-mediatek/patches/129-board-mediatek-wire-up-NMBM-support.patch
+++ b/package/boot/uboot-mediatek/patches/129-board-mediatek-wire-up-NMBM-support.patch
@@ -12,7 +12,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support

 --- a/board/mediatek/mt7622/mt7622_rfb.c
 +++ b/board/mediatek/mt7622/mt7622_rfb.c
-@@ -9,4 +9,42 @@
+@@ -9,9 +9,47 @@
 #include <init.h>
 #include <asm/global_data.h>
 
@@ -22,6 +22,11 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
 +#include <nmbm/nmbm-mtd.h>
 +
 DECLARE_GLOBAL_DATA_PTR;
+ 
+ int board_init(void)
+ {
+ 	return 0;
+ }
 +
 +int board_nmbm_init(void)
 +{
@@ -108,15 +113,34 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
 +}
 --- a/board/mediatek/mt7981/mt7981_rfb.c
 +++ b/board/mediatek/mt7981/mt7981_rfb.c
-@@ -4,3 +4,38 @@
+@@ -4,7 +4,57 @@
  * Author: Sam Shih <sam.shih@mediatek.com>
  */
 
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
 +#include <mtd.h>
 +#include <linux/mtd/mtd.h>
 +#include <nmbm/nmbm.h>
 +#include <nmbm/nmbm-mtd.h>
 +
+DECLARE_GLOBAL_DATA_PTR;
+
+ int board_init(void)
+ {
+ 	return 0;
+ }
+
+int board_late_init(void)
+{
+	gd->env_valid = 1; //to load environment variable from persistent store
+	env_relocate();
+	return 0;
+}
+
 +int board_nmbm_init(void)
 +{
 +#ifdef CONFIG_ENABLE_NAND_NMBM
@@ -149,15 +173,34 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support
 +}
 --- a/board/mediatek/mt7986/mt7986_rfb.c
 +++ b/board/mediatek/mt7986/mt7986_rfb.c
-@@ -4,3 +4,40 @@
+@@ -4,7 +4,59 @@
  * Author: Sam Shih <sam.shih@mediatek.com>
  */
 
+#include <config.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+
 +#include <mtd.h>
 +#include <linux/mtd/mtd.h>
 +#include <nmbm/nmbm.h>
 +#include <nmbm/nmbm-mtd.h>
 +
+DECLARE_GLOBAL_DATA_PTR;
+
+ int board_init(void)
+ {
+ 	return 0;
+ }
+
+int board_late_init(void)
+{
+	gd->env_valid = 1; //to load environment variable from persistent store
+	env_relocate();
+	return 0;
+}
+
 +int board_nmbm_init(void)
 +{
 +#ifdef CONFIG_ENABLE_NAND_NMBM
--- a/package/boot/uboot-mediatek/patches/130-01-env-mtd-add-the-missing-put_mtd_device.patch
+++ b/package/boot/uboot-mediatek/patches/130-01-env-mtd-add-the-missing-put_mtd_device.patch
@@ -0,0 +1,47 @@
+From 0508c8e120d275d994e6099eb9c60bfaec0c3f5f Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Mon, 21 Jul 2025 21:32:16 +0800
+Subject: [PATCH 1/2] env: mtd: add the missing put_mtd_device()
+
+The mtd device is got in setup_mtd_device(), we must put the mtd
+device before exiting the function to update the mtd use count. This
+patch fixes the following env error:
+
+> Removing MTD device #2 (u-boot-env) with use count 1
+> Error when deleting partition "u-boot-env" (-16)
+
+Fixes: 03fb08d4aef8 ("env: Introduce support for MTD")
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ env/mtd.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/env/mtd.c
+++ b/env/mtd.c
+@@ -131,6 +131,8 @@ static int env_mtd_save(void)
+ 	puts("done\n");
+ 
+ done:
+	put_mtd_device(mtd_env);
+
+ 	if (saved_buf)
+ 		free(saved_buf);
+ 
+@@ -188,6 +190,8 @@ static int env_mtd_load(void)
+ 		gd->env_valid = ENV_VALID;
+ 
+ out:
+	put_mtd_device(mtd_env);
+
+ 	free(buf);
+ 
+ 	return ret;
+@@ -280,6 +284,8 @@ static int env_mtd_erase(void)
+ 	ret = 0;
+ 
+ done:
+	put_mtd_device(mtd_env);
+
+ 	if (saved_buf)
+ 		free(saved_buf);
+ 
--- a/package/boot/uboot-mediatek/patches/130-02-env-mtd-initialize-saved_buf-pointer.patch
+++ b/package/boot/uboot-mediatek/patches/130-02-env-mtd-initialize-saved_buf-pointer.patch
@@ -0,0 +1,25 @@
+From 0ef932f509fd9f9215af2ea4ca2919d3285ddf60 Mon Sep 17 00:00:00 2001
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Thu, 24 Jul 2025 07:50:40 +0800
+Subject: [PATCH 2/2] env: mtd: initialize saved_buf pointer
+
+When sect_size is greater than CONFIG_ENV_SIZE, this wild
+pointer will cause CPU halt or system crash.
+
+Fixes: 03fb08d4aef8 ("env: Introduce support for MTD")
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ env/mtd.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/env/mtd.c
+++ b/env/mtd.c
+@@ -201,7 +201,7 @@ static int env_mtd_erase(void)
+ {
+ 	struct mtd_info *mtd_env;
+ 	u32 sect_size, sect_num;
+-	char *saved_buf, *tmp;
+	char *saved_buf = NULL, *tmp;
+ 	struct erase_info ei;
+ 	size_t ret_len;
+ 	int remaining;
--- a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
+++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch
--- a/package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch
+++ b/package/boot/uboot-mediatek/patches/170-cmd-bootmenu-permit-to-select-bootmenu-entry-with.patch
@@ -0,0 +1,261 @@
+From 16fd9af92b7ed93ece62fa8d1bef341455d773cf Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 24 May 2025 23:23:53 +0200
+Subject: [PATCH v2] cmd: bootmenu: permit to select bootmenu entry with a
+ shortcut
+
+Permit to select a bootmenu entry with a key shortcut. This is
+especially useful in production or testing scenario to automate flashing
+procedure or testing procedure.
+
+The boot entry are changed to append the shortcut key to it.
+
+Example:
+      1. Run default boot command.
+      2. Boot system via TFTP.
+      3. Boot production system from NAND.
+      4. Boot recovery system from NAND.
+      5. Load production system via TFTP then write to NAND.
+      6. Load recovery system via TFTP then write to NAND.
+      7. Load BL31+U-Boot FIP via TFTP then write to NAND.
+      8. Load BL2 preloader via TFTP then write to NAND.
+      9. Reboot.
+      a. Reset all settings to factory defaults.
+      0. Exit
+
+0 is always reserved for Exit to console.
+On pressing the keyboard key 2, the bootmenu entry 2 is selected and
+executed.
+
+Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9
+and a-z.
+If a shortcut key not present in the bootmenu list is pressed, it is
+simply ignored and eventually the autoboot is interrupted.
+
+Capital A-Z are converted to lower a-z and the related option is
+selected.
+
+Suggested-by: Weijie Gao <weijie.gao@mediatek.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+Changes v2:
+- Fix spelling mistake
+- Fix case with '0'
+
+ cmd/bootmenu.c | 41 ++++++++++++++++++++++++++++++++++++++---
+ common/menu.c  | 44 ++++++++++++++++++++++++++++++++++++++++++--
+ include/cli.h  |  2 ++
+ include/menu.h |  3 +++
+ 4 files changed, 85 insertions(+), 5 deletions(-)
+
+--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
+@@ -114,6 +114,14 @@ static char *bootmenu_choice_entry(void
+ 				++menu->active;
+ 			/* no menu key selected, regenerate menu */
+ 			return NULL;
+		case BKEY_SHORTCUT:
+			/* invalid shortcut, regenerate menu */
+			if (cch->shortcut_key >= menu->count - 1)
+				return NULL;
+			/* shortcut_key value for Exit is is -1 */
+			menu->active = cch->shortcut_key < 0 ? menu->count - 1 :
+							       cch->shortcut_key;
+			fallthrough;
+ 		case BKEY_SELECT:
+ 			iter = menu->first;
+ 			for (i = 0; i < menu->active; ++i)
+@@ -161,6 +169,21 @@ static void bootmenu_destroy(struct boot
+ 	free(menu);
+ }
+ 
+static char bootmenu_entry_shortcut_key(int index)
+{
+	switch (index) {
+	/* 1-9 shortcut key (0 reserved) */
+	case 0 ... 8:
+		return '1' + index;
+	/* a-z shortcut key  */
+	case 9 ... 34:
+		return 'a' + index - 9;
+	/* We support shortcut for up to 34 options (0 reserved) */
+	default:
+		return -ENOENT;
+	}
+}
+
+ /**
+  * prepare_bootmenu_entry() - generate the bootmenu_xx entries
+  *
+@@ -184,6 +207,8 @@ static int prepare_bootmenu_entry(struct
+ 	struct bootmenu_entry *iter = *current;
+ 
+ 	while ((option = bootmenu_getoption(i))) {
+		char shortcut_key;
+		int len;
+ 
+ 		/* bootmenu_[num] format is "[title]=[commands]" */
+ 		sep = strchr(option, '=');
+@@ -196,12 +221,22 @@ static int prepare_bootmenu_entry(struct
+ 		if (!entry)
+ 			return -ENOMEM;
+ 
+-		entry->title = strndup(option, sep - option);
+		/* Add shotcut key option: %c. %s\0 */
+		len = sep - option + 4;
+
+		entry->title = malloc(len);
+ 		if (!entry->title) {
+ 			free(entry);
+ 			return -ENOMEM;
+ 		}
+ 
+		shortcut_key = bootmenu_entry_shortcut_key(i);
+		/* Use emtpy space if entry doesn't support shortcut key */
+		snprintf(entry->title, len, "%c%c %s",
+			 shortcut_key > 0 ? shortcut_key : ' ',
+			 shortcut_key > 0 ? '.' : ' ',
+			 option);
+
+ 		entry->command = strdup(sep + 1);
+ 		if (!entry->command) {
+ 			free(entry->title);
+@@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_cr
+ 
+ 		/* Add Quit entry if exiting bootmenu is disabled */
+ 		if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE))
+-			entry->title = strdup("Exit");
+			entry->title = strdup("0. Exit");
+ 		else
+-			entry->title = strdup("Quit");
+			entry->title = strdup("0. Quit");
+ 
+ 		if (!entry->title) {
+ 			free(entry);
+--- a/common/menu.c
+++ b/common/menu.c
+@@ -8,6 +8,7 @@
+ #include <cli.h>
+ #include <malloc.h>
+ #include <errno.h>
+#include <linux/ctype.h>
+ #include <linux/delay.h>
+ #include <linux/list.h>
+ #include <watchdog.h>
+@@ -436,6 +437,29 @@ int menu_destroy(struct menu *m)
+ 	return 1;
+ }
+ 
+static int bootmenu_conv_shortcut_key(struct bootmenu_data *menu, int ichar)
+{
+	int shortcut_key;
+
+	ichar = tolower(ichar);
+	switch (ichar) {
+	/* a-z for bootmenu entry > 9 */
+	case 'a' ... 'z':
+		shortcut_key = ichar - 'a' + 9;
+		break;
+	/* 1-9 for bootmenu entry <= 9 */
+	case '1' ... '9':
+		shortcut_key = ichar - '1';
+		break;
+	/* Reserve 0 for last option (aka Exit) */
+	case '0':
+	default:
+		return -1;
+	}
+
+	return shortcut_key;
+}
+
+ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu,
+ 					 struct cli_ch_state *cch)
+ {
+@@ -443,12 +467,12 @@ enum bootmenu_key bootmenu_autoboot_loop
+ 	int i, c;
+ 
+ 	while (menu->delay > 0) {
+		int ichar;
+
+ 		if (ansi)
+ 			printf(ANSI_CURSOR_POSITION, menu->count + 5, 3);
+ 		printf("Hit any key to stop autoboot: %d ", menu->delay);
+ 		for (i = 0; i < 100; ++i) {
+-			int ichar;
+-
+ 			if (!tstc()) {
+ 				schedule();
+ 				mdelay(10);
+@@ -470,6 +494,11 @@ enum bootmenu_key bootmenu_autoboot_loop
+ 			case 0x3: /* ^C */
+ 				key = BKEY_QUIT;
+ 				break;
+			case 'A' ... 'Z':
+			case 'a' ... 'z':
+			case '0' ... '9':
+				key = BKEY_SHORTCUT;
+				break;
+ 			default:
+ 				key = BKEY_NONE;
+ 				break;
+@@ -477,6 +506,9 @@ enum bootmenu_key bootmenu_autoboot_loop
+ 			break;
+ 		}
+ 
+		if (key == BKEY_SHORTCUT)
+			cch->shortcut_key = bootmenu_conv_shortcut_key(menu, ichar);
+
+ 		if (menu->delay < 0)
+ 			break;
+ 
+@@ -524,6 +556,11 @@ enum bootmenu_key bootmenu_conv_key(int
+ 	case ' ':
+ 		key = BKEY_SPACE;
+ 		break;
+	case 'A' ... 'Z':
+	case 'a' ... 'z':
+	case '0' ... '9':
+		key = BKEY_SHORTCUT;
+		break;
+ 	default:
+ 		key = BKEY_NONE;
+ 		break;
+@@ -554,5 +591,8 @@ enum bootmenu_key bootmenu_loop(struct b
+ 
+ 	key = bootmenu_conv_key(c);
+ 
+	if (key == BKEY_SHORTCUT)
+		cch->shortcut_key = bootmenu_conv_shortcut_key(menu, c);
+
+ 	return key;
+ }
+--- a/include/cli.h
+++ b/include/cli.h
+@@ -17,12 +17,14 @@
+  * @esc_save: Escape characters collected so far
+  * @emit_upto: Next index to emit from esc_save
+  * @emitting: true if emitting from esc_save
+ * @shortcut_key: Selected shortcut option index
+  */
+ struct cli_ch_state {
+ 	int esc_len;
+ 	char esc_save[8];
+ 	int emit_upto;
+ 	bool emitting;
+	int shortcut_key;
+ };
+ 
+ /**
+--- a/include/menu.h
+++ b/include/menu.h
+@@ -54,6 +54,9 @@ enum bootmenu_key {
+ 	BKEY_QUIT,
+ 	BKEY_SAVE,
+ 
+	/* shortcut key to select menu option directly */
+	BKEY_SHORTCUT,
+
+ 	/* 'extra' keys, which are used by menus but not cedit */
+ 	BKEY_PLUS,
+ 	BKEY_MINUS,
--- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
+++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch
@@ -129,7 +129,7 @@
 		   int arch, int ph_type, int bootstage_id,
 --- a/include/image.h
 +++ b/include/image.h
-@@ -1114,6 +1114,7 @@ int fit_parse_subimage(const char *spec,
+@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec,
 		ulong *addr, const char **image_name);
 
 int fit_get_subimage_count(const void *fit, int images_noffset);
--- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
+++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch
@@ -1,6 +1,6 @@
 --- a/cmd/Kconfig
 +++ b/cmd/Kconfig
-@@ -715,6 +715,12 @@ config CMD_ENV_EXISTS
+@@ -709,6 +709,12 @@ config CMD_ENV_EXISTS
 	  Check if a variable is defined in the environment for use in
 	  shell scripting.
 
--- a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
+++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch
@@ -16,7 +16,7 @@ Reviewed-by: Tom Rini <trini@konsulko.com>

 --- a/boot/image-fdt.c
 +++ b/boot/image-fdt.c
-@@ -631,6 +631,12 @@ int image_setup_libfdt(struct bootm_head
+@@ -614,6 +614,12 @@ int image_setup_libfdt(struct bootm_head
 					images->fit_uname_cfg,
 					strlen(images->fit_uname_cfg) + 1, 1);
 
--- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
+++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch
@@ -17,9 +17,9 @@
 
 #include <mtd.h>
 #include <linux/mtd/mtd.h>
-@@ -16,6 +23,28 @@
- 
- DECLARE_GLOBAL_DATA_PTR;
+@@ -21,6 +28,28 @@ int board_init(void)
+ 	return 0;
+ }
 
 +int board_late_init(void)
 +{
@@ -39,9 +39,9 @@
 +		}
 +	}
 +
-+	env_relocate();
-+	return 0;
-+}
+ 	env_relocate();
+ 	return 0;
+ }
 +
 int board_nmbm_init(void)
 {
--- a/Show More
+++ b/Show More