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ar71xx: reorder some patches

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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34674
This commit is contained in:
Gabor Juhos 2012-12-14 07:16:56 +00:00
parent 34411a0cbd
commit 2e2c88b625
6 changed files with 26 additions and 26 deletions
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6
target/linux/ar71xx/patches-3.3/620-MIPS-ath79-OTP-support.patch → target/linux/ar71xx/patches-3.3/523-MIPS-ath79-OTP-support.patch
View File

@ -149,9 +149,9 @@
#endif /* _ATH79_DEV_WMAC_H */
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -129,6 +129,14 @@
#define QCA955X_NFC_BASE 0x1b000200
#define QCA955X_NFC_SIZE 0xb8
@@ -113,6 +113,14 @@
#define QCA955X_EHCI1_BASE 0x1b400000
#define QCA955X_EHCI_SIZE 0x200
+#define AR9300_OTP_BASE 0x14000
+#define AR9300_OTP_STATUS 0x15f18

0
target/linux/ar71xx/patches-3.3/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch → target/linux/ar71xx/patches-3.3/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
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20
target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch
View File

@ -53,9 +53,9 @@
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
/*
* DDR_CTRL block
@@ -167,6 +183,9 @@
#define AR9300_OTP_BASE 0x14000
#define AR9300_OTP_STATUS 0x15f18
@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
@ -65,7 +65,7 @@
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
@@ -179,6 +198,8 @@
@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@ -74,7 +74,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
@@ -191,6 +212,9 @@
@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@ -84,7 +84,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
@@ -212,6 +236,8 @@
@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@ -93,7 +93,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@@ -244,6 +270,8 @@
@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@ -102,7 +102,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
@@ -370,16 +398,50 @@
@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@ -153,7 +153,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
@@ -520,6 +582,12 @@
@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@ -166,7 +166,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
@@ -550,4 +618,133 @@
@@ -558,4 +626,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7

6
target/linux/ar71xx/patches-3.6/620-MIPS-ath79-OTP-support.patch → target/linux/ar71xx/patches-3.6/523-MIPS-ath79-OTP-support.patch
View File

@ -149,9 +149,9 @@
#endif /* _ATH79_DEV_WMAC_H */
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -129,6 +129,14 @@
#define QCA955X_NFC_BASE 0x1b000200
#define QCA955X_NFC_SIZE 0xb8
@@ -113,6 +113,14 @@
#define QCA955X_EHCI1_BASE 0x1b400000
#define QCA955X_EHCI_SIZE 0x200
+#define AR9300_OTP_BASE 0x14000
+#define AR9300_OTP_STATUS 0x15f18

0
target/linux/ar71xx/patches-3.6/621-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch → target/linux/ar71xx/patches-3.6/524-MIPS-ath79-add-ath79_wmac_disable_25ghz-helpers.patch
View File

20
target/linux/ar71xx/patches-3.6/601-MIPS-ath79-add-more-register-defines.patch
View File

@ -53,9 +53,9 @@
+#define QCA955X_NFC_BASE 0x1b000200
+#define QCA955X_NFC_SIZE 0xb8
/*
* DDR_CTRL block
@@ -167,6 +183,9 @@
#define AR9300_OTP_BASE 0x14000
#define AR9300_OTP_STATUS 0x15f18
@@ -175,6 +191,9 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
@ -65,7 +65,7 @@
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
@@ -179,6 +198,8 @@
@@ -187,6 +206,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
@ -74,7 +74,7 @@
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
@@ -191,6 +212,9 @@
@@ -199,6 +220,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
@ -84,7 +84,7 @@
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
@@ -212,6 +236,8 @@
@@ -220,6 +244,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
@ -93,7 +93,7 @@
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@@ -244,6 +270,8 @@
@@ -252,6 +278,8 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
@ -102,7 +102,7 @@
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
@@ -370,16 +398,50 @@
@@ -378,16 +406,50 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
@ -153,7 +153,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
@@ -520,6 +582,12 @@
@@ -528,6 +590,12 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@ -166,7 +166,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
@@ -551,4 +619,133 @@
@@ -559,4 +627,133 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7