e4eec3bfd8
Refreshed all patches. Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
103 lines
3.4 KiB
Diff
103 lines
3.4 KiB
Diff
From d96cf7e724105dc73f623c2019ab5bc78cef036e Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Wed, 20 Dec 2017 17:47:06 +0800
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Subject: [PATCH 175/224] net: mediatek: remove superfluous pin setup for
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MT7622 SoC
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Remove superfluous pin setup to get out of accessing invalid I/O pin
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registers because the way for pin configuring tends to be different from
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various SoCs and thus it should be better being managed and controlled by
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the pinctrl driver which MT7622 already can support.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++
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2 files changed, 24 insertions(+), 14 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1977,14 +1977,16 @@ static int mtk_hw_init(struct mtk_eth *e
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}
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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- /* Set GE2 driving and slew rate */
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- regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
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+ if (eth->pctl) {
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+ /* Set GE2 driving and slew rate */
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+ regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
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- /* set GE2 TDSEL */
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- regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
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+ /* set GE2 TDSEL */
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+ regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
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- /* set GE2 TUNE */
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- regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
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+ /* set GE2 TUNE */
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+ regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
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+ }
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/* Set linkdown as the default for each GMAC. Its own MCR would be set
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* up with the more appropriate value when mtk_phy_link_adjust call is
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@@ -2569,11 +2571,13 @@ static int mtk_probe(struct platform_dev
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}
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}
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- eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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- "mediatek,pctl");
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- if (IS_ERR(eth->pctl)) {
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- dev_err(&pdev->dev, "no pctl regmap found\n");
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- return PTR_ERR(eth->pctl);
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+ if (eth->soc->required_pctl) {
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+ eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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+ "mediatek,pctl");
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+ if (IS_ERR(eth->pctl)) {
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+ dev_err(&pdev->dev, "no pctl regmap found\n");
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+ return PTR_ERR(eth->pctl);
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+ }
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}
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for (i = 0; i < 3; i++) {
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@@ -2699,17 +2703,20 @@ static int mtk_remove(struct platform_de
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static const struct mtk_soc_data mt2701_data = {
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.caps = MTK_GMAC1_TRGMII,
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- .required_clks = MT7623_CLKS_BITMAP
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+ .required_clks = MT7623_CLKS_BITMAP,
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+ .required_pctl = true,
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};
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static const struct mtk_soc_data mt7622_data = {
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.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
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- .required_clks = MT7622_CLKS_BITMAP
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+ .required_clks = MT7622_CLKS_BITMAP,
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+ .required_pctl = false,
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};
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static const struct mtk_soc_data mt7623_data = {
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.caps = MTK_GMAC1_TRGMII,
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- .required_clks = MT7623_CLKS_BITMAP
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+ .required_clks = MT7623_CLKS_BITMAP,
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+ .required_pctl = true,
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};
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const struct of_device_id of_mtk_match[] = {
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -574,10 +574,13 @@ struct mtk_rx_ring {
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* @caps Flags shown the extra capability for the SoC
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* @required_clks Flags shown the bitmap for required clocks on
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* the target SoC
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+ * @required_pctl A bool value to show whether the SoC requires
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+ * the extra setup for those pins used by GMAC.
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*/
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struct mtk_soc_data {
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u32 caps;
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u32 required_clks;
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+ bool required_pctl;
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};
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/* currently no SoC has more than 2 macs */
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