0dbced8a48
This patch adds support for TP-LINK TL-WDR3320 v2. This router uses a chinese version 2 firmware header,. Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 46934
147 lines
3.8 KiB
C
147 lines
3.8 KiB
C
/*
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* TP-LINK TL-WDR3320 v2 board support
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*
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2015 Weijie Gao <hackpascal@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define WDR3320_GPIO_LED_WLAN5G 12
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#define WDR3320_GPIO_LED_SYSTEM 14
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#define WDR3320_GPIO_LED_QSS 15
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#define WDR3320_GPIO_LED_WAN 4
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#define WDR3320_GPIO_LED_LAN1 18
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#define WDR3320_GPIO_LED_LAN2 20
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#define WDR3320_GPIO_LED_LAN3 21
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#define WDR3320_GPIO_LED_LAN4 22
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#define WDR3320_GPIO_BTN_RESET 16
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#define WDR3320_KEYS_POLL_INTERVAL 20 /* msecs */
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#define WDR3320_KEYS_DEBOUNCE_INTERVAL (3 * WDR3320_KEYS_POLL_INTERVAL)
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#define WDR3320_WMAC_CALDATA_OFFSET 0x1000
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#define WDR3320_PCIE_CALDATA_OFFSET 0x5000
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static const char *wdr3320_part_probes[] = {
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"tp-link",
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NULL,
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};
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static struct flash_platform_data wdr3320_flash_data = {
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.part_probes = wdr3320_part_probes,
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};
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static struct gpio_led wdr3320_leds_gpio[] __initdata = {
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{
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.name = "tp-link:green:qss",
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.gpio = WDR3320_GPIO_LED_QSS,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:system",
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.gpio = WDR3320_GPIO_LED_SYSTEM,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:wlan5g",
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.gpio = WDR3320_GPIO_LED_WLAN5G,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button wdr3320_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = WDR3320_KEYS_DEBOUNCE_INTERVAL,
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.gpio = WDR3320_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static void __init wdr3320_setup(void)
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{
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u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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u8 tmpmac[ETH_ALEN];
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ath79_register_m25p80(&wdr3320_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3320_leds_gpio),
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wdr3320_leds_gpio);
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ath79_register_gpio_keys_polled(-1, WDR3320_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(wdr3320_gpio_keys),
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wdr3320_gpio_keys);
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ath79_init_mac(tmpmac, mac, 0);
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ath79_register_wmac(art + WDR3320_WMAC_CALDATA_OFFSET, tmpmac);
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ath79_init_mac(tmpmac, mac, -1);
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ap9x_pci_setup_wmac_led_pin(0, 0);
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ap91_pci_init(art + WDR3320_PCIE_CALDATA_OFFSET, tmpmac);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
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ath79_register_mdio(1, 0x0);
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/* LAN */
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ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
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/* GMAC1 is connected to the internal switch */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_register_eth(1);
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/* WAN */
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ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
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/* GMAC0 is connected to the PHY4 of the internal switch */
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ath79_switch_data.phy4_mii_en = 1;
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ath79_switch_data.phy_poll_mask = BIT(4);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(0);
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ath79_register_usb();
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ath79_gpio_output_select(WDR3320_GPIO_LED_LAN1,
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AR934X_GPIO_OUT_LED_LINK0);
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ath79_gpio_output_select(WDR3320_GPIO_LED_LAN2,
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AR934X_GPIO_OUT_LED_LINK1);
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ath79_gpio_output_select(WDR3320_GPIO_LED_LAN3,
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AR934X_GPIO_OUT_LED_LINK2);
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ath79_gpio_output_select(WDR3320_GPIO_LED_LAN4,
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AR934X_GPIO_OUT_LED_LINK3);
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ath79_gpio_output_select(WDR3320_GPIO_LED_WAN,
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AR934X_GPIO_OUT_LED_LINK4);
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}
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MIPS_MACHINE(ATH79_MACH_TL_WDR3320_V2, "TL-WDR3320-v2",
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"TP-LINK TL-WDR3320 v2",
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wdr3320_setup);
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