72 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			72 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| --- a/gcc/config/arm/arm.c
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| +++ b/gcc/config/arm/arm.c
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| @@ -3769,6 +3769,7 @@ arm_legitimate_address_p (enum machine_m
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|        rtx xop1 = XEXP (x, 1);
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|  
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|        return ((arm_address_register_rtx_p (xop0, strict_p)
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| +	       && GET_CODE(xop1) == CONST_INT
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|  	       && arm_legitimate_index_p (mode, xop1, outer, strict_p))
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|  	      || (arm_address_register_rtx_p (xop1, strict_p)
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|  		  && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
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| --- a/gcc/config/arm/arm.md
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| +++ b/gcc/config/arm/arm.md
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| @@ -4199,7 +4199,7 @@
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|  
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|  (define_expand "extendqihi2"
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|    [(set (match_dup 2)
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| -	(ashift:SI (match_operand:QI 1 "general_operand" "")
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| +	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
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|  		   (const_int 24)))
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|     (set (match_operand:HI 0 "s_register_operand" "")
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|  	(ashiftrt:SI (match_dup 2)
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| @@ -4224,7 +4224,7 @@
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|  
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|  (define_insn "*arm_extendqihi_insn"
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|    [(set (match_operand:HI 0 "s_register_operand" "=r")
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| -	(sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))]
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| +	(sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
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|    "TARGET_ARM && arm_arch4"
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|    "ldr%(sb%)\\t%0, %1"
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|    [(set_attr "type" "load_byte")
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| @@ -4235,7 +4235,7 @@
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|  
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|  (define_expand "extendqisi2"
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|    [(set (match_dup 2)
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| -	(ashift:SI (match_operand:QI 1 "general_operand" "")
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| +	(ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
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|  		   (const_int 24)))
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|     (set (match_operand:SI 0 "s_register_operand" "")
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|  	(ashiftrt:SI (match_dup 2)
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| @@ -4267,7 +4267,7 @@
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|  
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|  (define_insn "*arm_extendqisi"
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|    [(set (match_operand:SI 0 "s_register_operand" "=r")
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| -	(sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))]
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| +	(sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
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|    "TARGET_ARM && arm_arch4 && !arm_arch6"
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|    "ldr%(sb%)\\t%0, %1"
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|    [(set_attr "type" "load_byte")
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| @@ -4278,7 +4278,8 @@
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|  
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|  (define_insn "*arm_extendqisi_v6"
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|    [(set (match_operand:SI 0 "s_register_operand" "=r,r")
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| -	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))]
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| +	(sign_extend:SI
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| +	 (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
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|    "TARGET_ARM && arm_arch6"
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|    "@
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|     sxtb%?\\t%0, %1
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| --- a/gcc/config/arm/predicates.md
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| +++ b/gcc/config/arm/predicates.md
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| @@ -234,6 +234,10 @@
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|         (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
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|  					      0)")))
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|  
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| +(define_special_predicate "arm_reg_or_extendqisi_mem_op"
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| +  (ior (match_operand 0 "arm_extendqisi_mem_op")
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| +       (match_operand 0 "s_register_operand")))
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| +
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|  (define_predicate "power_of_two_operand"
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|    (match_code "const_int")
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|  {
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