02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
118 lines
3.0 KiB
Diff
118 lines
3.0 KiB
Diff
From 0a38d7a21ef0e851d025e4e16f096d5579226299 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Mon, 16 Jun 2014 17:44:08 -0700
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Subject: [PATCH 168/182] clk: qcom: Add MSM8960's HFPLLs
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Describe the HFPLLs present on MSM8960 devices.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/gcc-msm8960.c | 82 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 82 insertions(+)
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--- a/drivers/clk/qcom/gcc-msm8960.c
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+++ b/drivers/clk/qcom/gcc-msm8960.c
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@@ -30,6 +30,7 @@
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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+#include "clk-hfpll.h"
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#include "reset.h"
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static struct clk_pll pll3 = {
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@@ -75,6 +76,84 @@ static struct clk_regmap pll8_vote = {
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},
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};
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+static struct hfpll_data hfpll0_data = {
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+ .mode_reg = 0x3200,
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+ .l_reg = 0x3208,
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+ .m_reg = 0x320c,
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+ .n_reg = 0x3210,
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+ .config_reg = 0x3204,
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+ .status_reg = 0x321c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3214,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+ .d = &hfpll0_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll0",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+ .mode_reg = 0x3300,
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+ .l_reg = 0x3308,
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+ .m_reg = 0x330c,
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+ .n_reg = 0x3310,
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+ .config_reg = 0x3304,
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+ .status_reg = 0x331c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3314,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+ .d = &hfpll1_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll1",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+ .mode_reg = 0x3400,
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+ .l_reg = 0x3408,
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+ .m_reg = 0x340c,
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+ .n_reg = 0x3410,
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+ .config_reg = 0x3404,
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+ .status_reg = 0x341c,
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+ .config_val = 0x7845c665,
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+ .droop_reg = 0x3414,
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+ .droop_val = 0x0108c000,
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+ .min_rate = 600000000UL,
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+ .max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+ .d = &hfpll_l2_data,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .parent_names = (const char *[]){ "pxo" },
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+ .num_parents = 1,
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+ .name = "hfpll_l2",
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+ .ops = &clk_ops_hfpll,
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+ .flags = CLK_IGNORE_UNUSED,
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+ },
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+ .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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+};
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+
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static struct clk_pll pll14 = {
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.l_reg = 0x31c4,
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.m_reg = 0x31c8,
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@@ -2763,6 +2842,9 @@ static struct clk_regmap *gcc_msm8960_cl
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[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+ [PLL9] = &hfpll0.clkr,
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+ [PLL10] = &hfpll1.clkr,
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+ [PLL12] = &hfpll_l2.clkr,
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};
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static const struct qcom_reset_map gcc_msm8960_resets[] = {
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