02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
66 lines
1.6 KiB
Diff
66 lines
1.6 KiB
Diff
From 6992cf3e8900d042a845eafc11e7841f32fec0a6 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Thu, 12 Jun 2014 10:56:54 -0500
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Subject: [PATCH 146/182] ARM: dts: qcom: Add SATA support for IPQ8064 and
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AP148 board
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 ++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++
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2 files changed, 38 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -118,5 +118,13 @@
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0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
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0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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};
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+
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+ sata-phy@1b400000 {
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+ status = "ok";
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+ };
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+
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+ sata@29000000 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -339,5 +339,35 @@
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clock-names = "core", "iface", "phy";
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status = "disabled";
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};
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+
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+ sata_phy: sata-phy@1b400000 {
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+ compatible = "qcom,ipq806x-sata-phy";
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+ reg = <0x1b400000 0x200>;
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+
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+ clocks = <&gcc SATA_PHY_CFG_CLK>;
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+ clock-names = "cfg";
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+
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+ #phy-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ sata@29000000 {
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+ compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci";
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+ reg = <0x29000000 0x180>;
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+
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+ interrupts = <0 209 0x0>;
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+
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+ clocks = <&gcc SFAB_SATA_S_H_CLK>,
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+ <&gcc SATA_H_CLK>,
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+ <&gcc SATA_A_CLK>,
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+ <&gcc SATA_RXOOB_CLK>,
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+ <&gcc SATA_PMALIVE_CLK>;
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+ clock-names = "slave_face", "iface", "core",
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+ "rxoob", "pmalive";
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+
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+ phys = <&sata_phy>;
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+ phy-names = "sata-phy";
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+ status = "disabled";
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+ };
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};
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};
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