58d2bd88ae
Changes:
- Update patches
- Update dts with new binding
Tx term offset dropped and replaced with a new compatible
Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
Rejected upstream, can't find any reason to have this. No regression with
testing it on R7800.
Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
From 5149901e9e6deca487c01cc434a3ac4125c7b00b Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 15 Jun 2020 23:06:03 +0200
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Subject: PCI: qcom: Define some PARF params needed for ipq8064 SoC
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Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
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needed on some ipq8064 based device (Netgear R7800 for example). Without
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this the system locks on kernel load.
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Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com
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Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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Cc: stable@vger.kernel.org # v4.5+
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -76,6 +76,18 @@
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#define DBI_RO_WR_EN 1
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#define PERST_DELAY_US 1000
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+/* PARF registers */
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+#define PCIE20_PARF_PCS_DEEMPH 0x34
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+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
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+
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+#define PCIE20_PARF_PCS_SWING 0x38
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+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
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+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
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+
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+#define PCIE20_PARF_CONFIG_BITS 0x50
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+#define PHY_RX0_EQ(x) ((x) << 24)
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#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define SLV_ADDR_SPACE_SZ 0x10000000
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@@ -282,6 +294,7 @@ static int qcom_pcie_init_2_1_0(struct q
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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+ struct device_node *node = dev->of_node;
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u32 val;
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int ret;
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@@ -336,6 +349,17 @@ static int qcom_pcie_init_2_1_0(struct q
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val &= ~BIT(0);
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writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
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+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
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+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
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+ writel(PCS_SWING_TX_SWING_FULL(120) |
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+ PCS_SWING_TX_SWING_LOW(120),
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+ pcie->parf + PCIE20_PARF_PCS_SWING);
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+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
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+ }
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+
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/* enable external reference clock */
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val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
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val |= BIT(16);
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