16b01fb1b9
Hardware
--------
SoC: NXP P1020 (2x e500 @ 800MHz)
RAM: 256M DDR3 (Micron)
FLASH: 32M NOR (Spansion S29GL128S)
BTN: 1x Reset
WiFi: 1x Atheros AR9590 2.4 bgn 3x3
2x Atheros AR9590 5.0 an 3x3
ETH: 1x Gigabit Ethernet (Atheros AR8033)
LED: System (green/red) - Radio{0,1} (green)
LAN (connected to PHY)
- GE blue
- FE green
Serial is a Cisco-compatible RJ45 next to the ethernet port.
115200-N-8 are the settings for OS and U-Boot.
Installation
------------
1. Grab the OpenWrt initramfs, rename it to 01C8A8C0.img. Place it in
the root directory of a TFTP server and serve it at
192.168.200.200/24.
2. Connect to the serial port and boot the AP. Stop autoboot in U-Boot
by pressing Enter when prompted. Credentials are identical to the one
in the APs interface. By default it is admin / new2day.
3. Set the bootcmd so the AP can boot OpenWrt by executing
$ setenv boot_openwrt "setenv bootargs;
cp.b 0xee000000 0x1000000 0x1000000; bootm 0x1000000"
$ setenv bootcmd "run boot_openwrt"
$ saveenv
If you plan on going back to the vendor firmware - the bootcmd for it
is stored in the boot_flash variable.
4. Load the initramfs image to RAM and boot by executing
$ tftpboot 0x1000000 192.168.200.200:01C8A8C0.img; bootm
5. Make a backup of the "firmware" partition if you ever wish to go back
to the vendor firmware.
6. Upload the OpenWrt sysupgrade image via SCP to the devices /tmp
folder.
7. Flash OpenWrt using sysupgrade.
$ sysupgrade -n /tmp/openwrt-sysupgrade.bin
Signed-off-by: David Bauer <mail@david-bauer.net>
173 lines
3.1 KiB
Plaintext
173 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later or MIT
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "Enterasys WS-AP3710i";
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compatible = "enterasys,ws-ap3710i";
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aliases {
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led-boot = &led_power_green;
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led-failsafe = &led_power_red;
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led-running = &led_power_green;
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led-upgrade = &led_power_red;
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label-mac-device = &enet0;
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};
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memory {
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device_type = "memory";
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};
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leds {
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compatible = "gpio-leds";
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wifi1 {
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gpios = <&gpio0 3 0>;
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label = "ws-ap3710i:green:radio1";
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linux,default-trigger = "phy0tpt";
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};
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wifi2 {
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gpios = <&gpio0 4 0>;
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label = "ws-ap3710i:green:radio2";
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linux,default-trigger = "phy1tpt";
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};
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led_power_green: power_green {
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gpios = <&gpio0 8 0>;
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label = "ws-ap3710i:green:power";
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};
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led_power_red: power_red {
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gpios = <&gpio0 9 0>;
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label = "ws-ap3710i:red:power";
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 1 1>; /* active low */
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linux,code = <0x198>; /* KEY_RESTART */
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};
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xee000000 0x2000000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x2000000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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compatible = "denx,fit";
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reg = <0x0 0x1d80000>;
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label = "firmware";
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};
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partition@1d80000 {
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reg = <0x1d80000 0x80000>;
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label = "u-boot";
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read-only;
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};
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partition@1e00000 {
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reg = <0x1e00000 0x100000>;
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label = "nvram";
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read-only;
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};
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partition@1f00000 {
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reg = <0x1f00000 0x20000>;
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label = "cfg2";
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read-only;
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};
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partition@1f20000 {
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reg = <0x1f20000 0x20000>;
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label = "cfg1";
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read-only;
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};
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};
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};
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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gpio0: gpio-controller@fc00 {
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};
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mdio@24000 {
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phy4: ethernet-phy@4 {
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reg = <0x4>;
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reset-gpios = <&gpio0 2 1>;
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};
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};
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enet0: ethernet@b0000 {
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phy-connection-type = "rgmii-id";
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phy-handle = <&phy4>;
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "disabled";
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};
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usb@22000 {
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status = "disabled";
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};
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usb@23000 {
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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reg = <0 0xffe09000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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pci1: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/include/ "fsl/p1020si-post.dtsi"
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