Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
		
			
				
	
	
		
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			71 lines
		
	
	
		
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| From 7b294e0cd2f7fbfb548a17b8d68d161da19e6592 Mon Sep 17 00:00:00 2001
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| From: Joakim Zhang <qiangqing.zhang@nxp.com>
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| Date: Fri, 12 Jul 2019 08:02:56 +0000
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| Subject: [PATCH] can: flexcan: add Transceiver Delay Compensation suopport
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| 
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| The CAN FD protocol allows the transmission and reception of data at a higher
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| bit rate than the nominal rate used in the arbitration phase when the message's
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| BRS bit is set.
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| 
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| The TDC mechanism is effective only during the data phase of FD frames
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| having BRS bit set. It has no effect either on non-FD frames, or on FD
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| frames transmitted at normal bit rate.
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| 
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| Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
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| Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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| ---
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|  drivers/net/can/flexcan.c | 19 ++++++++++++++++++-
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|  1 file changed, 18 insertions(+), 1 deletion(-)
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| 
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| --- a/drivers/net/can/flexcan.c
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| +++ b/drivers/net/can/flexcan.c
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| @@ -149,8 +149,11 @@
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|  
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|  /* FLEXCAN FD control register (FDCTRL) bits */
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|  #define FLEXCAN_FDCTRL_FDRATE		BIT(31)
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| +#define FLEXCAN_FDCTRL_TDCEN		BIT(15)
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| +#define FLEXCAN_FDCTRL_TDCFAIL		BIT(14)
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|  #define FLEXCAN_FDCTRL_MBDSR1(x)	(((x) & 0x3) << 19)
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|  #define FLEXCAN_FDCTRL_MBDSR0(x)	(((x) & 0x3) << 16)
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| +#define FLEXCAN_FDCTRL_TDCOFF(x)	(((x) & 0x1f) << 8)
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|  
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|  /* FLEXCAN FD Bit Timing register (FDCBT) bits */
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|  #define FLEXCAN_FDCBT_FPRESDIV(x)	(((x) & 0x3ff) << 20)
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| @@ -1101,7 +1104,7 @@ static void flexcan_set_bittiming(struct
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|  	struct can_bittiming *bt = &priv->can.bittiming;
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|  	struct can_bittiming *dbt = &priv->can.data_bittiming;
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|  	struct flexcan_regs __iomem *regs = priv->regs;
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| -	u32 reg, reg_cbt, reg_fdcbt;
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| +	u32 reg, reg_cbt, reg_fdcbt, reg_fdctrl;
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|  
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|  	reg = priv->read(®s->ctrl);
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|  	reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP | FLEXCAN_CTRL_LOM);
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| @@ -1173,6 +1176,19 @@ static void flexcan_set_bittiming(struct
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|  					FLEXCAN_FDCBT_FPROPSEG(dbt->prop_seg);
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|  			priv->write(reg_fdcbt, ®s->fdcbt);
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|  
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| +			/* enable transceiver delay compensation(TDC) for fd frame.
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| +			 * TDC must be disabled when Loop Back mode is enabled.
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| +			 */
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| +			reg_fdctrl = priv->read(®s->fdctrl);
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| +			if (!(reg & FLEXCAN_CTRL_LPB)) {
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| +				reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN;
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| +				reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCOFF(0x1f);
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| +				/* for the TDC to work reliably, the offset has to use optimal settings */
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| +				reg_fdctrl |= FLEXCAN_FDCTRL_TDCOFF(((dbt->phase_seg1 - 1) + dbt->prop_seg + 2) *
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| +								    ((dbt->brp -1) + 1));
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| +			}
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| +			priv->write(reg_fdctrl, ®s->fdctrl);
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| +
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|  			if (bt->brp != dbt->brp)
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|  				netdev_warn(dev, "Warning!! data brp = %d and brp = %d don't match.\n"
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|  					    "flexcan may not work. consider using different bitrate or data bitrate\n",
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| @@ -1322,6 +1338,7 @@ static int flexcan_chip_start(struct net
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|  	/* FDCTRL */
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|  	if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) {
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|  		reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
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| +		reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN;
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|  		reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
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|  		reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
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|  		reg_ctrl2 = priv->read(®s->ctrl2) & ~FLEXCAN_CTRL2_ISOCANFDEN;
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