36aa27189a
Deleted upstream patches:
generic:
041-genirq-affinity-Make-affinity-setting-if-activated-o.patch
ipq806x:
093-5-v5.8-ipq806x-PCI-qcom-Define-some-PARF-params-needed-for-ipq8064-SoC.patch
093-6-v5.8-ipq806x-PCI-qcom-Add-support-for-tx-term-offset-for-rev-2_1_0.patch
Merged manually:
ipq806x:
093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch
layerscape:
804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch
Build-tested: ath79/generic, ipq806x, layerscape/armv7, layerscape/armv8_64b
Run-tested: ipq806x (R7800)
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
104 lines
3.3 KiB
Diff
104 lines
3.3 KiB
Diff
From 8b6f0330b5f9a7543356bfa9e76d580f03aa2c1e Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 15 Jun 2020 23:05:57 +0200
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Subject: PCI: qcom: Add missing ipq806x clocks in PCIe driver
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Aux and Ref clk are missing in PCIe qcom driver. Add support for this
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optional clks for ipq8064/apq8064 SoC.
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Link: https://lore.kernel.org/r/20200615210608.21469-2-ansuelsmth@gmail.com
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Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 38 +++++++++++++++++++++++++++++-----
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1 file changed, 33 insertions(+), 5 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -103,6 +103,8 @@ struct qcom_pcie_resources_2_1_0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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+ struct clk *aux_clk;
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+ struct clk *ref_clk;
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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@@ -253,6 +255,14 @@ static int qcom_pcie_get_resources_2_1_0
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if (IS_ERR(res->phy_clk))
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return PTR_ERR(res->phy_clk);
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+ res->aux_clk = devm_clk_get_optional(dev, "aux");
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+ if (IS_ERR(res->aux_clk))
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+ return PTR_ERR(res->aux_clk);
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+
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+ res->ref_clk = devm_clk_get_optional(dev, "ref");
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+ if (IS_ERR(res->ref_clk))
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+ return PTR_ERR(res->ref_clk);
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+
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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if (IS_ERR(res->pci_reset))
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return PTR_ERR(res->pci_reset);
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@@ -285,6 +295,8 @@ static void qcom_pcie_deinit_2_1_0(struc
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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clk_disable_unprepare(res->phy_clk);
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+ clk_disable_unprepare(res->aux_clk);
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+ clk_disable_unprepare(res->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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@@ -315,16 +327,28 @@ static int qcom_pcie_init_2_1_0(struct q
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goto err_assert_ahb;
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}
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+ ret = clk_prepare_enable(res->core_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable core clock\n");
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+ goto err_clk_core;
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+ }
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+
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ret = clk_prepare_enable(res->phy_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable phy clock\n");
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goto err_clk_phy;
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}
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- ret = clk_prepare_enable(res->core_clk);
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+ ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable core clock\n");
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- goto err_clk_core;
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_clk_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->ref_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable ref clock\n");
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+ goto err_clk_ref;
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}
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ret = reset_control_deassert(res->ahb_reset);
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@@ -400,10 +424,14 @@ static int qcom_pcie_init_2_1_0(struct q
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return 0;
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err_deassert_ahb:
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- clk_disable_unprepare(res->core_clk);
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-err_clk_core:
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+ clk_disable_unprepare(res->ref_clk);
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+err_clk_ref:
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+ clk_disable_unprepare(res->aux_clk);
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+err_clk_aux:
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clk_disable_unprepare(res->phy_clk);
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err_clk_phy:
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+ clk_disable_unprepare(res->core_clk);
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+err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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err_assert_ahb:
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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