10c5d3dd5f
SoC: Mediatek MT7621A
CPU: 4x 880Mhz
Cache: 32 KB I-Cache and 32 KB D-Cach
256 KB L2 Cache (shared by Dual-Core)
RAM: DDR3 512MB 16bits BUS
FLASH: 16MB
Switch: Mediatek Gigabit Switch (2 x LAN, 1 x WAN)
POE: (1x PD, 2x PSE)
USB: 1x 3.0
PCI: 3x Mini PCIe (3 USB2.0 + 2 x UIM interface)
GPS: Quectel L70B
SIM: 2 Slots
BTN: Reset
LED: - Power
- Ethernet
- Wifi
- USB
UART: UART is present as Pads with throughholes on the PCB.
They are located on left side.
3.3V - RX - GND - TX / 57600-8N1
3.3V is the square pad
Installation
------------
The stock image is a modified openwrt and can be overflashed via sysupgrade -F
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
[merge conflict in mt7621.mk]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
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| .. | ||
| imagebuilder | ||
| linux | ||
| sdk | ||
| toolchain | ||
| Config.in | ||
| Makefile | ||