diff --git a/target/linux/octeon/patches-5.4/705-last-debugs.patch b/target/linux/octeon/patches-5.4/705-last-debugs.patch
index aea2bf6996..60e1d3255f 100644
--- a/target/linux/octeon/patches-5.4/705-last-debugs.patch
+++ b/target/linux/octeon/patches-5.4/705-last-debugs.patch
@@ -1,6 +1,8 @@
+diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+index 93a498d05184..27733d710355 100644
 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
 +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
-@@ -121,38 +121,53 @@ int __cvmx_helper_xaui_enable(int interface)
+@@ -121,58 +121,80 @@ int __cvmx_helper_xaui_enable(int interface)
  	union cvmx_gmxx_tx_int_en gmx_tx_int_en;
  	union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
  
@@ -54,8 +56,11 @@
  	xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
  	xauiCtl.s.lo_pwr = 0;
  
-@@ -161,18 +176,24 @@ int __cvmx_helper_xaui_enable(int interface)
- 	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
+ 	/* Issuing a reset here seems to hang some CN68XX chips. */
+ 	if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) &&
+-	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X))
++	    !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X) &&
++        0)
  		xauiCtl.s.reset = 1;
  
 +    cvmx_dprintf("4.4\n");
@@ -79,7 +84,7 @@
  	/* Wait for RX to be ready */
  	if (CVMX_WAIT_FOR_FIELD64
  	    (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
-@@ -180,8 +201,11 @@ int __cvmx_helper_xaui_enable(int interface)
+@@ -180,8 +202,11 @@ int __cvmx_helper_xaui_enable(int interface)
  		return -1;
  
  	/* (6) Configure GMX */
@@ -91,7 +96,7 @@
  	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
  
  	/* Wait for GMX RX to be idle */
-@@ -189,62 +213,87 @@ int __cvmx_helper_xaui_enable(int interface)
+@@ -189,62 +214,87 @@ int __cvmx_helper_xaui_enable(int interface)
  	    (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
  		    rx_idle, ==, 1, 10000))
  		return -1;