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7ace30aeb6
Backport upstream code split patch for qca8k needed for ipq40xx target to correctly implement a DSA driver. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
136 lines
4.6 KiB
Diff
136 lines
4.6 KiB
Diff
From d5f901eab2e9dfed1095995dfc98f231f4fd2971 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 27 Jul 2022 13:35:13 +0200
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Subject: [PATCH 04/14] net: dsa: qca8k: move qca8k read/write/rmw and reg
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table to common code
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The same reg table and read/write/rmw function are used by drivers
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based on qca8k family switch.
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Move them to common code to make it accessible also by other drivers.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 42 ------------------------------
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drivers/net/dsa/qca/qca8k-common.c | 38 +++++++++++++++++++++++++++
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drivers/net/dsa/qca/qca8k.h | 6 +++++
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3 files changed, 44 insertions(+), 42 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -133,24 +133,6 @@ qca8k_set_page(struct qca8k_priv *priv,
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return 0;
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}
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-static int
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-qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
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-{
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- return regmap_read(priv->regmap, reg, val);
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-}
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-
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-static int
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-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
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-{
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- return regmap_write(priv->regmap, reg, val);
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-}
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-
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-static int
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-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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-{
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- return regmap_update_bits(priv->regmap, reg, mask, write_val);
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-}
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-
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static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
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{
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struct qca8k_mgmt_eth_data *mgmt_eth_data;
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@@ -483,30 +465,6 @@ exit:
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return ret;
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}
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-static const struct regmap_range qca8k_readable_ranges[] = {
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- regmap_reg_range(0x0000, 0x00e4), /* Global control */
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- regmap_reg_range(0x0100, 0x0168), /* EEE control */
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- regmap_reg_range(0x0200, 0x0270), /* Parser control */
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- regmap_reg_range(0x0400, 0x0454), /* ACL */
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- regmap_reg_range(0x0600, 0x0718), /* Lookup */
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- regmap_reg_range(0x0800, 0x0b70), /* QM */
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- regmap_reg_range(0x0c00, 0x0c80), /* PKT */
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- regmap_reg_range(0x0e00, 0x0e98), /* L3 */
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- regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
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- regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
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- regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
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- regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
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- regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
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- regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
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- regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
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-
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-};
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-
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-static const struct regmap_access_table qca8k_readable_table = {
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- .yes_ranges = qca8k_readable_ranges,
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- .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
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-};
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-
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static struct regmap_config qca8k_regmap_config = {
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.reg_bits = 16,
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.val_bits = 32,
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--- a/drivers/net/dsa/qca/qca8k-common.c
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+++ b/drivers/net/dsa/qca/qca8k-common.c
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@@ -61,3 +61,41 @@ const struct qca8k_mib_desc ar8327_mib[]
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MIB_DESC(1, 0xa8, "RXUnicast"),
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MIB_DESC(1, 0xac, "TXUnicast"),
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};
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+
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+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
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+{
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+ return regmap_read(priv->regmap, reg, val);
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+}
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+
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+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
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+{
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+ return regmap_write(priv->regmap, reg, val);
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+}
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+
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+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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+{
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+ return regmap_update_bits(priv->regmap, reg, mask, write_val);
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+}
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+
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+static const struct regmap_range qca8k_readable_ranges[] = {
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+ regmap_reg_range(0x0000, 0x00e4), /* Global control */
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+ regmap_reg_range(0x0100, 0x0168), /* EEE control */
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+ regmap_reg_range(0x0200, 0x0270), /* Parser control */
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+ regmap_reg_range(0x0400, 0x0454), /* ACL */
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+ regmap_reg_range(0x0600, 0x0718), /* Lookup */
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+ regmap_reg_range(0x0800, 0x0b70), /* QM */
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+ regmap_reg_range(0x0c00, 0x0c80), /* PKT */
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+ regmap_reg_range(0x0e00, 0x0e98), /* L3 */
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+ regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
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+ regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
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+ regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
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+ regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
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+ regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
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+ regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
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+ regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
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+};
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+
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+const struct regmap_access_table qca8k_readable_table = {
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+ .yes_ranges = qca8k_readable_ranges,
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+ .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
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+};
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--- a/drivers/net/dsa/qca/qca8k.h
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+++ b/drivers/net/dsa/qca/qca8k.h
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@@ -416,5 +416,11 @@ struct qca8k_fdb {
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/* Common setup function */
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extern const struct qca8k_mib_desc ar8327_mib[];
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+extern const struct regmap_access_table qca8k_readable_table;
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+
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+/* Common read/write/rmw function */
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+int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val);
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+int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);
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+int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val);
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#endif /* __QCA8K_H */
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