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61d1eedc2d
Refresh kernel patches using make target/linux/refresh. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
109 lines
3.1 KiB
Diff
109 lines
3.1 KiB
Diff
From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 9 May 2023 01:57:17 +0200
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Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
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comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
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current problem, we are forced to use sdhci_set_clock.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
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1 file changed, 43 insertions(+), 43 deletions(-)
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--- a/drivers/mmc/host/sdhci-msm.c
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+++ b/drivers/mmc/host/sdhci-msm.c
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@@ -1755,49 +1755,49 @@ static unsigned int sdhci_msm_get_min_cl
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return SDHCI_MSM_MIN_CLOCK;
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}
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-/*
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- * __sdhci_msm_set_clock - sdhci_msm clock control.
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- *
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- * Description:
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- * MSM controller does not use internal divider and
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- * instead directly control the GCC clock as per
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- * HW recommendation.
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- **/
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-static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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-{
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- u16 clk;
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-
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- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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-
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- if (clock == 0)
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- return;
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-
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- /*
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- * MSM controller do not use clock divider.
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- * Thus read SDHCI_CLOCK_CONTROL and only enable
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- * clock with no divider value programmed.
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- */
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- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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- sdhci_enable_clk(host, clk);
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-}
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-
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-/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
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-static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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-{
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- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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-
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- if (!clock) {
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- host->mmc->actual_clock = msm_host->clk_rate = 0;
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- goto out;
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- }
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-
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- sdhci_msm_hc_select_mode(host);
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-
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- msm_set_clock_rate_for_bus_mode(host, clock);
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-out:
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- __sdhci_msm_set_clock(host, clock);
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-}
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+// /*
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+// * __sdhci_msm_set_clock - sdhci_msm clock control.
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+// *
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+// * Description:
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+// * MSM controller does not use internal divider and
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+// * instead directly control the GCC clock as per
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+// * HW recommendation.
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+// **/
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+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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+// {
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+// u16 clk;
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+
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+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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+
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+// if (clock == 0)
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+// return;
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+
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+// /*
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+// * MSM controller do not use clock divider.
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+// * Thus read SDHCI_CLOCK_CONTROL and only enable
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+// * clock with no divider value programmed.
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+// */
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+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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+// sdhci_enable_clk(host, clk);
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+// }
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+
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+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
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+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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+// {
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+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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+
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+// if (!clock) {
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+// host->mmc->actual_clock = msm_host->clk_rate = 0;
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+// goto out;
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+// }
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+
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+// sdhci_msm_hc_select_mode(host);
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+
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+// msm_set_clock_rate_for_bus_mode(host, clock);
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+// out:
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+// __sdhci_msm_set_clock(host, clock);
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+// }
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/*****************************************************************************\
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* *
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