mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-04 06:54:27 -05:00
3771176c9e
The following patches are dropped because they are merged upstream: -0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch -0006-usb-drop-deprecated-symbols.patch -0009-MIPS-ath79-add-lots-of-missing-registers.patch -0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch -0014-MIPS-ath79-finetune-cpu-overrides.patch -0015-MIPS-ath79-enable-uart-during-early_prink.patch -0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch This patch is dropped due to the introduction of spi-mem framework: -461-spi-ath79-add-fast-flash-read.patch Thank to Michael Marley @mamarley for his work on this patch: -910-unaligned_access_hacks.patch Signed-off-by: Chuanhong Guo <gch981213@gmail.com> [synchronized kernel config with make kernel_oldconfig] Signed-off-by: Petr Štetiar <ynezz@true.cz>
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
|
|
From: Felix Fietkau <nbd@nbd.name>
|
|
Date: Tue, 6 Mar 2018 13:27:28 +0100
|
|
Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
|
|
|
|
On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
|
|
clock. If that feature is not used, it defaults to the main reference
|
|
clock, like on all other SoC.
|
|
|
|
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|
Signed-off-by: John Crispin <john@phrozen.org>
|
|
---
|
|
arch/mips/ath79/clock.c | 8 ++++++++
|
|
include/dt-bindings/clock/ath79-clk.h | 3 ++-
|
|
2 files changed, 10 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/mips/ath79/clock.c
|
|
+++ b/arch/mips/ath79/clock.c
|
|
@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
|
|
[ATH79_CLK_DDR] = "ddr",
|
|
[ATH79_CLK_AHB] = "ahb",
|
|
[ATH79_CLK_REF] = "ref",
|
|
+ [ATH79_CLK_MDIO] = "mdio",
|
|
};
|
|
|
|
static const char * __init ath79_clk_name(int type)
|
|
@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
|
|
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
|
|
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
|
|
|
|
+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
|
|
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
|
|
+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
|
|
+
|
|
iounmap(dpll_base);
|
|
}
|
|
|
|
@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
|
|
else if (of_device_is_compatible(np, "qca,qca9560-pll"))
|
|
qca956x_clocks_init(pll_base);
|
|
|
|
+ if (!clks[ATH79_CLK_MDIO])
|
|
+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
|
|
+
|
|
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
|
|
pr_err("%pOF: could not register clk provider\n", np);
|
|
goto err_iounmap;
|
|
--- a/include/dt-bindings/clock/ath79-clk.h
|
|
+++ b/include/dt-bindings/clock/ath79-clk.h
|
|
@@ -14,7 +14,8 @@
|
|
#define ATH79_CLK_DDR 1
|
|
#define ATH79_CLK_AHB 2
|
|
#define ATH79_CLK_REF 3
|
|
+#define ATH79_CLK_MDIO 4
|
|
|
|
-#define ATH79_CLK_END 4
|
|
+#define ATH79_CLK_END 5
|
|
|
|
#endif /* __DT_BINDINGS_ATH79_CLK_H */
|