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Changelog: * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.5 Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 46598
153 lines
3.9 KiB
Diff
153 lines
3.9 KiB
Diff
From 0460e9868fd82a3675db02f6ceb6edfd8501c194 Mon Sep 17 00:00:00 2001
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From: Boris BREZILLON <boris.brezillon@free-electrons.com>
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Date: Mon, 28 Jul 2014 14:31:42 +0200
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Subject: [PATCH] mtd: nand: Add DT NAND partition parser
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Add a of_nandpart_parse function to help parsing NAND partitions from DT.
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This function should be called from NAND controller drivers just after the
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nand_scan_tail in place of mtd_device_parse_register.
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The caller can specify a parser function to retrieve HW specific
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informations from the DT.
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Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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drivers/mtd/nand/ofnandpart.c | 104 ++++++++++++++++++++++++++++++++++++++++++
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include/linux/mtd/nand.h | 17 +++++++
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2 files changed, 121 insertions(+)
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create mode 100644 drivers/mtd/nand/ofnandpart.c
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--- /dev/null
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+++ b/drivers/mtd/nand/ofnandpart.c
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@@ -0,0 +1,104 @@
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+/*
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+ * NAND Flash partitions described by the OF (or flattened) device tree
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+ *
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+ * Copyright © 2014 Boris BREZILLON <b.brezillon.dev@gmail.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/of.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/slab.h>
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+#include <linux/mtd/nand.h>
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+
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+static inline bool node_has_compatible(struct device_node *pp)
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+{
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+ return of_get_property(pp, "compatible", NULL);
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+}
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+
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+int ofnandpart_parse(struct mtd_info *master,
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+ const struct ofnandpart_data *data)
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+{
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+ struct device_node *node;
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+ const char *partname;
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+ struct device_node *pp;
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+ int i;
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+
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+ if (!data)
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+ return 0;
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+
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+ node = data->node;
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+ if (!node)
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+ return 0;
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+
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+ i = 0;
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+ for_each_child_of_node(node, pp) {
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+ const __be32 *reg;
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+ int len;
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+ int a_cells, s_cells;
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+ uint64_t offset, size;
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+ uint32_t mask_flags = 0;
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+ struct nand_part *part;
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+
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+ if (node_has_compatible(pp))
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+ continue;
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+
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+ reg = of_get_property(pp, "reg", &len);
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+ if (!reg)
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+ continue;
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+
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+ a_cells = of_n_addr_cells(pp);
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+ s_cells = of_n_size_cells(pp);
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+ offset = of_read_number(reg, a_cells);
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+ size = of_read_number(reg + a_cells, s_cells);
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+
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+ partname = of_get_property(pp, "label", &len);
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+ if (!partname)
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+ partname = of_get_property(pp, "name", &len);
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+
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+ if (of_get_property(pp, "read-only", &len))
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+ mask_flags |= MTD_WRITEABLE;
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+
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+ if (of_get_property(pp, "lock", &len))
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+ mask_flags |= MTD_POWERUP_LOCK;
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+
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+ if (data->parse)
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+ part = data->parse(data->priv, master, pp);
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+ else
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+ part = nandpart_alloc();
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+
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+ if (IS_ERR(part))
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+ continue;
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+
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+ part->offset = offset;
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+ part->master = master;
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+ part->mtd.name = partname;
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+ part->mtd.size = size;
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+ part->mtd.flags = mask_flags;
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+
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+ if (nand_add_partition(master, part)) {
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+ if (part->release)
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+ part->release(part);
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+ continue;
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+ }
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+
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+ i++;
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+ }
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+
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+ if (!i) {
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+ of_node_put(pp);
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+ pr_err("No valid partition found on %s\n", node->full_name);
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+ }
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+
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+ return i;
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+}
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+EXPORT_SYMBOL(ofnandpart_parse);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_DESCRIPTION("Parser for NAND flash partitioning information in device tree");
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+MODULE_AUTHOR("Boris BREZILLON");
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--- a/include/linux/mtd/nand.h
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+++ b/include/linux/mtd/nand.h
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@@ -1014,6 +1014,23 @@ static inline int jedec_feature(struct n
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: 0;
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}
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+/**
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+ * struct ofnandpart_data - struct used to retrieve NAND partitions from a DT
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+ * node
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+ * @parse: driver specific parser function
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+ * @priv: driver private data
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+ * @node: OF node containing NAND partitions
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+ */
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+struct ofnandpart_data {
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+ struct nand_part *(*parse)(void *priv, struct mtd_info *master,
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+ struct device_node *pp);
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+ void *priv;
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+ struct device_node *node;
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+};
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+
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+int ofnandpart_parse(struct mtd_info *master,
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+ const struct ofnandpart_data *data);
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+
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/*
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* struct nand_sdr_timings - SDR NAND chip timings
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*
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