mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-30 05:24:26 -04:00
2d379e796f
Changelog: * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.6 Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 46713
392 lines
14 KiB
Diff
392 lines
14 KiB
Diff
--- a/arch/mips/include/asm/r4kcache.h
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+++ b/arch/mips/include/asm/r4kcache.h
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@@ -25,6 +25,20 @@
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_icache)(void);
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+#ifdef CONFIG_BCM47XX
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+#include <asm/paccess.h>
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+#include <linux/ssb/ssb.h>
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+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE)))
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#define BCM4710_DUMMY_RREG()
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+
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+#define BCM4710_FILL_TLB(addr)
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+#define BCM4710_PROTECTED_FILL_TLB(addr)
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+#endif
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -98,6 +112,7 @@ static inline void flush_icache_line_ind
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -125,6 +140,7 @@ static inline void flush_icache_line(uns
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -132,6 +148,7 @@ static inline void flush_dcache_line(uns
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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@@ -187,6 +204,7 @@ static inline void protected_flush_icach
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Invalidate_I, addr);
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#else
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+ BCM4710_DUMMY_RREG();
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protected_cache_op(Hit_Invalidate_I, addr);
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#endif
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break;
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@@ -201,6 +219,7 @@ static inline void protected_flush_icach
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Writeback_Inv_D, addr);
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#else
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@@ -554,8 +573,51 @@ static inline void invalidate_tcache_pag
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: "r" (base), \
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"i" (op));
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+static inline void blast_dcache(void)
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+{
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+ unsigned long start = KSEG0;
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+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
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+ unsigned long end = (start + dcache_size);
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+
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+
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+ BCM4710_FILL_TLB(start);
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Hit_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page_indexed(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+ for (ws = 0; ws < ws_end; ws += ws_inc) {
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+ start = page + ws;
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+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, addr);
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+ }
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+ }
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+}
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+
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
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+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
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static inline void extra##blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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@@ -567,6 +629,7 @@ static inline void extra##blast_##pfx##c
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\
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__##pfx##flush_prologue \
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\
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+ war \
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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@@ -581,6 +644,7 @@ static inline void extra##blast_##pfx##c
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\
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__##pfx##flush_prologue \
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\
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+ war \
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do { \
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cache##lsize##_unroll32(start, hitop); \
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start += lsize * 32; \
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@@ -599,6 +663,8 @@ static inline void extra##blast_##pfx##c
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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+ war \
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+ \
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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@@ -608,26 +674,26 @@ static inline void extra##blast_##pfx##c
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__##pfx##flush_epilogue \
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}
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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-
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
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-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
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-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
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+
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
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+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
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+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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@@ -656,17 +722,19 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
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+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
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static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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+ war \
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\
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__##pfx##flush_prologue \
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\
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while (1) { \
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+ war2 \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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@@ -678,8 +746,8 @@ static inline void prot##extra##blast_##
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#ifndef CONFIG_EVA
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
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-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
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#else
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@@ -716,14 +784,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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#endif
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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- protected_, loongson2_)
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
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-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
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+ protected_, loongson2_, , )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
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/* blast_inv_dcache_range */
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-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
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-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
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+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
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#endif /* _ASM_R4KCACHE_H */
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--- a/arch/mips/include/asm/stackframe.h
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+++ b/arch/mips/include/asm/stackframe.h
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@@ -358,6 +358,10 @@
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set arch=r4000
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+#ifdef CONFIG_BCM47XX
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+ nop
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+ nop
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+#endif
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eret
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.set mips0
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.endm
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--- a/arch/mips/kernel/genex.S
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+++ b/arch/mips/kernel/genex.S
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@@ -32,6 +32,10 @@
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NESTED(except_vec3_generic, 0, sp)
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.set push
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.set noat
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+#ifdef CONFIG_BCM47XX
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+ nop
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+ nop
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+#endif
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -39,6 +39,9 @@
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#include <asm/dma-coherence.h>
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#include <asm/mips-cm.h>
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+/* For enabling BCM4710 cache workarounds */
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+int bcm4710 = 0;
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+
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/*
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* Special Variant of smp_call_function for use by cache functions:
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*
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@@ -157,6 +160,9 @@ static void r4k_blast_dcache_user_page_s
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_user_page = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -175,6 +181,9 @@ static void r4k_blast_dcache_page_indexe
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page_indexed = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -194,6 +203,9 @@ static void r4k_blast_dcache_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -793,6 +805,8 @@ static void local_r4k_flush_cache_sigtra
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unsigned long addr = (unsigned long) arg;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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if (dc_lsize)
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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@@ -1599,6 +1613,17 @@ static void coherency_setup(void)
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_type()) {
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+ case CPU_BMIPS3300:
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+ {
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+ u32 cm;
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+ break;
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -1645,6 +1670,15 @@ void r4k_cache_init(void)
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extern void build_copy_page(void);
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struct cpuinfo_mips *c = ¤t_cpu_data;
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM47XX
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+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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+#endif
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+ bcm4710 = 0;
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+
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probe_pcache();
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setup_scache();
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@@ -1714,7 +1748,15 @@ void r4k_cache_init(void)
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*/
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local_r4k___flush_cache_all(NULL);
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+#ifdef CONFIG_BCM47XX
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+ {
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+ static void (*_coherency_setup)(void);
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+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
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+ _coherency_setup();
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+ }
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+#else
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coherency_setup();
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+#endif
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board_cache_error_setup = r4k_cache_error_setup;
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/*
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -1296,6 +1296,9 @@ static void build_r4000_tlb_refill_handl
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/* No need for uasm_i_nop */
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}
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(&p);
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+#endif
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#ifdef CONFIG_64BIT
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build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
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#else
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@@ -1868,6 +1871,9 @@ build_r4000_tlbchange_handler_head(u32 *
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{
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struct work_registers wr = build_get_work_registers(p);
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+#ifdef CONFIG_BCM47XX
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+ uasm_i_nop(p);
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+#endif
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#ifdef CONFIG_64BIT
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build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
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#else
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