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598ba5b169
The BCM63167 is a BCM63268 SoC with a different physical packaging. Add the CPU ID to allow supporting routers with this SoC (i.e Sercomm H500-s) Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
146 lines
5.0 KiB
Diff
146 lines
5.0 KiB
Diff
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -184,7 +184,8 @@ enum bcm63xx_regs_set {
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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RSET_RNG,
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- RSET_MISC
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+ RSET_MISC,
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+ RSET_NAND
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@@ -262,6 +263,7 @@ enum bcm63xx_regs_set {
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#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_3368_RNG_BASE (0xdeadbeef)
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#define BCM_3368_MISC_BASE (0xdeadbeef)
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+#define BCM_3368_NAND_BASE (0xdeadbeef)
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/*
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* 6318 register sets base address
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@@ -309,6 +311,7 @@ enum bcm63xx_regs_set {
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#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6318_RNG_BASE (0xdeadbeef)
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#define BCM_6318_MISC_BASE (0xb0000280)
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+#define BCM_6318_NAND_BASE (0xdeadbeef)
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#define BCM_6318_OTP_BASE (0xdeadbeef)
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#define BCM_6318_STRAP_BASE (0xb0000900)
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@@ -359,6 +362,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_RNG_BASE (0xdeadbeef)
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#define BCM_6328_MISC_BASE (0xb0001800)
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+#define BCM_6328_NAND_BASE (0xb0000200)
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#define BCM_6328_OTP_BASE (0xb0000600)
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/*
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@@ -408,6 +412,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_RNG_BASE (0xdeadbeef)
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#define BCM_6338_MISC_BASE (0xdeadbeef)
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+#define BCM_6338_NAND_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@@ -456,6 +461,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_RNG_BASE (0xdeadbeef)
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#define BCM_6345_MISC_BASE (0xdeadbeef)
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+#define BCM_6345_NAND_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@@ -502,6 +508,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_RNG_BASE (0xdeadbeef)
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#define BCM_6348_MISC_BASE (0xdeadbeef)
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+#define BCM_6348_NAND_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@@ -548,7 +555,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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#define BCM_6358_RNG_BASE (0xdeadbeef)
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#define BCM_6358_MISC_BASE (0xdeadbeef)
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-
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+#define BCM_6358_NAND_BASE (0xdeadbeef)
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/*
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* 6362 register sets base address
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@@ -596,6 +603,7 @@ enum bcm63xx_regs_set {
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#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6362_RNG_BASE (0xdeadbeef)
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#define BCM_6362_MISC_BASE (0xb0001800)
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+#define BCM_6362_NAND_BASE (0xb0000200)
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#define BCM_6362_NAND_REG_BASE (0xb0000200)
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#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
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@@ -651,6 +659,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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#define BCM_6368_RNG_BASE (0xb0004180)
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#define BCM_6368_MISC_BASE (0xdeadbeef)
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+#define BCM_6368_NAND_BASE (0xb0000200)
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/*
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* 63268 register sets base address
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@@ -698,6 +707,7 @@ enum bcm63xx_regs_set {
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#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_63268_RNG_BASE (0xdeadbeef)
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#define BCM_63268_MISC_BASE (0xb0001800)
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+#define BCM_63268_NAND_BASE (0xb0000200)
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extern const unsigned long *bcm63xx_regs_base;
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@@ -743,6 +753,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
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[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
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+ [RSET_NAND] = BCM_## __cpu ##_NAND_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -111,5 +111,7 @@
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#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
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#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
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#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
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+#define bcm_nand_readl(o) bcm_rset_readl(RSET_NAND, (o))
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+#define bcm_nand_writel(v, o) bcm_rset_writel(RSET_NAND, (v), (o))
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#endif /* ! BCM63XX_IO_H_ */
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1688,4 +1688,31 @@
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#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
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#define OTP_6328_REG3_TP1_DISABLED BIT(9)
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+/*************************************************************************
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+ * _REG relative to RSET_NAND
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+ *************************************************************************/
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+
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+#define NAND_CS_SEL_REG 0x14
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+#define NAND_CS_SEL_EBC_CS0_SEL (1 << 0)
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+#define NAND_CS_SEL_EBC_CS1_SEL (1 << 1)
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+#define NAND_CS_SEL_EBC_CS2_SEL (1 << 2)
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+#define NAND_CS_SEL_EBC_CS3_SEL (1 << 3)
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+#define NAND_CS_SEL_EBC_CS4_SEL (1 << 4)
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+#define NAND_CS_SEL_EBC_CS5_SEL (1 << 5)
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+#define NAND_CS_SEL_EBC_CS6_SEL (1 << 6)
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+#define NAND_CS_SEL_EBC_CS7_SEL (1 << 7)
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+#define NAND_CS_SEL_EBI_CS0_USES_NAND (1 << 8)
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+#define NAND_CS_SEL_EBI_CS1_USES_NAND (1 << 9)
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+#define NAND_CS_SEL_EBI_CS2_USES_NAND (1 << 10)
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+#define NAND_CS_SEL_EBI_CS3_USES_NAND (1 << 11)
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+#define NAND_CS_SEL_EBI_CS4_USES_NAND (1 << 12)
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+#define NAND_CS_SEL_EBI_CS5_USES_NAND (1 << 13)
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+#define NAND_CS_SEL_EBI_CS6_USES_NAND (1 << 14)
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+#define NAND_CS_SEL_EBI_CS7_USES_NAND (1 << 15)
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+#define NAND_CS_SEL_WR_PROT_BLK0 (1 << 28)
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+#define NAND_CS_SEL_AUTO_DEV_ID (1 << 30)
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+#define NAND_CS_SEL_CS_LOCK (1 << 31)
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+
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+#define NAND_CS_XOR_REG 0x18
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+
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#endif /* BCM63XX_REGS_H_ */
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