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cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
99 lines
4.1 KiB
Diff
99 lines
4.1 KiB
Diff
From f48ec27500239c0400114327ecbbfec34bfc2deb Mon Sep 17 00:00:00 2001
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From: Li Yang <leoli@freescale.com>
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Date: Wed, 22 Feb 2012 15:52:50 +0000
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Subject: [PATCH] fsl_pmc: update device bindings
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Signed-off-by: Li Yang <leoyang.li@nxp.com>
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Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
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Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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---
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.../devicetree/bindings/powerpc/fsl/pmc.txt | 59 +++++++++++++---------
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1 file changed, 34 insertions(+), 25 deletions(-)
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--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
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+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
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@@ -9,15 +9,20 @@ Properties:
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"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8536-pmc" should also be listed for any chip
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- whose PMC is compatible, and implies deep-sleep capability.
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+ whose PMC is compatible, and implies deep-sleep capability and
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+ wake on user defined packet(wakeup on ARP).
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+
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+ "fsl,p1022-pmc" should be listed for any chip whose PMC is
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+ compatible, and implies lossless Ethernet capability during sleep.
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"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
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compatible; all statements below that apply to "fsl,mpc8548-pmc" also
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apply to "fsl,mpc8641d-pmc".
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Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
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- bit assignments are indicated via the sleep specifier in each device's
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- sleep property.
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+ bit assignments are indicated via the clock nodes. Device which has a
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+ controllable clock source should have a "fsl,pmc-handle" property pointing
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+ to the clock node.
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- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
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is the PMC block, and the second resource is the Clock Configuration
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@@ -33,31 +38,35 @@ Properties:
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this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
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a wakeup source from deep sleep.
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-Sleep specifiers:
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-
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- fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
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- that is set in the cell, the corresponding bit in SCCR will be saved
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- and cleared on suspend, and restored on resume. This sleep controller
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- supports disabling and resuming devices at any time.
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-
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- fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
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- which will be ORed into PMCDR upon suspend, and cleared from PMCDR
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- upon resume. The first two cells are as described for fsl,mpc8578-pmc.
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- This sleep controller only supports disabling devices during system
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- sleep, or permanently.
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-
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- fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
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- first of which will be ORed into DEVDISR (and the second into
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- DEVDISR2, if present -- this cell should be zero or absent if the
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- hardware does not have DEVDISR2) upon a request for permanent device
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- disabling. This sleep controller does not support configuring devices
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- to disable during system sleep (unless supported by another compatible
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- match), or dynamically.
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+Clock nodes:
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+The clock nodes are to describe the masks in PM controller registers for each
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+soc clock.
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+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
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+ ORed into PMCDR before suspend if the device using this clock is the wake-up
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+ source and need to be running during low power mode; clear the mask if
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+ otherwise.
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+
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+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
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+ bit specified by the mask in SCCR will be saved and cleared on suspend, and
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+ restored on resume.
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+
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+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
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+ DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR
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+ or DEVDISR2 when the clock should be permenently disabled.
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Example:
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- power@b00 {
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- compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
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- reg = <0xb00 0x100 0xa00 0x100>;
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- interrupts = <80 8>;
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+ power@e0070 {
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+ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
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+ reg = <0xe0070 0x20>;
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+
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+ etsec1_clk: soc-clk@24 {
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+ fsl,pmcdr-mask = <0x00000080>;
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+ };
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+ etsec2_clk: soc-clk@25 {
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+ fsl,pmcdr-mask = <0x00000040>;
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+ };
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+ etsec3_clk: soc-clk@26 {
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+ fsl,pmcdr-mask = <0x00000020>;
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+ };
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};
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