mirror of
				git://git.openwrt.org/openwrt/openwrt.git
				synced 2025-11-03 14:34:27 -05:00 
			
		
		
		
	Deleted (upstreamed): bcm27xx/patches-5.10/950-0669-drm-vc4-hdmi-Make-sure-the-device-is-powered-with-CE.patch [1] bcm27xx/patches-5.10/950-0672-drm-vc4-hdmi-Move-initial-register-read-after-pm_run.patch [1] gemini/patches-5.10/0003-ARM-dts-gemini-NAS4220-B-fis-index-block-with-128-Ki.patch [2] Manually rebased: bcm27xx/patches-5.10/950-0675-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-CEC-int.patch Manually reverted: generic/pending-5.10/860-Revert-ASoC-mediatek-Check-for-error-clk-pointer.patch [3] [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=55b10b88ac8654fc2f31518aa349a2e643b37f18 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.94&id=958a8819d41420d7a74ed922a09cacc0ba3a4218 [3] https://lore.kernel.org/all/trinity-2a727d96-0335-4d03-8f30-e22a0e10112d-1643363480085@3c-app-gmx-bap33/ Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
		
			
				
	
	
		
			58 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			58 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
From a29a7d01cd778854e08108461cba321a63d98871 Mon Sep 17 00:00:00 2001
 | 
						|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
 | 
						|
Date: Fri, 2 Jul 2021 16:39:47 +0200
 | 
						|
Subject: [PATCH] PCI: aardvark: Fix reading MSI interrupt number
 | 
						|
MIME-Version: 1.0
 | 
						|
Content-Type: text/plain; charset=UTF-8
 | 
						|
Content-Transfer-Encoding: 8bit
 | 
						|
 | 
						|
In advk_pcie_handle_msi() the authors expect that when bit i in the W1C
 | 
						|
register PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is
 | 
						|
updated to contain the MSI number corresponding to index i.
 | 
						|
 | 
						|
Experiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG
 | 
						|
always contains the number of the last received MSI, overall.
 | 
						|
 | 
						|
Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt
 | 
						|
number. Since Aardvark already forbids more than 32 interrupts and uses
 | 
						|
own allocated hwirq numbers, the msi_idx already corresponds to the
 | 
						|
received MSI number.
 | 
						|
 | 
						|
Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
 | 
						|
Signed-off-by: Pali Rohár <pali@kernel.org>
 | 
						|
Signed-off-by: Marek Behún <kabel@kernel.org>
 | 
						|
---
 | 
						|
 drivers/pci/controller/pci-aardvark.c | 13 ++++++-------
 | 
						|
 1 file changed, 6 insertions(+), 7 deletions(-)
 | 
						|
 | 
						|
--- a/drivers/pci/controller/pci-aardvark.c
 | 
						|
+++ b/drivers/pci/controller/pci-aardvark.c
 | 
						|
@@ -1393,7 +1393,7 @@ static void advk_pcie_remove_irq_domain(
 | 
						|
 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
 | 
						|
 {
 | 
						|
 	u32 msi_val, msi_mask, msi_status, msi_idx;
 | 
						|
-	u16 msi_data;
 | 
						|
+	int virq;
 | 
						|
 
 | 
						|
 	msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
 | 
						|
 	msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
 | 
						|
@@ -1403,13 +1403,12 @@ static void advk_pcie_handle_msi(struct
 | 
						|
 		if (!(BIT(msi_idx) & msi_status))
 | 
						|
 			continue;
 | 
						|
 
 | 
						|
-		/*
 | 
						|
-		 * msi_idx contains bits [4:0] of the msi_data and msi_data
 | 
						|
-		 * contains 16bit MSI interrupt number
 | 
						|
-		 */
 | 
						|
 		advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
 | 
						|
-		msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
 | 
						|
-		generic_handle_irq(msi_data);
 | 
						|
+		virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
 | 
						|
+		if (virq)
 | 
						|
+			generic_handle_irq(virq);
 | 
						|
+		else
 | 
						|
+			dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
 | 
						|
 	}
 | 
						|
 
 | 
						|
 	advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
 |