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752cd29904
Manually rebased: generic/hack-5.4/662-remove_pfifo_fast.patch All other patches automatically rebased. Build system: x86_64 Build-tested: ipq806x/R7800 Run-tested: ipq806x/R7800 No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us> [manual changes to ramips/patches-5.10/835-asoc-add-mt7620-support.patch] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
81 lines
2.3 KiB
Diff
81 lines
2.3 KiB
Diff
From: MarkLee <Mark-MC.Lee@mediatek.com>
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Date: Wed, 13 Nov 2019 10:38:42 +0800
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Subject: [PATCH] net: ethernet: mediatek: Integrate GDM/PSE setup operations
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Integrate GDM/PSE setup operations into single function "mtk_gdm_config"
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Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -2232,6 +2232,28 @@ static int mtk_start_dma(struct mtk_eth
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return 0;
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}
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+static void mtk_gdm_config(struct mtk_eth *eth, u32 config)
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+{
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+ int i;
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+
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+ for (i = 0; i < MTK_MAC_COUNT; i++) {
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+ u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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+
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+ /* default setup the forward port to send frame to PDMA */
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+ val &= ~0xffff;
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+
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+ /* Enable RX checksum */
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+ val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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+
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+ val |= config;
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+
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+ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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+ }
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+ /* Reset and enable PSE */
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+ mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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+ mtk_w32(eth, 0, MTK_RST_GL);
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+}
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+
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static int mtk_open(struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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@@ -2427,8 +2449,6 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
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mtk_tx_irq_disable(eth, ~0);
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mtk_rx_irq_disable(eth, ~0);
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- mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
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- mtk_w32(eth, 0, MTK_RST_GL);
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/* FE int grouping */
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mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
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@@ -2437,18 +2457,7 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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- for (i = 0; i < MTK_MAC_COUNT; i++) {
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- u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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-
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- /* setup the forward port to send frame to PDMA */
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- val &= ~0xffff;
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-
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- /* Enable RX checksum */
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- val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
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-
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- /* setup the mac dma */
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- mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
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- }
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+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
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return 0;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -84,6 +84,7 @@
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#define MTK_GDMA_ICS_EN BIT(22)
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#define MTK_GDMA_TCS_EN BIT(21)
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#define MTK_GDMA_UCS_EN BIT(20)
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+#define MTK_GDMA_TO_PDMA 0x0
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/* Unicast Filter MAC Address Register - Low */
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#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
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