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e3a1e78cd8
It compiles but *doesn't* boot so it isn't enabled yet. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
From ab4dda7a8cb7e55ea3d92fd5e249cf6f5396028c Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Thu, 11 Mar 2021 13:35:20 +0100
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Subject: [PATCH] dt-bindings: net: bcm4908-enet: add optional TX interrupt
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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I discovered that hardware actually supports two interrupts, one per DMA
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channel (RX and TX).
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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.../bindings/net/brcm,bcm4908-enet.yaml | 17 +++++++++++++----
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1 file changed, 13 insertions(+), 4 deletions(-)
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--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
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+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
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@@ -22,10 +22,18 @@ properties:
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maxItems: 1
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interrupts:
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- description: RX interrupt
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+ minItems: 1
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+ maxItems: 2
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+ items:
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+ - description: RX interrupt
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+ - description: TX interrupt
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interrupt-names:
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- const: rx
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+ minItems: 1
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+ maxItems: 2
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+ items:
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+ - const: rx
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+ - const: tx
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required:
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- reg
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@@ -43,6 +51,7 @@ examples:
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compatible = "brcm,bcm4908-enet";
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reg = <0x80002000 0x1000>;
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- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "rx";
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "rx", "tx";
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};
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