mirror of
				git://git.openwrt.org/openwrt/openwrt.git
				synced 2025-10-31 05:54:26 -04:00 
			
		
		
		
	This adds Kernel 5.10 support for the generic, nand and tiny subtargets. The following patch is not contained, as it needs to be reworked: platform/920-mikrotik-rb4xx.patch Tested-on: - Siemens WS-AP3610 - Enterasys WS-AP3710 - Aerohive HiveAP 121 - TP-Link TL-WA901 v2 - TP-Link TL-WR741 v1 Signed-off-by: David Bauer <mail@david-bauer.net>
		
			
				
	
	
		
			53 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			53 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| --- a/arch/mips/ath79/clock.c
 | |
| +++ b/arch/mips/ath79/clock.c
 | |
| @@ -40,6 +40,7 @@ static const char * const clk_names[ATH7
 | |
|  	[ATH79_CLK_AHB] = "ahb",
 | |
|  	[ATH79_CLK_REF] = "ref",
 | |
|  	[ATH79_CLK_MDIO] = "mdio",
 | |
| +	[ATH79_CLK_UART1] = "uart1",
 | |
|  };
 | |
|  
 | |
|  static const char * __init ath79_clk_name(int type)
 | |
| @@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo
 | |
|  	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
 | |
|  		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
 | |
|  
 | |
| +	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)
 | |
| +		ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);
 | |
| +
 | |
|  	iounmap(dpll_base);
 | |
|  }
 | |
|  
 | |
| @@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(
 | |
|  	if (!clks[ATH79_CLK_MDIO])
 | |
|  		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
 | |
|  
 | |
| +	if (!clks[ATH79_CLK_UART1])
 | |
| +		clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];
 | |
| +
 | |
|  	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
 | |
|  		pr_err("%pOF: could not register clk provider\n", np);
 | |
|  		goto err_iounmap;
 | |
| --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 | |
| +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 | |
| @@ -348,6 +348,7 @@
 | |
|  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
 | |
|  
 | |
|  #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
 | |
| +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL	BIT(7)
 | |
|  
 | |
|  #define QCA953X_PLL_CPU_CONFIG_REG		0x00
 | |
|  #define QCA953X_PLL_DDR_CONFIG_REG		0x04
 | |
| --- a/include/dt-bindings/clock/ath79-clk.h
 | |
| +++ b/include/dt-bindings/clock/ath79-clk.h
 | |
| @@ -11,7 +11,8 @@
 | |
|  #define ATH79_CLK_AHB		2
 | |
|  #define ATH79_CLK_REF		3
 | |
|  #define ATH79_CLK_MDIO		4
 | |
| +#define ATH79_CLK_UART1		5
 | |
|  
 | |
| -#define ATH79_CLK_END		5
 | |
| +#define ATH79_CLK_END		6
 | |
|  
 | |
|  #endif /* __DT_BINDINGS_ATH79_CLK_H */
 |