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6bac820c0f
Refresh backport patches with make target/linux/refresh. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
184 lines
7.1 KiB
Diff
184 lines
7.1 KiB
Diff
From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 14 Nov 2023 15:08:42 +0100
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Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
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Move MMD_VEND define to header to clean things up and in preparation for
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firmware loading support that require some define placed in
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aquantia_main.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/aquantia/aquantia.h | 69 +++++++++++++++++++++++
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drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
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drivers/net/phy/aquantia/aquantia_main.c | 55 ------------------
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3 files changed, 69 insertions(+), 69 deletions(-)
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--- a/drivers/net/phy/aquantia/aquantia.h
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+++ b/drivers/net/phy/aquantia/aquantia.h
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@@ -9,6 +9,75 @@
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#include <linux/device.h>
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#include <linux/phy.h>
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+/* Vendor specific 1, MDIO_MMD_VEND1 */
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+#define VEND1_GLOBAL_FW_ID 0x0020
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+#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
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+#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
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+
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+/* The following registers all have similar layouts; first the registers... */
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+#define VEND1_GLOBAL_CFG_10M 0x0310
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+#define VEND1_GLOBAL_CFG_100M 0x031b
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+#define VEND1_GLOBAL_CFG_1G 0x031c
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+#define VEND1_GLOBAL_CFG_2_5G 0x031d
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+#define VEND1_GLOBAL_CFG_5G 0x031e
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+#define VEND1_GLOBAL_CFG_10G 0x031f
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+/* ...and now the fields */
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
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+#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
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+
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+/* Vendor specific 1, MDIO_MMD_VEND2 */
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+#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
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+#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
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+#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
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+#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
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+#define VEND1_THERMAL_STAT1 0xc820
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+#define VEND1_THERMAL_STAT2 0xc821
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+#define VEND1_THERMAL_STAT2_VALID BIT(0)
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+#define VEND1_GENERAL_STAT1 0xc830
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+#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
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+#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
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+#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
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+#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
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+
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+#define VEND1_GLOBAL_GEN_STAT2 0xc831
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+#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
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+
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+#define VEND1_GLOBAL_RSVD_STAT1 0xc885
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+#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
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+#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
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+
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+#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
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+#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
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+#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
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+
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+#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
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+#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
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+
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+#define VEND1_GLOBAL_INT_STD_MASK 0xff00
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+#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
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+#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
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+#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
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+#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
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+#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
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+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
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+#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
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+#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
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+#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
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+#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
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+#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
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+
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+#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
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+#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
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+#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
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+#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
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+#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
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+#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
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+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
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+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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+#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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+
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#if IS_REACHABLE(CONFIG_HWMON)
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int aqr_hwmon_probe(struct phy_device *phydev);
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#else
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--- a/drivers/net/phy/aquantia/aquantia_hwmon.c
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+++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
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@@ -13,20 +13,6 @@
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#include "aquantia.h"
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-/* Vendor specific 1, MDIO_MMD_VEND2 */
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-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
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-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
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-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
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-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
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-#define VEND1_THERMAL_STAT1 0xc820
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-#define VEND1_THERMAL_STAT2 0xc821
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-#define VEND1_THERMAL_STAT2_VALID BIT(0)
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-#define VEND1_GENERAL_STAT1 0xc830
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-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
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-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
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-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
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-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
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-
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#if IS_REACHABLE(CONFIG_HWMON)
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static umode_t aqr_hwmon_is_visible(const void *data,
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--- a/drivers/net/phy/aquantia/aquantia_main.c
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+++ b/drivers/net/phy/aquantia/aquantia_main.c
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@@ -91,61 +91,6 @@
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#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
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#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
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-/* Vendor specific 1, MDIO_MMD_VEND1 */
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-#define VEND1_GLOBAL_FW_ID 0x0020
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-#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
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-#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
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-
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-#define VEND1_GLOBAL_GEN_STAT2 0xc831
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-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
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-
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-/* The following registers all have similar layouts; first the registers... */
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-#define VEND1_GLOBAL_CFG_10M 0x0310
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-#define VEND1_GLOBAL_CFG_100M 0x031b
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-#define VEND1_GLOBAL_CFG_1G 0x031c
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-#define VEND1_GLOBAL_CFG_2_5G 0x031d
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-#define VEND1_GLOBAL_CFG_5G 0x031e
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-#define VEND1_GLOBAL_CFG_10G 0x031f
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-/* ...and now the fields */
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-#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
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-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
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-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
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-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
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-
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-#define VEND1_GLOBAL_RSVD_STAT1 0xc885
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-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
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-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
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-
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-#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
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-#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
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-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
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-
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-#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
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-#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
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-
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-#define VEND1_GLOBAL_INT_STD_MASK 0xff00
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-#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
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-#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
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-#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
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-#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
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-#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
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-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
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-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
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-#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
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-#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
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-#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
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-#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
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-
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-#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
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-#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
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-#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
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-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
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-#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
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-#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
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-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
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-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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-
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/* Sleep and timeout for checking if the Processor-Intensive
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* MDIO operation is finished
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*/
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