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This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
188 lines
3.9 KiB
C
188 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Setup for the Realtek RTL838X SoC:
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* Memory, Timer and Serial
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*
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* Copyright (C) 2020 B. Koblitz
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* based on the original BSP by
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* Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
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*
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*/
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#include <linux/console.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <linux/of_fdt.h>
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#include <asm/reboot.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include "mach-rtl838x.h"
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extern int rtl838x_serial_init(void);
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extern struct rtl838x_soc_info soc_info;
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struct clk {
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struct clk_lookup cl;
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unsigned long rate;
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};
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struct clk cpu_clk;
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u32 pll_reset_value;
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static void rtl838x_restart(char *command)
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{
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u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
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/* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
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void (*f)(void) = (void *) 0xbfc00000;
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pr_info("System restart.\n");
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if (soc_info.family == RTL8390_FAMILY_ID) {
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f();
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/* If calling reset vector fails, reset entire chip */
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sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
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/* If this fails, halt the CPU */
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while
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(1);
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}
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pr_info("PLL control register: %x, applying reset value %x\n",
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pll, pll_reset_value);
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sw_w32(3, RTL838X_INT_RW_CTRL);
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sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
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sw_w32(0, RTL838X_INT_RW_CTRL);
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pr_info("Resetting RTL838X SoC\n");
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/* Reset Global Control1 Register */
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sw_w32(1, RTL838X_RST_GLB_CTRL_1);
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}
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static void rtl838x_halt(void)
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{
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pr_info("System halted.\n");
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while
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(1);
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}
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static void __init rtl838x_setup(void)
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{
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unsigned int val;
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pr_info("Registering _machine_restart\n");
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_machine_restart = rtl838x_restart;
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_machine_halt = rtl838x_halt;
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val = rtl838x_r32((volatile void *)0xBB0040000);
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if (val == 3)
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pr_info("PCI device found\n");
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else
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pr_info("NO PCI device found\n");
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/* Setup System LED. Bit 15 (14 for RTL8390) then allows to toggle it */
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if (soc_info.family == RTL8380_FAMILY_ID)
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sw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);
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else
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sw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);
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}
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void __init plat_mem_setup(void)
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{
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void *dtb;
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pr_info("%s called\n", __func__);
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set_io_port_base(KSEG1);
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if (fw_passed_dtb) /* UHI interface */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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panic("no dtb found");
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/*
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* Load the devicetree. This causes the chosen node to be
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* parsed resulting in our memory appearing
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*/
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__dt_setup_arch(dtb);
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rtl838x_setup();
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}
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/*
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* Linux clock API
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*/
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL_GPL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (!clk)
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return 0;
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return clk->rate;
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}
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EXPORT_SYMBOL_GPL(clk_get_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return -1;
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}
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EXPORT_SYMBOL_GPL(clk_set_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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return -1;
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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void __init plat_time_init(void)
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{
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u32 freq = 500000000;
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struct device_node *np;
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struct clk *clk = &cpu_clk;
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np = of_find_node_by_name(NULL, "cpus");
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if (!np) {
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pr_err("Missing 'cpus' DT node, using default frequency.");
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} else {
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if (of_property_read_u32(np, "frequency", &freq) < 0)
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pr_err("No 'frequency' property in DT, using default.");
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else
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pr_info("CPU frequency from device tree: %d", freq);
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of_node_put(np);
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}
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clk->rate = freq;
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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pr_info("CPU Clock: %ld MHz\n", clk->rate / 1000000);
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mips_hpt_frequency = freq / 2;
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pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
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pr_info("PLL control register: %x\n", pll_reset_value);
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/* With the info from the command line and cpu-freq we can setup the console */
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rtl838x_serial_init();
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}
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