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801c88295e
Add the patches with real changes from the binutils 2.40 stable branch. I am not aware that we ran into any of these problems, but I think it is better to take the existing stable patches. They were exported like this: git format-patch binutils-2_40...origin/binutils-2_40-branch I removed the patches changing the version numbers and updating the translations only. I removed the following patches: *Automatic-date-updat* 001-Re-enable-development.-Update-version-to-2.40.0.patch 004-Updated-translations-for-the-gas-and-binutils-sub-di.patch 015-Updated-Swedish-translation-for-the-binutils-sub-dir.patch 027-Updated-Swedish-translation-for-the-binutils-sub-dir.patch Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
210 lines
12 KiB
Diff
210 lines
12 KiB
Diff
From 3e888977f165594cf44dbe8f67e3a4960b22c11f Mon Sep 17 00:00:00 2001
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From: "Guillermo E. Martinez" <guillermo.e.martinez@oracle.com>
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Date: Fri, 3 Feb 2023 11:17:49 -0600
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Subject: [PATCH 34/50] bpf: fix error conversion from long unsigned int to
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unsigned int [-Werror=overflow]
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Regenerating BPF target using the maintainer mode emits:
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.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
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57 | 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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The use of a narrow size to handle the mask CGEN in instruction format
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is causing this error. Additionally eBPF `call' instructions
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constructed by expressions using symbols (BPF_PSEUDO_CALL) emits
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annotations in `src' field of the instruction, used to identify BPF
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target endianness.
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cpu/
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* bpf.cpu (define-call-insn): Remove `src' field from
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instruction mask.
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include/
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*opcode/cge.h (CGEN_IFMT): Adjust mask bit width.
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opcodes/
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* bpf-opc.c: Regenerate.
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(cherry picked from commit 7f6ebecd56e690012b05af0a492280765b17f186)
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---
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cpu/bpf.cpu | 2 +-
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include/opcode/cgen.h | 2 +-
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opcodes/bpf-opc.c | 54 +++++++++++++++++++++++--------------------
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opcodes/cgen-dis.c | 2 +-
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4 files changed, 32 insertions(+), 28 deletions(-)
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--- a/cpu/bpf.cpu
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+++ b/cpu/bpf.cpu
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@@ -768,7 +768,7 @@
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"call"
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(endian-isas x-endian)
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"call $disp32"
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- (+ disp32 (f-offset16 0) (f-regs 0)
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+ (+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0)
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OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
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(c-call VOID
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"bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
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--- a/include/opcode/cgen.h
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+++ b/include/opcode/cgen.h
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@@ -914,7 +914,7 @@ typedef struct
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Each insn's value is stored with the insn.
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The first step in recognizing an insn for disassembly is
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(opcode & mask) == value. */
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- CGEN_INSN_INT mask;
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+ CGEN_INSN_LGUINT mask;
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#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
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/* Instruction fields.
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--- a/opcodes/bpf-opc.c
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+++ b/opcodes/bpf-opc.c
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@@ -50,99 +50,103 @@ static const CGEN_IFMT ifmt_empty ATTRIB
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};
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static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
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- 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
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- 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+};
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+
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+static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {
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+ 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
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- 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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+ 64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
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};
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#undef F
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@@ -1646,7 +1650,7 @@ static const CGEN_OPCODE bpf_cgen_insn_o
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{
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{ 0, 0, 0, 0 },
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{ { MNEM, ' ', OP (DISP32), 0 } },
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- & ifmt_callle, { 0x85 }
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+ & ifmt_callbe, { 0x85 }
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},
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/* call $dstle */
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{
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--- a/opcodes/cgen-dis.c
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+++ b/opcodes/cgen-dis.c
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@@ -39,7 +39,7 @@ static void add_insn_to_hash_chain (CG
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static int
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count_decodable_bits (const CGEN_INSN *insn)
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{
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- unsigned mask = CGEN_INSN_BASE_MASK (insn);
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+ CGEN_INSN_LGUINT mask = CGEN_INSN_BASE_MASK (insn);
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#if GCC_VERSION >= 3004
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return __builtin_popcount (mask);
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#else
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