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f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
160 lines
5.6 KiB
Diff
160 lines
5.6 KiB
Diff
From cef08115846e581f80ff99abf7bf218da1840616 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Thu, 14 Oct 2021 00:39:18 +0200
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Subject: net: dsa: qca8k: set internal delay also for sgmii
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QCA original code report port instability and sa that SGMII also require
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to set internal delay. Generalize the rgmii delay function and apply the
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advised value if they are not defined in DT.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 88 +++++++++++++++++++++++++++++++++----------------
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drivers/net/dsa/qca8k.h | 2 ++
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2 files changed, 62 insertions(+), 28 deletions(-)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -1004,6 +1004,7 @@ qca8k_parse_port_config(struct qca8k_pri
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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+ case PHY_INTERFACE_MODE_SGMII:
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delay = 0;
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if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
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@@ -1036,8 +1037,13 @@ qca8k_parse_port_config(struct qca8k_pri
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priv->rgmii_rx_delay[cpu_port_index] = delay;
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- break;
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- case PHY_INTERFACE_MODE_SGMII:
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+ /* Skip sgmii parsing for rgmii* mode */
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+ if (mode == PHY_INTERFACE_MODE_RGMII ||
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+ mode == PHY_INTERFACE_MODE_RGMII_ID ||
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+ mode == PHY_INTERFACE_MODE_RGMII_TXID ||
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+ mode == PHY_INTERFACE_MODE_RGMII_RXID)
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+ break;
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+
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if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
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priv->sgmii_tx_clk_falling_edge = true;
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@@ -1261,12 +1267,53 @@ qca8k_setup(struct dsa_switch *ds)
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}
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static void
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+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
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+ u32 reg)
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+{
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+ u32 delay, val = 0;
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+ int ret;
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+
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+ /* Delay can be declared in 3 different way.
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+ * Mode to rgmii and internal-delay standard binding defined
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+ * rgmii-id or rgmii-tx/rx phy mode set.
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+ * The parse logic set a delay different than 0 only when one
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+ * of the 3 different way is used. In all other case delay is
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+ * not enabled. With ID or TX/RXID delay is enabled and set
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+ * to the default and recommended value.
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+ */
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+ if (priv->rgmii_tx_delay[cpu_port_index]) {
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+ delay = priv->rgmii_tx_delay[cpu_port_index];
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+
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+ val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
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+ }
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+
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+ if (priv->rgmii_rx_delay[cpu_port_index]) {
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+ delay = priv->rgmii_rx_delay[cpu_port_index];
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+
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+ val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
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+ }
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+
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+ /* Set RGMII delay based on the selected values */
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+ ret = qca8k_rmw(priv, reg,
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
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+ QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
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+ QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
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+ val);
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+ if (ret)
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+ dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
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+ cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
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+}
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+
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+static void
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qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct qca8k_priv *priv = ds->priv;
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int cpu_port_index, ret;
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- u32 reg, val, delay;
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+ u32 reg, val;
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switch (port) {
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case 0: /* 1st CPU port */
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@@ -1315,32 +1362,10 @@ qca8k_phylink_mac_config(struct dsa_swit
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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- val = QCA8K_PORT_PAD_RGMII_EN;
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-
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- /* Delay can be declared in 3 different way.
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- * Mode to rgmii and internal-delay standard binding defined
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- * rgmii-id or rgmii-tx/rx phy mode set.
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- * The parse logic set a delay different than 0 only when one
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- * of the 3 different way is used. In all other case delay is
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- * not enabled. With ID or TX/RXID delay is enabled and set
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- * to the default and recommended value.
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- */
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- if (priv->rgmii_tx_delay[cpu_port_index]) {
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- delay = priv->rgmii_tx_delay[cpu_port_index];
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-
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- val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
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- QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
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- }
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-
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- if (priv->rgmii_rx_delay[cpu_port_index]) {
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- delay = priv->rgmii_rx_delay[cpu_port_index];
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-
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- val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
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- QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
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- }
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+ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
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- /* Set RGMII delay based on the selected values */
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- qca8k_write(priv, reg, val);
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+ /* Configure rgmii delay */
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+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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/* QCA8337 requires to set rgmii rx delay for all ports.
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* This is enabled through PORT5_PAD_CTRL for all ports,
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@@ -1411,6 +1436,13 @@ qca8k_phylink_mac_config(struct dsa_swit
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QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
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QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
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val);
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+
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+ /* From original code is reported port instability as SGMII also
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+ * require delay set. Apply advised values here or take them from DT.
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+ */
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+ if (state->interface == PHY_INTERFACE_MODE_SGMII)
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+ qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
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+
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break;
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default:
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dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -39,7 +39,9 @@
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#define QCA8K_REG_PORT5_PAD_CTRL 0x008
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#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
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#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
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+#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
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#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
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+#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
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#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
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#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
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