mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-30 21:44:27 -04:00
f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
81 lines
2.3 KiB
Diff
81 lines
2.3 KiB
Diff
From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001
|
|
From: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Date: Thu, 14 Oct 2021 00:39:06 +0200
|
|
Subject: dsa: qca8k: add mac_power_sel support
|
|
|
|
Add missing mac power sel support needed for ipq8064/5 SoC that require
|
|
1.8v for the internal regulator port instead of the default 1.5v.
|
|
If other device needs this, consider adding a dedicated binding to
|
|
support this.
|
|
|
|
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
|
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++
|
|
drivers/net/dsa/qca8k.h | 5 +++++
|
|
2 files changed, 36 insertions(+)
|
|
|
|
--- a/drivers/net/dsa/qca8k.c
|
|
+++ b/drivers/net/dsa/qca8k.c
|
|
@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_
|
|
}
|
|
|
|
static int
|
|
+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
|
|
+{
|
|
+ u32 mask = 0;
|
|
+ int ret = 0;
|
|
+
|
|
+ /* SoC specific settings for ipq8064.
|
|
+ * If more device require this consider adding
|
|
+ * a dedicated binding.
|
|
+ */
|
|
+ if (of_machine_is_compatible("qcom,ipq8064"))
|
|
+ mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
|
|
+
|
|
+ /* SoC specific settings for ipq8065 */
|
|
+ if (of_machine_is_compatible("qcom,ipq8065"))
|
|
+ mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
|
|
+
|
|
+ if (mask) {
|
|
+ ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
|
|
+ QCA8K_MAC_PWR_RGMII0_1_8V |
|
|
+ QCA8K_MAC_PWR_RGMII1_1_8V,
|
|
+ mask);
|
|
+ }
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int
|
|
qca8k_setup(struct dsa_switch *ds)
|
|
{
|
|
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
|
|
@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)
|
|
if (ret)
|
|
return ret;
|
|
|
|
+ ret = qca8k_setup_mac_pwr_sel(priv);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
/* Enable CPU Port */
|
|
ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
|
|
QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
|
|
--- a/drivers/net/dsa/qca8k.h
|
|
+++ b/drivers/net/dsa/qca8k.h
|
|
@@ -100,6 +100,11 @@
|
|
#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
|
|
#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
|
|
|
|
+/* MAC_PWR_SEL registers */
|
|
+#define QCA8K_REG_MAC_PWR_SEL 0x0e4
|
|
+#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18)
|
|
+#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19)
|
|
+
|
|
/* EEE control registers */
|
|
#define QCA8K_REG_EEE_CTRL 0x100
|
|
#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
|