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d8ac24b325
Update bmips cleanup patches with upstream submission and backport a few bmips fixes. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39267
42 lines
1.5 KiB
Diff
42 lines
1.5 KiB
Diff
From c4091d3fbbed922a3641e5e749655e49cc0d4dee Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 24 Jul 2013 17:12:10 +0100
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Subject: [PATCH] MIPS: BMIPS: do not change interrupt routing depending on
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boot CPU
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Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
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than 0") changed the interupt routing when we are booting from physical
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CPU 0, but the settings are actually correct if we are booting from
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physical CPU 0 or CPU 1. Revert that specific change.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: cernekee@gmail.com
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Cc: jogo@openwrt.org
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Cc: blogic@openwrt.org
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Patchwork: https://patchwork.linux-mips.org/patch/5622/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/kernel/smp-bmips.c | 8 +-------
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1 file changed, 1 insertion(+), 7 deletions(-)
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--- a/arch/mips/kernel/smp-bmips.c
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+++ b/arch/mips/kernel/smp-bmips.c
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@@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void)
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* MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
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* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
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* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
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- *
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- * If booting from TP1, leave the existing CMT interrupt routing
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- * such that TP0 responds to SW1 and TP1 responds to SW0.
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*/
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- if (boot_cpu == 0)
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- change_c0_brcm_cmt_intr(0xf8018000,
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+ change_c0_brcm_cmt_intr(0xf8018000,
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(0x02 << 27) | (0x03 << 15));
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- else
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- change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
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/* single core, 2 threads (2 pipelines) */
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max_cpus = 2;
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