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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
141 lines
4.2 KiB
Diff
141 lines
4.2 KiB
Diff
From bc3f8207d9f0af3cb96a7eae232074a644a175f6 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Mon, 8 Jan 2024 19:06:09 +0800
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Subject: [PATCH 032/116] dt-bindings: PCI: Add StarFive JH7110 PCIe controller
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Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA
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XpressRICH PCIe host controller IP.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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---
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.../bindings/pci/starfive,jh7110-pcie.yaml | 120 ++++++++++++++++++
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1 file changed, 120 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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@@ -0,0 +1,120 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 PCIe host controller
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+
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+maintainers:
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+ - Kevin Xie <kevin.xie@starfivetech.com>
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+
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+allOf:
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+ - $ref: plda,xpressrich3-axi-common.yaml#
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-pcie
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+
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+ clocks:
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+ items:
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+ - description: NOC bus clock
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+ - description: Transport layer clock
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+ - description: AXI MST0 clock
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+ - description: APB clock
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+
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+ clock-names:
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+ items:
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+ - const: noc
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+ - const: tl
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+ - const: axi_mst0
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+ - const: apb
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+
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+ resets:
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+ items:
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+ - description: AXI MST0 reset
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+ - description: AXI SLAVE0 reset
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+ - description: AXI SLAVE reset
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+ - description: PCIE BRIDGE reset
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+ - description: PCIE CORE reset
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+ - description: PCIE APB reset
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+
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+ reset-names:
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+ items:
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+ - const: mst0
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+ - const: slv0
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+ - const: slv
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+ - const: brg
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+ - const: core
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+ - const: apb
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+
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+ starfive,stg-syscon:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ description:
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+ The phandle to System Register Controller syscon node.
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+
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+ perst-gpios:
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+ description: GPIO controlled connection to PERST# signal
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+ maxItems: 1
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+
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+ phys:
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+ description:
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+ Specified PHY is attached to PCIe controller.
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+ maxItems: 1
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+
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+required:
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+ - clocks
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+ - resets
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+ - starfive,stg-syscon
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/gpio/gpio.h>
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ pcie@940000000 {
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+ compatible = "starfive,jh7110-pcie";
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+ reg = <0x9 0x40000000 0x0 0x10000000>,
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+ <0x0 0x2b000000 0x0 0x1000000>;
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+ reg-names = "cfg", "apb";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ device_type = "pci";
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+ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
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+ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
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+ starfive,stg-syscon = <&stg_syscon>;
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+ bus-range = <0x0 0xff>;
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+ interrupt-parent = <&plic>;
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+ interrupts = <56>;
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
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+ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
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+ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
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+ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
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+ msi-controller;
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+ clocks = <&syscrg 86>,
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+ <&stgcrg 10>,
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+ <&stgcrg 8>,
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+ <&stgcrg 9>;
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+ clock-names = "noc", "tl", "axi_mst0", "apb";
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+ resets = <&stgcrg 11>,
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+ <&stgcrg 12>,
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+ <&stgcrg 13>,
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+ <&stgcrg 14>,
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+ <&stgcrg 15>,
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+ <&stgcrg 16>;
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+ perst-gpios = <&gpios 26 GPIO_ACTIVE_LOW>;
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+ phys = <&pciephy0>;
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+
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+ pcie_intc0: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+ };
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