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d9386dc8e9
Drop backported patches already included in 6.6 and refresh the rest to apply. Signed-off-by: Robert Marko <robimarko@gmail.com>
114 lines
3.5 KiB
Diff
114 lines
3.5 KiB
Diff
From 0b9cd949136f1b63f7aa9424b6e583a1ab261e36 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 13 Oct 2023 19:20:02 +0200
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Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
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IPQ8074 comes in 3 families:
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* IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
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* IPQ8172/IPQ8173/IPQ8174 (Oak) up to 1.4GHz
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* IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
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So, in order to be able to share one OPP table lets add support for IPQ8074
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family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
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IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
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will get created by NVMEM CPUFreq driver.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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[ Viresh: Fixed rebase conflict. ]
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 48 ++++++++++++++++++++++++++++
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2 files changed, 49 insertions(+)
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--- a/drivers/cpufreq/cpufreq-dt-platdev.c
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+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
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@@ -179,6 +179,7 @@ static const struct of_device_id blockli
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{ .compatible = "qcom,ipq6018", },
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{ .compatible = "qcom,ipq8064", },
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+ { .compatible = "qcom,ipq8074", },
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{ .compatible = "qcom,apq8064", },
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{ .compatible = "qcom,msm8974", },
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{ .compatible = "qcom,msm8960", },
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -32,6 +32,11 @@
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#define IPQ6000_VERSION BIT(2)
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+enum ipq8074_versions {
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+ IPQ8074_HAWKEYE_VERSION = 0,
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+ IPQ8074_ACORN_VERSION,
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+};
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+
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struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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@@ -256,6 +261,44 @@ static int qcom_cpufreq_ipq6018_name_ver
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return 0;
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}
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+static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
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+ struct nvmem_cell *speedbin_nvmem,
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+ char **pvs_name,
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+ struct qcom_cpufreq_drv *drv)
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+{
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+ u32 msm_id;
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+ int ret;
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+ *pvs_name = NULL;
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+
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+ ret = qcom_smem_get_soc_id(&msm_id);
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+ if (ret)
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+ return ret;
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+
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+ switch (msm_id) {
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+ case QCOM_ID_IPQ8070A:
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+ case QCOM_ID_IPQ8071A:
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+ case QCOM_ID_IPQ8172:
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+ case QCOM_ID_IPQ8173:
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+ case QCOM_ID_IPQ8174:
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+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
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+ break;
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+ case QCOM_ID_IPQ8072A:
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+ case QCOM_ID_IPQ8074A:
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+ case QCOM_ID_IPQ8076A:
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+ case QCOM_ID_IPQ8078A:
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+ drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
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+ break;
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+ default:
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+ dev_err(cpu_dev,
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+ "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
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+ msm_id);
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+ drv->versions = BIT(IPQ8074_ACORN_VERSION);
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static const struct qcom_cpufreq_match_data match_data_kryo = {
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.get_version = qcom_cpufreq_kryo_name_version,
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};
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@@ -274,6 +317,10 @@ static const struct qcom_cpufreq_match_d
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.get_version = qcom_cpufreq_ipq6018_name_version,
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};
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+static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
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+ .get_version = qcom_cpufreq_ipq8074_name_version,
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+};
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+
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static int qcom_cpufreq_probe(struct platform_device *pdev)
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{
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struct qcom_cpufreq_drv *drv;
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@@ -418,6 +465,7 @@ static const struct of_device_id qcom_cp
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{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
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{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
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{ .compatible = "qcom,ipq8064", .data = &match_data_krait },
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+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
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{ .compatible = "qcom,apq8064", .data = &match_data_krait },
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{ .compatible = "qcom,msm8974", .data = &match_data_krait },
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{ .compatible = "qcom,msm8960", .data = &match_data_krait },
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