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4f277b4da5
A lot of patches are outdated versions of upstreamed patches and drivers. So lets pull in the upstreamed patches and reorder remaining ones. This drops the unnecessary 721-dts-ipq4019-add-ethernet-essedma-node.patch which adds nodes for not yet in OpenWrt IPQESS driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> [do not touch 902-dts-ipq4019-ap-dk04.1.patch here] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
116 lines
3.5 KiB
Diff
116 lines
3.5 KiB
Diff
From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
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From: Christian Lamparter <chunkeey@googlemail.com>
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Date: Sun, 11 Mar 2018 14:41:31 +0100
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Subject: [PATCH 2/2] clk: fix apss cpu overclocking
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There's an interaction issue between the clk changes:"
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clk: qcom: ipq4019: Add the apss cpu pll divider clock node
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clk: qcom: ipq4019: remove fixed clocks and add pll clocks
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" and the cpufreq-dt.
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cpufreq-dt is now spamming the kernel-log with the following:
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[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
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for freq 761142857 (-34)
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This only happens on certain devices like the Compex WPJ428
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and AVM FritzBox!4040. However, other devices like the Asus
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RT-AC58U and Meraki MR33 work just fine.
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The issue stem from the fact that all higher CPU-Clocks
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are achieved by switching the clock-parent to the P_DDRPLLAPSS
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(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
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as part of the DDR calibration.
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For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
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at round 533 MHz (ddrpllsdcc = 190285714 Hz).
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whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
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clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
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This patch attempts to fix the issue by modifying
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clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
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to use a new qcom_find_freq_close() function, which returns the closest
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matching frequency, instead of the next higher. This way, the SoC in
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the FB4040 (with its max clock speed of 710.4 MHz) will no longer
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try to overclock to 761 MHz.
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Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
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1 file changed, 31 insertions(+), 3 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq4019.c
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+++ b/drivers/clk/qcom/gcc-ipq4019.c
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@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
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.reg = 0x2f020,
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};
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+
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+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
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+ unsigned long rate)
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+{
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+ const struct freq_tbl *last = NULL;
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+
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+ for ( ; f->freq; f++) {
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+ if (rate == f->freq)
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+ return f;
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+
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+ if (f->freq > rate) {
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+ if (!last ||
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+ (f->freq - rate) < (rate - last->freq))
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+ return f;
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+ else
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+ return last;
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+ }
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+ last = f;
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+ }
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+
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+ return last;
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+}
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+
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/*
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* Round rate function for APSS CPU PLL Clock divider.
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* It looks up the frequency table and returns the next higher frequency
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@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
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struct clk_hw *p_hw;
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const struct freq_tbl *f;
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- f = qcom_find_freq(pll->freq_tbl, rate);
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+ f = qcom_find_freq_close(pll->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
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u32 mask;
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int ret;
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- f = qcom_find_freq(pll->freq_tbl, rate);
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+ f = qcom_find_freq_close(pll->freq_tbl, rate);
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if (!f)
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return -EINVAL;
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@@ -1305,6 +1328,7 @@ static unsigned long
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clk_cpu_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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+ const struct freq_tbl *f;
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struct clk_fepll *pll = to_clk_fepll(hw);
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u32 cdiv, pre_div;
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u64 rate;
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@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
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rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
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do_div(rate, pre_div);
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- return rate;
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+ f = qcom_find_freq_close(pll->freq_tbl, rate);
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+ if (!f)
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+ return rate;
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+
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+ return f->freq;
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};
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static const struct clk_ops clk_regmap_cpu_div_ops = {
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