mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 05:54:26 -04:00
347 lines
8.6 KiB
C
347 lines
8.6 KiB
C
#include <linux/ioport.h>
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#include <rt305x_regs.h>
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#include <rt305x_esw_platform.h>
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#define RT305X_ESW_REG_FCT0 0x08
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#define RT305X_ESW_REG_PFC1 0x14
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#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
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#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
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#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
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#define RT305X_ESW_REG_FPA 0x84
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#define RT305X_ESW_REG_SOCPC 0x8c
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#define RT305X_ESW_REG_POC1 0x90
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#define RT305X_ESW_REG_POC2 0x94
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#define RT305X_ESW_REG_POC3 0x98
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#define RT305X_ESW_REG_SGC 0x9c
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#define RT305X_ESW_REG_PCR0 0xc0
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#define RT305X_ESW_REG_PCR1 0xc4
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#define RT305X_ESW_REG_FPA2 0xc8
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#define RT305X_ESW_REG_FCT2 0xcc
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#define RT305X_ESW_REG_SGC2 0xe4
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#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
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#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
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#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
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#define RT305X_ESW_PCR1_WT_DONE BIT(0)
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#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
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#define RT305X_ESW_PVIDC_PVID_M 0xfff
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#define RT305X_ESW_PVIDC_PVID_S 12
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#define RT305X_ESW_VLANI_VID_M 0xfff
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#define RT305X_ESW_VLANI_VID_S 12
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#define RT305X_ESW_VMSC_MSC_M 0xff
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#define RT305X_ESW_VMSC_MSC_S 8
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#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
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#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
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#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
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#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
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#define RT305X_ESW_POC1_EN_BP_S 0
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#define RT305X_ESW_POC1_EN_FC_S 8
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#define RT305X_ESW_POC1_DIS_RMC2CPU_S 16
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#define RT305X_ESW_POC1_DIS_PORT_S 23
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#define RT305X_ESW_POC3_UNTAG_EN_S 0
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#define RT305X_ESW_POC3_ENAGING_S 8
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#define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
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#define RT305X_ESW_PORT0 0
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#define RT305X_ESW_PORT1 1
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#define RT305X_ESW_PORT2 2
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#define RT305X_ESW_PORT3 3
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#define RT305X_ESW_PORT4 4
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#define RT305X_ESW_PORT5 5
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#define RT305X_ESW_PORT6 6
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#define RT305X_ESW_PORTS_INTERNAL \
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(BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
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BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
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BIT(RT305X_ESW_PORT4))
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#define RT305X_ESW_PORTS_NOCPU \
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(RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
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#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
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#define RT305X_ESW_PORTS_ALL \
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(RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
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struct rt305x_esw {
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void __iomem *base;
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struct rt305x_esw_platform_data *pdata;
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spinlock_t reg_rw_lock;
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};
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static inline void
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rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
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{
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__raw_writel(val, esw->base + reg);
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}
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static inline u32
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rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
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{
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return __raw_readl(esw->base + reg);
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}
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static inline void
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rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long t;
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t = __raw_readl(esw->base + reg) & ~mask;
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__raw_writel(t | val, esw->base + reg);
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}
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static void
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rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
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unsigned long val)
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{
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unsigned long flags;
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spin_lock_irqsave(&esw->reg_rw_lock, flags);
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rt305x_esw_rmw_raw(esw, reg, mask, val);
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spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
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}
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static u32
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rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
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u32 write_data)
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{
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unsigned long t_start = jiffies;
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int ret = 0;
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while (1) {
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if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE))
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break;
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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goto out;
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}
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}
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write_data &= 0xffff;
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rt305x_esw_wr(esw,
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(write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
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(phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
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(phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
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RT305X_ESW_REG_PCR0);
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t_start = jiffies;
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while (1) {
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if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
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RT305X_ESW_PCR1_WT_DONE)
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break;
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if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
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ret = 1;
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break;
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}
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}
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out:
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if (ret)
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printk(KERN_ERR "ramips_eth: MDIO timeout\n");
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return ret;
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}
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static void
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rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
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{
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unsigned s;
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s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_VLANI(vlan / 2),
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RT305X_ESW_VLANI_VID_M << s,
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(vid & RT305X_ESW_VLANI_VID_M) << s);
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}
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static void
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rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
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{
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unsigned s;
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s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_PVIDC(port / 2),
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RT305X_ESW_PVIDC_PVID_M << s,
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(pvid & RT305X_ESW_PVIDC_PVID_M) << s);
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}
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static void
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rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
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{
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unsigned s;
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s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
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rt305x_esw_rmw(esw,
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RT305X_ESW_REG_VMSC(vlan / 4),
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RT305X_ESW_VMSC_MSC_M << s,
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(msc & RT305X_ESW_VMSC_MSC_M) << s);
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}
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static void
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rt305x_esw_hw_init(struct rt305x_esw *esw)
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{
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int i;
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/* vodoo from original driver */
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rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
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rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
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rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
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/* Enable Back Pressure, and Flow Control */
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
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(RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
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RT305X_ESW_REG_POC1);
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/* Enable Aging, and VLAN TAG removal */
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rt305x_esw_wr(esw,
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((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
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(RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
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RT305X_ESW_REG_POC3);
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rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
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rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
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/* Setup SoC Port control register */
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rt305x_esw_wr(esw,
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(RT305X_ESW_SOCPC_CRC_PADDING |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
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(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
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RT305X_ESW_REG_SOCPC);
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rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
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rt305x_esw_set_pvid(esw, RT305X_ESW_PORT5, 1);
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rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
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rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
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rt305x_mii_write(esw, 0, 31, 0x8000);
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for (i = 0; i < 5; i++) {
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/* TX10 waveform coefficient */
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rt305x_mii_write(esw, i, 0, 0x3100);
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/* TX10 waveform coefficient */
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rt305x_mii_write(esw, i, 26, 0x1601);
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/* TX100/TX10 AD/DA current bias */
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rt305x_mii_write(esw, i, 29, 0x7058);
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/* TX100 slew rate control */
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rt305x_mii_write(esw, i, 30, 0x0018);
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}
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/* PHY IOT */
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/* select global register */
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rt305x_mii_write(esw, 0, 31, 0x0);
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/* tune TP_IDL tail and head waveform */
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rt305x_mii_write(esw, 0, 22, 0x052f);
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/* set TX10 signal amplitude threshold to minimum */
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rt305x_mii_write(esw, 0, 17, 0x0fe0);
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/* set squelch amplitude to higher threshold */
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rt305x_mii_write(esw, 0, 18, 0x40ba);
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/* longer TP_IDL tail length */
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rt305x_mii_write(esw, 0, 14, 0x65);
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/* select local register */
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rt305x_mii_write(esw, 0, 31, 0x8000);
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/* set default vlan */
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rt305x_esw_set_vlan_id(esw, 0, 1);
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rt305x_esw_set_vlan_id(esw, 1, 2);
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rt305x_esw_set_vmsc(esw, 0,
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(BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
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BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
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BIT(RT305X_ESW_PORT6)));
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rt305x_esw_set_vmsc(esw, 1,
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(BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6)));
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rt305x_esw_set_vmsc(esw, 2, 0);
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rt305x_esw_set_vmsc(esw, 3, 0);
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}
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static int
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rt305x_esw_probe(struct platform_device *pdev)
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{
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struct rt305x_esw_platform_data *pdata;
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struct rt305x_esw *esw;
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struct resource *res;
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int err;
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pdata = pdev->dev.platform_data;
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if (!pdata)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "no memory resource found\n");
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return -ENOMEM;
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}
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esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
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if (!esw) {
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dev_err(&pdev->dev, "no memory for private data\n");
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return -ENOMEM;
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}
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esw->base = ioremap(res->start, resource_size(res));
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if (!esw->base) {
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dev_err(&pdev->dev, "ioremap failed\n");
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err = -ENOMEM;
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goto free_esw;
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}
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platform_set_drvdata(pdev, esw);
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esw->pdata = pdata;
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spin_lock_init(&esw->reg_rw_lock);
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rt305x_esw_hw_init(esw);
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return 0;
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free_esw:
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kfree(esw);
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return err;
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}
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static int
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rt305x_esw_remove(struct platform_device *pdev)
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{
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struct rt305x_esw *esw;
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esw = platform_get_drvdata(pdev);
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if (esw) {
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platform_set_drvdata(pdev, NULL);
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iounmap(esw->base);
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kfree(esw);
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}
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return 0;
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}
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static struct platform_driver rt305x_esw_driver = {
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.probe = rt305x_esw_probe,
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.remove = rt305x_esw_remove,
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.driver = {
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.name = "rt305x-esw",
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.owner = THIS_MODULE,
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},
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};
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static int __init
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rt305x_esw_init(void)
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{
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return platform_driver_register(&rt305x_esw_driver);
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}
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static void __exit
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rt305x_esw_exit(void)
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{
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platform_driver_unregister(&rt305x_esw_driver);
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}
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