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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
114 lines
2.9 KiB
Diff
114 lines
2.9 KiB
Diff
From 944b96d734199642e2ede978c48d754109ca334c Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Mon, 20 Mar 2023 21:54:31 +0800
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Subject: [PATCH 059/122] dt-bindings: timer: Add timer for StarFive JH7110 SoC
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Add bindings for the timer on the JH7110 RISC-V SoC
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by StarFive Technology Ltd.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
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1 file changed, 95 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
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@@ -0,0 +1,95 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 Timer
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+maintainers:
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+ - Xingyu Wu <xingyu.wu@starfivetech.com>
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+ - Samin Guo <samin.guo@starfivetech.com>
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+
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+description:
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+ This timer has four free-running 32 bit counters in StarFive JH7110 SoC.
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+ And each channel(counter) triggers an interrupt when timeout. They support
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+ one-shot mode and continuous-run mode.
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-timer
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+
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+ reg:
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+ maxItems: 1
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+
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+ interrupts:
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+ items:
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+ - description: channel 0
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+ - description: channel 1
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+ - description: channel 2
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+ - description: channel 3
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+
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+ clocks:
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+ items:
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+ - description: timer APB
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+ - description: channel 0
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+ - description: channel 1
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+ - description: channel 2
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+ - description: channel 3
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+
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+ clock-names:
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+ items:
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+ - const: apb
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+ - const: ch0
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+ - const: ch1
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+ - const: ch2
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+ - const: ch3
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+
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+ resets:
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+ items:
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+ - description: timer APB
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+ - description: channel 0
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+ - description: channel 1
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+ - description: channel 2
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+ - description: channel 3
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+
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+ reset-names:
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+ items:
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+ - const: apb
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+ - const: ch0
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+ - const: ch1
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+ - const: ch2
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+ - const: ch3
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupts
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ timer@13050000 {
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+ compatible = "starfive,jh7110-timer";
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+ reg = <0x13050000 0x10000>;
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+ interrupts = <69>, <70>, <71> ,<72>;
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+ clocks = <&clk 124>,
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+ <&clk 125>,
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+ <&clk 126>,
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+ <&clk 127>,
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+ <&clk 128>;
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+ clock-names = "apb", "ch0", "ch1",
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+ "ch2", "ch3";
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+ resets = <&rst 117>,
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+ <&rst 118>,
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+ <&rst 119>,
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+ <&rst 120>,
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+ <&rst 121>;
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+ reset-names = "apb", "ch0", "ch1",
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+ "ch2", "ch3";
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+ };
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+
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