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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
216 lines
7.3 KiB
Diff
216 lines
7.3 KiB
Diff
From dbee38aac9811a25e3e3204f813048bf64155248 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:22 +0800
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Subject: [PATCH 010/122] reset: starfive: Extract the common JH71X0 reset code
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Extract the common JH71X0 reset code for reusing them to
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support JH7110 SoC.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../reset/starfive/reset-starfive-jh7100.c | 49 ++++++++++++
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.../reset/starfive/reset-starfive-jh71x0.c | 76 ++++++-------------
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.../reset/starfive/reset-starfive-jh71x0.h | 5 +-
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3 files changed, 76 insertions(+), 54 deletions(-)
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--- a/drivers/reset/starfive/reset-starfive-jh7100.c
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+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
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@@ -10,6 +10,55 @@
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#include "reset-starfive-jh71x0.h"
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+#include <dt-bindings/reset/starfive-jh7100.h>
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+
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+/* register offsets */
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+#define JH7100_RESET_ASSERT0 0x00
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+#define JH7100_RESET_ASSERT1 0x04
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+#define JH7100_RESET_ASSERT2 0x08
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+#define JH7100_RESET_ASSERT3 0x0c
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+#define JH7100_RESET_STATUS0 0x10
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+#define JH7100_RESET_STATUS1 0x14
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+#define JH7100_RESET_STATUS2 0x18
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+#define JH7100_RESET_STATUS3 0x1c
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+
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+/*
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+ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
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+ * line 32m + n, and writing a 0 deasserts the same line.
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+ * Most reset lines have their status inverted so a 0 bit in the STATUS
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+ * register means the line is asserted and a 1 means it's deasserted. A few
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+ * lines don't though, so store the expected value of the status registers when
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+ * all lines are asserted.
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+ */
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+static const u64 jh7100_reset_asserted[2] = {
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+ /* STATUS0 */
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+ BIT_ULL_MASK(JH7100_RST_U74) |
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+ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
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+ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
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+ /* STATUS1 */
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+ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
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+ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
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+ /* STATUS2 */
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+ BIT_ULL_MASK(JH7100_RST_E24) |
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+ /* STATUS3 */
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+ 0,
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+};
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+
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+static int __init jh7100_reset_probe(struct platform_device *pdev)
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+{
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+ void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
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+
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
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+ base + JH7100_RESET_ASSERT0,
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+ base + JH7100_RESET_STATUS0,
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+ jh7100_reset_asserted,
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+ JH7100_RSTN_END,
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+ THIS_MODULE);
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+}
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+
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static const struct of_device_id jh7100_reset_dt_ids[] = {
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{ .compatible = "starfive,jh7100-reset" },
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{ /* sentinel */ }
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
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@@ -10,51 +10,18 @@
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#include <linux/io.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/iopoll.h>
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-#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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#include "reset-starfive-jh71x0.h"
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-#include <dt-bindings/reset/starfive-jh7100.h>
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-
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-/* register offsets */
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-#define JH7100_RESET_ASSERT0 0x00
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-#define JH7100_RESET_ASSERT1 0x04
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-#define JH7100_RESET_ASSERT2 0x08
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-#define JH7100_RESET_ASSERT3 0x0c
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-#define JH7100_RESET_STATUS0 0x10
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-#define JH7100_RESET_STATUS1 0x14
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-#define JH7100_RESET_STATUS2 0x18
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-#define JH7100_RESET_STATUS3 0x1c
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-
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-/*
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- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
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- * line 32m + n, and writing a 0 deasserts the same line.
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- * Most reset lines have their status inverted so a 0 bit in the STATUS
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- * register means the line is asserted and a 1 means it's deasserted. A few
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- * lines don't though, so store the expected value of the status registers when
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- * all lines are asserted.
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- */
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-static const u64 jh7100_reset_asserted[2] = {
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- /* STATUS0 */
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- BIT_ULL_MASK(JH7100_RST_U74) |
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- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
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- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
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- /* STATUS1 */
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- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
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- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
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- /* STATUS2 */
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- BIT_ULL_MASK(JH7100_RST_E24) |
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- /* STATUS3 */
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- 0,
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-};
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-
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struct jh7100_reset {
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struct reset_controller_dev rcdev;
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/* protect registers against concurrent read-modify-write */
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spinlock_t lock;
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- void __iomem *base;
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+ void __iomem *assert;
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+ void __iomem *status;
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+ const u64 *asserted;
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};
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static inline struct jh7100_reset *
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@@ -69,9 +36,9 @@ static int jh7100_reset_update(struct re
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struct jh7100_reset *data = jh7100_reset_from(rcdev);
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unsigned long offset = BIT_ULL_WORD(id);
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u64 mask = BIT_ULL_MASK(id);
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- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
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- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
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- u64 done = jh7100_reset_asserted[offset] & mask;
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+ void __iomem *reg_assert = data->assert + offset * sizeof(u64);
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+ void __iomem *reg_status = data->status + offset * sizeof(u64);
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+ u64 done = data->asserted ? data->asserted[offset] & mask : 0;
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u64 value;
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unsigned long flags;
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int ret;
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@@ -125,10 +92,10 @@ static int jh7100_reset_status(struct re
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struct jh7100_reset *data = jh7100_reset_from(rcdev);
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unsigned long offset = BIT_ULL_WORD(id);
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u64 mask = BIT_ULL_MASK(id);
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- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
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+ void __iomem *reg_status = data->status + offset * sizeof(u64);
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u64 value = readq(reg_status);
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- return !((value ^ jh7100_reset_asserted[offset]) & mask);
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+ return !((value ^ data->asserted[offset]) & mask);
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}
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static const struct reset_control_ops jh7100_reset_ops = {
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@@ -138,25 +105,28 @@ static const struct reset_control_ops jh
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.status = jh7100_reset_status,
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};
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-int jh7100_reset_probe(struct platform_device *pdev)
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+int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
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+ void __iomem *assert, void __iomem *status,
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+ const u64 *asserted, unsigned int nr_resets,
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+ struct module *owner)
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{
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struct jh7100_reset *data;
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- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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- data->base = devm_platform_ioremap_resource(pdev, 0);
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- if (IS_ERR(data->base))
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- return PTR_ERR(data->base);
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-
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data->rcdev.ops = &jh7100_reset_ops;
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- data->rcdev.owner = THIS_MODULE;
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- data->rcdev.nr_resets = JH7100_RSTN_END;
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- data->rcdev.dev = &pdev->dev;
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- data->rcdev.of_node = pdev->dev.of_node;
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+ data->rcdev.owner = owner;
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+ data->rcdev.nr_resets = nr_resets;
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+ data->rcdev.dev = dev;
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+ data->rcdev.of_node = of_node;
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+
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spin_lock_init(&data->lock);
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+ data->assert = assert;
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+ data->status = status;
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+ data->asserted = asserted;
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- return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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+ return devm_reset_controller_register(dev, &data->rcdev);
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}
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-EXPORT_SYMBOL_GPL(jh7100_reset_probe);
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+EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
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@@ -6,6 +6,9 @@
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#ifndef __RESET_STARFIVE_JH71X0_H
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#define __RESET_STARFIVE_JH71X0_H
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-int jh7100_reset_probe(struct platform_device *pdev);
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+int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
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+ void __iomem *assert, void __iomem *status,
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+ const u64 *asserted, unsigned int nr_resets,
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+ struct module *owner);
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#endif /* __RESET_STARFIVE_JH71X0_H */
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