mirror of
git://git.openwrt.org/openwrt/openwrt.git
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572ea68070
Import pending patches adding support for MT7988 and provide builds for the reference board for all possible boot media. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
From 0d6d8a408f80358dd47984320ea9c65e555ac4c9 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 19 Jul 2023 17:15:54 +0800
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Subject: [PATCH 03/29] spi: mtk_spim: get spi clk rate only once
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We don't really need to switch clk rate during operating SPIM controller.
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Get clk rate only once at driver probing.
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Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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---
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drivers/spi/mtk_spim.c | 21 +++++++++++++--------
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1 file changed, 13 insertions(+), 8 deletions(-)
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--- a/drivers/spi/mtk_spim.c
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+++ b/drivers/spi/mtk_spim.c
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@@ -137,6 +137,8 @@ struct mtk_spim_capability {
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* @state: Controller state
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* @sel_clk: Pad clock
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* @spi_clk: Core clock
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+ * @pll_clk_rate: Controller's PLL source clock rate, which is different
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+ * from SPI bus clock rate
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* @xfer_len: Current length of data for transfer
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* @hw_cap: Controller capabilities
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* @tick_dly: Used to postpone SPI sampling time
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@@ -149,6 +151,7 @@ struct mtk_spim_priv {
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void __iomem *base;
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u32 state;
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struct clk sel_clk, spi_clk;
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+ u32 pll_clk_rate;
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u32 xfer_len;
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struct mtk_spim_capability hw_cap;
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u32 tick_dly;
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@@ -253,11 +256,10 @@ static int mtk_spim_hw_init(struct spi_s
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static void mtk_spim_prepare_transfer(struct mtk_spim_priv *priv,
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u32 speed_hz)
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{
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- u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
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+ u32 div, sck_time, cs_time, reg_val;
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- spi_clk_hz = clk_get_rate(&priv->spi_clk);
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- if (speed_hz <= spi_clk_hz / 4)
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- div = DIV_ROUND_UP(spi_clk_hz, speed_hz);
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+ if (speed_hz <= priv->pll_clk_rate / 4)
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+ div = DIV_ROUND_UP(priv->pll_clk_rate, speed_hz);
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else
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div = 4;
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@@ -404,7 +406,7 @@ static int mtk_spim_transfer_wait(struct
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{
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struct udevice *bus = dev_get_parent(slave->dev);
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struct mtk_spim_priv *priv = dev_get_priv(bus);
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- u32 sck_l, sck_h, spi_bus_clk, clk_count, reg;
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+ u32 sck_l, sck_h, clk_count, reg;
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ulong us = 1;
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int ret = 0;
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@@ -413,12 +415,11 @@ static int mtk_spim_transfer_wait(struct
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else
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clk_count = op->data.nbytes;
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- spi_bus_clk = clk_get_rate(&priv->spi_clk);
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sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
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sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
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- do_div(spi_bus_clk, sck_l + sck_h + 2);
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+ do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
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- us = CLK_TO_US(spi_bus_clk, clk_count * 8);
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+ us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
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us += 1000 * 1000; /* 1s tolerance */
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if (us > UINT_MAX)
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@@ -662,6 +663,10 @@ static int mtk_spim_probe(struct udevice
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clk_enable(&priv->sel_clk);
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clk_enable(&priv->spi_clk);
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+ priv->pll_clk_rate = clk_get_rate(&priv->spi_clk);
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+ if (priv->pll_clk_rate == 0)
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+ return -EINVAL;
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+
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return 0;
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}
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