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cc410a18eb
The following patches were removed: * 010-486180-Valgrind-MIPS-VexGuestArchState-has-no-member.patch [1] * 020-mips-skip-using-shared-syscall-numbers-for-mips32.patch [2] * 021-mips-skip-using-shared-syscall-numbers-for-mips64.patch [3] The License changed from GPLv2 to GPLv3. [4] RISCV64/Linux is supporterd since version 3.25.0. [1]: https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=7214886886bce9029f325214156c02dcfff760d5 [2]: https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=54d6ad3348fb50f5b972fe9c05d0d8757bfe73ba [3]: https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=efaa17e53a750d5f0f4c138b507b1b104729ed67 [4]: https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=3392155359822c0d4e8bb371862e92425054d02a Link: https://github.com/openwrt/openwrt/pull/20537 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
69 lines
2.2 KiB
Diff
69 lines
2.2 KiB
Diff
Disable the valgrind helpers which use MIPS floating point operations
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when floating point support is deactivated in the toolchain.
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The fix from this commit is not sufficient any more:
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https://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=869fcf2f6739f17b4eff36ec68f8dca826c8afeb
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This fixes the following error message when compiling with a GCC 10 MIPS BE 32:
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---------------------------------------------------------
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../VEX/priv/guest_mips_helpers.c: In function 'mips_dirtyhelper_calculate_FCSR_fp32':
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../VEX/priv/guest_mips_helpers.c:640:10: error: the register '$f21' cannot be clobbered in 'asm' for the current target
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640 | ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)
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| ^
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---------------------------------------------------------
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--- a/VEX/priv/guest_mips_helpers.c
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+++ b/VEX/priv/guest_mips_helpers.c
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@@ -620,6 +620,7 @@ extern UInt mips_dirtyhelper_calculate_F
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flt_op inst )
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{
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UInt ret = 0;
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+#ifndef __mips_soft_float
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#if defined(__mips__)
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VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;
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UInt loFsVal, hiFsVal, loFtVal, hiFtVal;
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@@ -702,6 +703,7 @@ extern UInt mips_dirtyhelper_calculate_F
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break;
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}
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#endif
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+#endif
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return ret;
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}
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@@ -711,6 +713,7 @@ extern UInt mips_dirtyhelper_calculate_F
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flt_op inst )
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{
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UInt ret = 0;
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+#ifndef __mips_soft_float
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#if defined(__mips__) && ((__mips == 64) || \
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(defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))
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#if defined(VGA_mips32)
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@@ -863,6 +866,7 @@ extern UInt mips_dirtyhelper_calculate_F
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break;
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}
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#endif
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+#endif
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return ret;
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}
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--- a/coregrind/m_machine.c
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+++ b/coregrind/m_machine.c
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@@ -2167,6 +2167,7 @@ Bool VG_(machine_get_hwcaps)( void )
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we are using alternative way to determine FP mode */
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ULong result = 0;
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+#ifndef __mips_soft_float
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if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {
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__asm__ volatile (
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".set push\n\t"
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@@ -2184,6 +2185,9 @@ Bool VG_(machine_get_hwcaps)( void )
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fpmode = (result != 0x3FF0000000000000ull);
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}
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+#else
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+ fpmode = 0;
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+#endif
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}
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if (fpmode != 0)
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