mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-04 06:54:27 -05:00
cddd459140
Add patches for linux-5.4. The patches are from NXP LSDK-20.04 release which was tagged LSDK-20.04-V5.4. https://source.codeaurora.org/external/qoriq/qoriq-components/linux/ For boards LS1021A-IOT, and Traverse-LS1043 which are not involved in LSDK, port the dts patches from 4.14. The patches are sorted into the following categories: 301-arch-xxxx 302-dts-xxxx 303-core-xxxx 701-net-xxxx 801-audio-xxxx 802-can-xxxx 803-clock-xxxx 804-crypto-xxxx 805-display-xxxx 806-dma-xxxx 807-gpio-xxxx 808-i2c-xxxx 809-jailhouse-xxxx 810-keys-xxxx 811-kvm-xxxx 812-pcie-xxxx 813-pm-xxxx 814-qe-xxxx 815-sata-xxxx 816-sdhc-xxxx 817-spi-xxxx 818-thermal-xxxx 819-uart-xxxx 820-usb-xxxx 821-vfio-xxxx Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
99 lines
4.1 KiB
Diff
99 lines
4.1 KiB
Diff
From f48ec27500239c0400114327ecbbfec34bfc2deb Mon Sep 17 00:00:00 2001
|
|
From: Li Yang <leoli@freescale.com>
|
|
Date: Wed, 22 Feb 2012 15:52:50 +0000
|
|
Subject: [PATCH] fsl_pmc: update device bindings
|
|
|
|
Signed-off-by: Li Yang <leoyang.li@nxp.com>
|
|
Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
|
|
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
|
|
---
|
|
.../devicetree/bindings/powerpc/fsl/pmc.txt | 59 +++++++++++++---------
|
|
1 file changed, 34 insertions(+), 25 deletions(-)
|
|
|
|
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
|
|
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
|
|
@@ -9,15 +9,20 @@ Properties:
|
|
|
|
"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
|
|
compatible. "fsl,mpc8536-pmc" should also be listed for any chip
|
|
- whose PMC is compatible, and implies deep-sleep capability.
|
|
+ whose PMC is compatible, and implies deep-sleep capability and
|
|
+ wake on user defined packet(wakeup on ARP).
|
|
+
|
|
+ "fsl,p1022-pmc" should be listed for any chip whose PMC is
|
|
+ compatible, and implies lossless Ethernet capability during sleep.
|
|
|
|
"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
|
|
compatible; all statements below that apply to "fsl,mpc8548-pmc" also
|
|
apply to "fsl,mpc8641d-pmc".
|
|
|
|
Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
|
|
- bit assignments are indicated via the sleep specifier in each device's
|
|
- sleep property.
|
|
+ bit assignments are indicated via the clock nodes. Device which has a
|
|
+ controllable clock source should have a "fsl,pmc-handle" property pointing
|
|
+ to the clock node.
|
|
|
|
- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
|
|
is the PMC block, and the second resource is the Clock Configuration
|
|
@@ -33,31 +38,35 @@ Properties:
|
|
this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
|
|
a wakeup source from deep sleep.
|
|
|
|
-Sleep specifiers:
|
|
-
|
|
- fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
|
|
- that is set in the cell, the corresponding bit in SCCR will be saved
|
|
- and cleared on suspend, and restored on resume. This sleep controller
|
|
- supports disabling and resuming devices at any time.
|
|
-
|
|
- fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
|
|
- which will be ORed into PMCDR upon suspend, and cleared from PMCDR
|
|
- upon resume. The first two cells are as described for fsl,mpc8578-pmc.
|
|
- This sleep controller only supports disabling devices during system
|
|
- sleep, or permanently.
|
|
-
|
|
- fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
|
|
- first of which will be ORed into DEVDISR (and the second into
|
|
- DEVDISR2, if present -- this cell should be zero or absent if the
|
|
- hardware does not have DEVDISR2) upon a request for permanent device
|
|
- disabling. This sleep controller does not support configuring devices
|
|
- to disable during system sleep (unless supported by another compatible
|
|
- match), or dynamically.
|
|
+Clock nodes:
|
|
+The clock nodes are to describe the masks in PM controller registers for each
|
|
+soc clock.
|
|
+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
|
|
+ ORed into PMCDR before suspend if the device using this clock is the wake-up
|
|
+ source and need to be running during low power mode; clear the mask if
|
|
+ otherwise.
|
|
+
|
|
+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
|
|
+ bit specified by the mask in SCCR will be saved and cleared on suspend, and
|
|
+ restored on resume.
|
|
+
|
|
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
|
|
+ DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR
|
|
+ or DEVDISR2 when the clock should be permenently disabled.
|
|
|
|
Example:
|
|
|
|
- power@b00 {
|
|
- compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
|
|
- reg = <0xb00 0x100 0xa00 0x100>;
|
|
- interrupts = <80 8>;
|
|
+ power@e0070 {
|
|
+ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
|
|
+ reg = <0xe0070 0x20>;
|
|
+
|
|
+ etsec1_clk: soc-clk@24 {
|
|
+ fsl,pmcdr-mask = <0x00000080>;
|
|
+ };
|
|
+ etsec2_clk: soc-clk@25 {
|
|
+ fsl,pmcdr-mask = <0x00000040>;
|
|
+ };
|
|
+ etsec3_clk: soc-clk@26 {
|
|
+ fsl,pmcdr-mask = <0x00000020>;
|
|
+ };
|
|
};
|