mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-30 13:34:27 -04:00
153 lines
5.0 KiB
Diff
153 lines
5.0 KiB
Diff
From: Wu Zhangjin <wuzj@lemote.com>
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the gcc 4.4 support for MIPS mostly refer to this PATCH:
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http://www.nabble.com/-PATCH--MIPS:-Handle-removal-of-%27h%27-constraint-in-GCC-4.4-td22192768.html
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but have been tuned a little.
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because only gcc 4.4 have loongson-specific support, so, we need to
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choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and
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we also need to consider use -march=loongson2e and -march=loongson2f for
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loongson2e and loongson2f respectively. this is handled by adding two
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new kernel options: CPU_LOONGSON2E and CPU_LOONGSON2F(thanks for the
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solutin provided by ZhangLe).
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I have tested it on FuLoong(2f) in 32bit and 64bit with gcc-4.4 and
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gcc-4.3. so, basically, it works.
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Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
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---
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arch/mips/Makefile | 9 +++++-
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arch/mips/include/asm/compiler.h | 10 ++++++
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arch/mips/include/asm/delay.h | 58 +++++++++++++++++++++++++------------
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3 files changed, 57 insertions(+), 20 deletions(-)
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -119,7 +119,14 @@ cflags-$(CONFIG_CPU_R4300) += -march=r43
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cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
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cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
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cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
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-cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
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+
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+# only gcc >= 4.4 have the loongson-specific support
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+cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
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+cflags-$(CONFIG_CPU_LOONGSON2E) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
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+ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2e); fi ;)
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+cflags-$(CONFIG_CPU_LOONGSON2F) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
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+ echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2f); fi ;)
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+
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cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
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-Wa,-mips32 -Wa,--trap
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cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
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--- a/arch/mips/include/asm/compiler.h
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+++ b/arch/mips/include/asm/compiler.h
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@@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2004, 2007 Maciej W. Rozycki
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+ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@@ -16,4 +17,13 @@
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#define GCC_REG_ACCUM "accum"
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#endif
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+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
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+#define GCC_NO_H_CONSTRAINT
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+#ifdef CONFIG_64BIT
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+typedef unsigned int uintx_t __attribute__((mode(TI)));
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+#else
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+typedef u64 uintx_t;
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+#endif
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+#endif
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+
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#endif /* _ASM_COMPILER_H */
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--- a/arch/mips/include/asm/delay.h
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+++ b/arch/mips/include/asm/delay.h
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@@ -7,6 +7,7 @@
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* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2007 Maciej W. Rozycki
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+ * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
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*/
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#ifndef _ASM_DELAY_H
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#define _ASM_DELAY_H
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@@ -48,6 +49,43 @@ static inline void __delay(unsigned long
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: "0" (loops), "r" (1));
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}
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+/*
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+ * convert usecs to loops
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+ *
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+ * handle removal of 'h' constraint in GCC 4.4
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+ */
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+
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+#ifndef GCC_NO_H_CONSTRAINT /* gcc <= 4.3 */
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+static inline unsigned long __usecs_to_loops(unsigned long usecs,
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+ unsigned long lpj)
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+{
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+ unsigned long hi, lo;
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+
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+ if (sizeof(long) == 4)
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+ __asm__("multu\t%2, %3"
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+ : "=h" (usecs), "=l" (lo)
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+ : "r" (usecs), "r" (lpj)
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+ : GCC_REG_ACCUM);
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+ else if (sizeof(long) == 8 && !R4000_WAR)
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+ __asm__("dmultu\t%2, %3"
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+ : "=h" (usecs), "=l" (lo)
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+ : "r" (usecs), "r" (lpj)
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+ : GCC_REG_ACCUM);
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+ else if (sizeof(long) == 8 && R4000_WAR)
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+ __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
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+ : "=r" (usecs), "=h" (hi), "=l" (lo)
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+ : "r" (usecs), "r" (lpj)
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+ : GCC_REG_ACCUM);
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+
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+ return usecs;
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+}
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+#else /* GCC_NO_H_CONSTRAINT, gcc >= 4.4 */
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+static inline unsigned long __usecs_to_loops(unsigned long usecs,
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+ unsigned long lpj)
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+{
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+ return ((uintx_t)usecs * lpj) >> BITS_PER_LONG;
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+}
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+#endif
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/*
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* Division by multiplication: you don't have to worry about
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@@ -62,8 +100,6 @@ static inline void __delay(unsigned long
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static inline void __udelay(unsigned long usecs, unsigned long lpj)
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{
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- unsigned long hi, lo;
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-
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/*
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* The rates of 128 is rounded wrongly by the catchall case
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* for 64-bit. Excessive precission? Probably ...
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@@ -77,23 +113,7 @@ static inline void __udelay(unsigned lon
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0x80000000ULL) >> 32);
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#endif
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- if (sizeof(long) == 4)
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- __asm__("multu\t%2, %3"
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- : "=h" (usecs), "=l" (lo)
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- : "r" (usecs), "r" (lpj)
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- : GCC_REG_ACCUM);
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- else if (sizeof(long) == 8 && !R4000_WAR)
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- __asm__("dmultu\t%2, %3"
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- : "=h" (usecs), "=l" (lo)
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- : "r" (usecs), "r" (lpj)
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- : GCC_REG_ACCUM);
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- else if (sizeof(long) == 8 && R4000_WAR)
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- __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
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- : "=r" (usecs), "=h" (hi), "=l" (lo)
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- : "r" (usecs), "r" (lpj)
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- : GCC_REG_ACCUM);
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-
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- __delay(usecs);
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+ __delay(__usecs_to_loops(usecs, lpj));
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}
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#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
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