mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-10-31 05:54:26 -04:00
101 lines
3.0 KiB
Diff
101 lines
3.0 KiB
Diff
--- a/drivers/ide/pci/aec62xx.c
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+++ b/drivers/ide/pci/aec62xx.c
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@@ -3,6 +3,8 @@
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*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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*
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+ * With Broadcom 4780 patches
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+ *
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*/
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#include <linux/module.h>
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@@ -329,7 +331,11 @@ static int aec62xx_config_drive_xfer_rat
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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+#ifndef CONFIG_BCM947XX
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if ((id->capability & 1) && drive->autodma) {
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+#else
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+ if (1) {
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+#endif
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/* Consult the list of known "bad" drives */
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if (hwif->ide_dma_bad_drive(drive))
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goto fast_ata_pio;
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@@ -414,10 +420,60 @@ static unsigned int __init init_chipset_
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{
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int bus_speed = system_bus_clock();
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+#ifndef CONFIG_BCM947XX
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if (dev->resource[PCI_ROM_RESOURCE].start) {
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
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printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
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}
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+#else
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+ if (dev->resource[PCI_ROM_RESOURCE].start) {
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+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
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+ dev->resource[PCI_ROM_RESOURCE].
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+ start | PCI_ROM_ADDRESS_ENABLE);
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+ } else {
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+ pci_write_config_dword(dev, PCI_ROM_ADDRESS,
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+ dev->resource[PCI_ROM_RESOURCE].
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+ start);
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+ }
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+
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+ /* Set IDE controller parameters manually - FIXME: replace magic values */
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+ {
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+ byte setting;
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+
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+ pci_write_config_word(dev, PCI_COMMAND, 0x0007);
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+ //pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x5A);
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+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x13);
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+
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+ pci_write_config_byte(dev, 0x40, 0x31);
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+ pci_write_config_byte(dev, 0x41, 0x31);
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+ pci_write_config_byte(dev, 0x42, 0x31);
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+ pci_write_config_byte(dev, 0x43, 0x31);
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+ // Set IDE Command Speed
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+ pci_write_config_byte(dev, 0x48, 0x31);
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+
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+ // Disable WriteSubSysID & PIOROM
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+ pci_read_config_byte(dev, 0x49, &setting);
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+ setting &= 0x07;
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+ pci_write_config_byte(dev, 0x49, setting);
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+
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+ // Enable PCI burst & INTA & PCI memory read multiple, FIFO threshold=80
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+ pci_read_config_byte(dev, 0x4A, &setting);
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+ //setting = (setting & 0xFE) | 0xA8;
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+ setting = (setting & 0xFE) | 0xD8;
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+ setting = (setting & 0xF7);
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+ pci_write_config_byte(dev, 0x4A, setting);
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+
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+ //pci_write_config_byte(dev, 0x4B, 0x20);
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+ pci_write_config_byte(dev, 0x4B, 0x2C);
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+ //pci_write_config_byte(dev, 0x4B, 0x0C);
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+
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+ // Set PreRead count: 512 byte
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+ pci_write_config_byte(dev, 0x4C, 0);
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+ pci_write_config_word(dev, 0x4D, 0x0002);
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+ pci_write_config_byte(dev, 0x54, 0);
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+ pci_write_config_word(dev, 0x55, 0x0002);
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+ }
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+#endif
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#if defined(DISPLAY_AEC62XX_TIMINGS) && defined(CONFIG_PROC_FS)
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aec_devs[n_aec_devs++] = dev;
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@@ -500,6 +556,7 @@ static void __init init_setup_aec62xx (s
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static void __init init_setup_aec6x80 (struct pci_dev *dev, ide_pci_device_t *d)
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{
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+#ifndef CONFIG_BCM947XX /* Causes OOPS on BCM4780 */
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unsigned long bar4reg = pci_resource_start(dev, 4);
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if (inb(bar4reg+2) & 0x10) {
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@@ -512,6 +569,7 @@ static void __init init_setup_aec6x80 (s
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strcpy(d->name, "AEC6280R");
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}
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+#endif
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ide_setup_pci_device(dev, d);
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}
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