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git://git.openwrt.org/openwrt/openwrt.git
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0f7de49fa3
Old bootloader (same ones which have DT disabled) don't perform any PCIe initialization. The consequence is a freeze during PCIe bring-up on these old u-boot. Same kernel with a newer bootloaders works fine as they contain the corresponding PCIe init code. In this change, we'll add the missing init and make sure the kernel doesn't rely on some preexisting init to get PCIe to work. That includes the following changes: *GPIOs: set function & drive strength *Clocks: add init code for aux & ref clocks *PCIe driver: additional init of the hardware controller Tested 3.18 and 4.1 on an AP148 with bootloader branch 0.0.1 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46557
279 lines
8.6 KiB
Diff
279 lines
8.6 KiB
Diff
--- a/drivers/pci/host/pcie-qcom.c
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+++ b/drivers/pci/host/pcie-qcom.c
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@@ -29,8 +29,53 @@
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#include "pcie-designware.h"
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+/* DBI registers */
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+#define PCIE20_CAP 0x70
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+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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+
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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+
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+#define PCIE20_PLR_IATU_VIEWPORT 0x900
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+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
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+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL1 0x904
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+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
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+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL2 0x908
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+#define PCIE20_PLR_IATU_ENABLE BIT(31)
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+
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+#define PCIE20_PLR_IATU_LBAR 0x90C
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+#define PCIE20_PLR_IATU_UBAR 0x910
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+#define PCIE20_PLR_IATU_LAR 0x914
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+#define PCIE20_PLR_IATU_LTAR 0x918
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+#define PCIE20_PLR_IATU_UTAR 0x91c
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+
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+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
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+
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+/* PARF registers */
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+#define PCIE20_PARF_PCS_DEEMPH 0x34
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+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
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+
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+#define PCIE20_PARF_PCS_SWING 0x38
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+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
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+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
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+
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#define PCIE20_PARF_PHY_CTRL 0x40
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+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
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+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
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+
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#define PCIE20_PARF_PHY_REFCLK 0x4C
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+#define REF_SSP_EN BIT(16)
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+#define REF_USE_PAD BIT(12)
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+
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+#define PCIE20_PARF_CONFIG_BITS 0x50
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+#define PHY_RX0_EQ(x) (x << 24)
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+
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#define PCIE20_PARF_DBI_BASE_ADDR 0x168
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#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
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#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
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@@ -39,9 +84,6 @@
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#define PCIE20_ELBI_SYS_STTS 0x08
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#define XMLH_LINK_UP BIT(10)
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-#define PCIE20_CAP 0x70
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-#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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-
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#define PERST_DELAY_MIN_US 1000
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#define PERST_DELAY_MAX_US 1005
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@@ -56,14 +98,18 @@ struct qcom_pcie_resources_v0 {
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struct clk *iface_clk;
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struct clk *core_clk;
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struct clk *phy_clk;
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+ struct clk *aux_clk;
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+ struct clk *ref_clk;
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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struct reset_control *por_reset;
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struct reset_control *phy_reset;
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+ struct reset_control *ext_reset;
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struct regulator *vdda;
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struct regulator *vdda_phy;
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struct regulator *vdda_refclk;
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+ uint8_t phy_tx0_term_offset;
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};
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struct qcom_pcie_resources_v1 {
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@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_
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reset_control_assert(res->axi_reset);
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reset_control_assert(res->ahb_reset);
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reset_control_assert(res->por_reset);
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- reset_control_assert(res->pci_reset);
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+ reset_control_assert(res->phy_reset);
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+ reset_control_assert(res->ext_reset);
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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clk_disable_unprepare(res->phy_clk);
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+ clk_disable_unprepare(res->aux_clk);
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+ clk_disable_unprepare(res->ref_clk);
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regulator_disable(res->vdda);
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regulator_disable(res->vdda_phy);
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regulator_disable(res->vdda_refclk);
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@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0
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goto err_vdda_phy;
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}
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+ ret = reset_control_deassert(res->ext_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot assert ext reset\n");
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+ goto err_reset_ext;
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+ }
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+
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ret = clk_prepare_enable(res->iface_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable iface clock\n");
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@@ -219,6 +274,18 @@ static int qcom_pcie_enable_resources_v0
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goto err_clk_phy;
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}
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+ ret = clk_prepare_enable(res->aux_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable aux clock\n");
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+ goto err_clk_aux;
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+ }
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+
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+ ret = clk_prepare_enable(res->ref_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable ref clock\n");
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+ goto err_clk_ref;
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+ }
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+
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ret = reset_control_deassert(res->ahb_reset);
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if (ret) {
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dev_err(dev, "cannot deassert ahb reset\n");
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@@ -228,12 +295,18 @@ static int qcom_pcie_enable_resources_v0
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return 0;
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err_reset_ahb:
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+ clk_disable_unprepare(res->ref_clk);
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+err_clk_ref:
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+ clk_disable_unprepare(res->aux_clk);
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+err_clk_aux:
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clk_disable_unprepare(res->phy_clk);
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err_clk_phy:
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clk_disable_unprepare(res->core_clk);
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err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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err_iface:
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+ reset_control_assert(res->ext_reset);
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+err_reset_ext:
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regulator_disable(res->vdda_phy);
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err_vdda_phy:
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regulator_disable(res->vdda_refclk);
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@@ -329,6 +402,14 @@ static int qcom_pcie_get_resources_v0(st
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if (IS_ERR(res->phy_clk))
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return PTR_ERR(res->phy_clk);
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+ res->aux_clk = devm_clk_get(dev, "aux");
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+ if (IS_ERR(res->aux_clk))
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+ return PTR_ERR(res->aux_clk);
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+
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+ res->ref_clk = devm_clk_get(dev, "ref");
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+ if (IS_ERR(res->ref_clk))
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+ return PTR_ERR(res->ref_clk);
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+
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res->pci_reset = devm_reset_control_get(dev, "pci");
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if (IS_ERR(res->pci_reset))
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return PTR_ERR(res->pci_reset);
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@@ -349,6 +430,14 @@ static int qcom_pcie_get_resources_v0(st
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if (IS_ERR(res->phy_reset))
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return PTR_ERR(res->phy_reset);
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+ res->ext_reset = devm_reset_control_get(dev, "ext");
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+ if (IS_ERR(res->ext_reset))
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+ return PTR_ERR(res->ext_reset);
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+
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+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
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+ &res->phy_tx0_term_offset))
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+ res->phy_tx0_term_offset = 0;
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+
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return 0;
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}
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@@ -461,6 +550,57 @@ err_res:
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qcom_pcie_disable_resources_v1(pcie);
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}
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+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
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+{
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+ struct pcie_port *pp = &pcie->pp;
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+
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+ /*
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+ * program and enable address translation region 0 (device config
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+ * address space); region type config;
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+ * axi config address range to device config address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(0),
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+ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->cfg0_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->cfg0_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
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+ writel((pp->cfg0_mod_base + pp->cfg0_size - 1),
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+ pcie->dbi + PCIE20_PLR_IATU_LAR);
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+ writel(busdev, pcie->dbi + PCIE20_PLR_IATU_LTAR);
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+ writel(0, pcie->dbi + PCIE20_PLR_IATU_UTAR);
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+}
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+
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+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
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+{
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+ struct pcie_port *pp = &pcie->pp;
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+
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+ /*
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+ * program and enable address translation region 2 (device resource
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+ * address space); region type memory;
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+ * axi device bar address range to device bar address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(2),
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+ pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->mem_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->mem_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
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+ writel(pp->mem_mod_base + pp->mem_size - 1,
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+ pcie->dbi + PCIE20_PLR_IATU_LAR);
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+ writel(pp->mem_bus_addr, pcie->dbi + PCIE20_PLR_IATU_LTAR);
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+ writel(upper_32_bits(pp->mem_bus_addr),
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+ pcie->dbi + PCIE20_PLR_IATU_UTAR);
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+
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+ /* 1K PCIE buffer setting */
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+ writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
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+ writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
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+}
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+
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static void qcom_pcie_host_init_v0(struct pcie_port *pp)
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{
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struct qcom_pcie *pcie = to_qcom_pcie(pp);
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@@ -476,9 +616,26 @@ static void qcom_pcie_host_init_v0(struc
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writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
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- /* enable external reference clock */
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- writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
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+ /* Set Tx termination offset */
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+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
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+ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
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+ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
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+
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+ /* PARF programming */
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+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
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+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
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+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
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+ PCS_SWING_TX_SWING_LOW(0x78),
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+ pcie->parf + PCIE20_PARF_PCS_SWING);
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+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
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+
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+ /* Enable reference clock */
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+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
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+ REF_USE_PAD, REF_SSP_EN);
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+ /* De-assert PHY, PCIe, POR and AXI resets */
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ret = reset_control_deassert(res->phy_reset);
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if (ret) {
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dev_err(dev, "cannot deassert phy reset\n");
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@@ -517,6 +674,9 @@ static void qcom_pcie_host_init_v0(struc
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if (ret)
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goto err;
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+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
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+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
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+
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return;
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err:
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qcom_ep_reset_assert(pcie);
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