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acd8ad4de5
(build errors has been fixed - juhosg) Signed-off-by: Arnaud Lacombe <lacombar@gmail.com> SVN-Revision: 23977
396 lines
9.4 KiB
C
396 lines
9.4 KiB
C
/*
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* Atheros AR724x PCI host controller driver
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*
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* Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/resource.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/interrupt.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#include <asm/mach-ar71xx/pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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static void __iomem *ar724x_pci_localcfg_base;
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static void __iomem *ar724x_pci_devcfg_base;
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static void __iomem *ar724x_pci_ctrl_base;
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static int ar724x_pci_fixup_enable;
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static DEFINE_SPINLOCK(ar724x_pci_lock);
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static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
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{
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unsigned long flags;
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u32 data;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*value = data;
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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}
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static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
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{
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unsigned long flags;
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u32 data;
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int s;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((value & 0xFF) << s);
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break;
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case 2:
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s = ((where & 2) << 3);
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data &= ~(0xFFFF << s);
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data |= ((value & 0xFFFF) << s);
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break;
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case 4:
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data = value;
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break;
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}
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__raw_writel(data, base + (where & ~3));
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/* flush write */
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(void)__raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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}
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static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *value)
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{
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if (bus->number != 0 || devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
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DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, *value);
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/*
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* WAR for BAR issue - We are unable to access the PCI device space
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* if we set the BAR with proper base address
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*/
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if ((where == 0x10) && (size == 4)) {
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u32 val;
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val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff;
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ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val);
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 value)
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{
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if (bus->number != 0 || devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
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where, size, value);
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ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
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return PCIBIOS_SUCCESSFUL;
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}
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static void ar724x_pci_fixup(struct pci_dev *dev)
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{
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u16 cmd;
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if (!ar724x_pci_fixup_enable)
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return;
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if (dev->bus->number != 0 || dev->devfn != 0)
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return;
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/* setup COMMAND register */
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
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PCI_COMMAND_FAST_BACK;
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
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int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
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uint8_t pin)
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{
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int irq = -1;
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int i;
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for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
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struct ar71xx_pci_irq *entry;
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entry = &ar71xx_pci_irq_map[i];
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if (entry->slot == slot && entry->pin == pin) {
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irq = entry->irq;
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break;
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}
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}
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if (irq < 0)
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printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
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pin, pci_name((struct pci_dev *)dev));
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else
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printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
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irq, pin, pci_name((struct pci_dev *)dev));
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return irq;
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}
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static struct pci_ops ar724x_pci_ops = {
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.read = ar724x_pci_read_config,
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.write = ar724x_pci_write_config,
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};
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static struct resource ar724x_pci_io_resource = {
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.name = "PCI IO space",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_IO,
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};
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static struct resource ar724x_pci_mem_resource = {
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.name = "PCI memory space",
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.start = AR71XX_PCI_MEM_BASE,
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.end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller ar724x_pci_controller = {
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.pci_ops = &ar724x_pci_ops,
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.mem_resource = &ar724x_pci_mem_resource,
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.io_resource = &ar724x_pci_io_resource,
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};
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static void __init ar724x_pci_reset(void)
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{
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ar71xx_device_stop(AR724X_RESET_PCIE);
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ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
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ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
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udelay(100);
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ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
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udelay(100);
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ar71xx_device_start(AR724X_RESET_PCIE_PHY);
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ar71xx_device_start(AR724X_RESET_PCIE);
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}
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static int __init ar724x_pci_setup(void)
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 t;
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/* setup COMMAND register */
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
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ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
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ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
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ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
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t = __raw_readl(base + AR724X_PCI_REG_RESET);
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if (t != 0x7) {
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udelay(100000);
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__raw_writel(0, base + AR724X_PCI_REG_RESET);
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udelay(100);
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__raw_writel(4, base + AR724X_PCI_REG_RESET);
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udelay(100000);
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}
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if (ar71xx_soc == AR71XX_SOC_AR7240)
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t = AR724X_PCI_APP_LTSSM_ENABLE;
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else
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t = 0x1ffc1;
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__raw_writel(t, base + AR724X_PCI_REG_APP);
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/* flush write */
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(void) __raw_readl(base + AR724X_PCI_REG_APP);
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udelay(1000);
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t = __raw_readl(base + AR724X_PCI_REG_RESET);
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if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) {
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printk(KERN_WARNING "PCI: no PCIe module found\n");
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return -ENODEV;
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}
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if (ar71xx_soc == AR71XX_SOC_AR7241 ||
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ar71xx_soc == AR71XX_SOC_AR7242) {
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t = __raw_readl(base + AR724X_PCI_REG_APP);
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t |= BIT(16);
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__raw_writel(t, base + AR724X_PCI_REG_APP);
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}
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return 0;
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}
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static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 pending;
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pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
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__raw_readl(base + AR724X_PCI_REG_INT_MASK);
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if (pending & AR724X_PCI_INT_DEV0)
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generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
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else
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spurious_interrupt();
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}
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static void ar724x_pci_irq_unmask(unsigned int irq)
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 t;
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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(void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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}
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}
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static void ar724x_pci_irq_mask(unsigned int irq)
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 t;
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switch (irq) {
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case AR71XX_PCI_IRQ_DEV0:
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irq -= AR71XX_PCI_IRQ_BASE;
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t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(t & ~AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_MASK);
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/* flush write */
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(void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
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t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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__raw_writel(t | AR724X_PCI_INT_DEV0,
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base + AR724X_PCI_REG_INT_STATUS);
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/* flush write */
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(void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
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}
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}
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static struct irq_chip ar724x_pci_irq_chip = {
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.name = "AR724X PCI ",
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.mask = ar724x_pci_irq_mask,
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.unmask = ar724x_pci_irq_unmask,
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.mask_ack = ar724x_pci_irq_mask,
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};
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static void __init ar724x_pci_irq_init(void)
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{
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void __iomem *base = ar724x_pci_ctrl_base;
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u32 t;
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int i;
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t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
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if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
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AR724X_RESET_PCIE_PHY_SERIAL)) {
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return;
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}
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__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
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__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
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for (i = AR71XX_PCI_IRQ_BASE;
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i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
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handle_level_irq);
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}
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set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
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}
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int __init ar724x_pcibios_init(void)
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{
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int ret = -ENOMEM;
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ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
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AR724X_PCI_CRP_SIZE);
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if (ar724x_pci_localcfg_base == NULL)
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goto err;
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ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
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AR724X_PCI_CFG_SIZE);
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if (ar724x_pci_devcfg_base == NULL)
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goto err_unmap_localcfg;
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ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
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AR724X_PCI_CTRL_SIZE);
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if (ar724x_pci_ctrl_base == NULL)
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goto err_unmap_devcfg;
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ar724x_pci_reset();
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ret = ar724x_pci_setup();
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if (ret)
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goto err_unmap_ctrl;
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ar724x_pci_fixup_enable = 1;
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ar724x_pci_irq_init();
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register_pci_controller(&ar724x_pci_controller);
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return 0;
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err_unmap_ctrl:
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iounmap(ar724x_pci_ctrl_base);
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err_unmap_devcfg:
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iounmap(ar724x_pci_devcfg_base);
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err_unmap_localcfg:
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iounmap(ar724x_pci_localcfg_base);
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err:
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return ret;
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}
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