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				git://git.openwrt.org/openwrt/openwrt.git
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			157 lines
		
	
	
		
			4.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			157 lines
		
	
	
		
			4.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| --- a/src/mei/ifxmips_atm_core.c
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| +++ b/src/mei/ifxmips_atm_core.c
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| @@ -58,9 +58,8 @@
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|  /*
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|   *  Chip Specific Head File
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|   */
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| -#include <asm/ifx/ifx_types.h>
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| -#include <asm/ifx/ifx_regs.h>
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| -#include <asm/ifx/common_routines.h>
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| +#include <ifxmips.h>
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| +#include <ifxmips_cgu.h>
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|  #include "ifxmips_atm_core.h"
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|  
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|  
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| @@ -1146,7 +1145,7 @@ static INLINE void mailbox_signal(unsign
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|  
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|  static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
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|  {
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| -    unsigned int qsb_clk = ifx_get_fpi_hz();
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| +    unsigned int qsb_clk = ifxmips_get_fpi_hz();
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|      unsigned int qsb_qid = queue + FIRST_QSB_QID;
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|      union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
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|      union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
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| @@ -1318,7 +1317,7 @@ static void set_qsb(struct atm_vcc *vcc,
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|  
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|  static void qsb_global_set(void)
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|  {
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| -    unsigned int qsb_clk = ifx_get_fpi_hz();
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| +    unsigned int qsb_clk = ifxmips_get_fpi_hz();
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|      int i;
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|      unsigned int tmp1, tmp2, tmp3;
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|  
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| @@ -2505,3 +2504,4 @@ static void __exit ifx_atm_exit(void)
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|  
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|  module_init(ifx_atm_init);
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|  module_exit(ifx_atm_exit);
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| +MODULE_LICENSE("Dual BSD/GPL");
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| --- a/src/mei/ifxmips_atm_ppe_common.h
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| +++ b/src/mei/ifxmips_atm_ppe_common.h
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| @@ -1,9 +1,10 @@
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|  #ifndef IFXMIPS_ATM_PPE_COMMON_H
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|  #define IFXMIPS_ATM_PPE_COMMON_H
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|  
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| -
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| -
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| -#if defined(CONFIG_DANUBE)
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| +#if defined(CONFIG_IFXMIPS)
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| +  #include "ifxmips_atm_ppe_danube.h"
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| +  #define CONFIG_DANUBE
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| +#elif defined(CONFIG_DANUBE) 
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|    #include "ifxmips_atm_ppe_danube.h"
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|  #elif defined(CONFIG_AMAZON_SE)
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|    #include "ifxmips_atm_ppe_amazon_se.h"
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| @@ -16,7 +17,6 @@
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|  #endif
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|  
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|  
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| -
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|  /*
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|   *  Code/Data Memory (CDM) Interface Configuration Register
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|   */
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| --- a/src/mei/ifxmips_atm_core.h
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| +++ b/src/mei/ifxmips_atm_core.h
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| @@ -25,8 +25,8 @@
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|  #define IFXMIPS_ATM_CORE_H
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|  
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|  
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| -
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| -#include <asm/ifx/ifx_atm.h>
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| +#include "ifxmips_compat.h"
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| +#include "ifx_atm.h"
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|  #include "ifxmips_atm_ppe_common.h"
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|  #include "ifxmips_atm_fw_regs_common.h"
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|  
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| --- /dev/null
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| +++ b/src/mei/ifxmips_compat.h
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| @@ -0,0 +1,43 @@
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| +#ifndef _IFXMIPS_COMPAT_H__
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| +#define _IFXMIPS_COMPAT_H__
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| +
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| +#define	IFX_SUCCESS	0
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| +#define IFX_ERROR	(-1)
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| +
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| +#define ATM_VBR_NRT     ATM_VBR
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| +#define ATM_VBR_RT      6
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| +#define ATM_UBR_PLUS    7
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| +#define ATM_GFR         8
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| +
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| +#define NUM_ENTITY(x)	(sizeof(x) / sizeof(*(x)))
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| +
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| +#define SET_BITS(x, msb, lsb, value)	\
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| +    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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| +
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| +
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| +#define IFX_PMU_ENABLE    1
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| +#define IFX_PMU_DISABLE   0
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| +
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| +#define IFX_PMU_MODULE_DSL_DFE    (1 << 9)
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| +#define IFX_PMU_MODULE_AHBS		  (1 << 13)
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| +#define IFX_PMU_MODULE_PPE_QSB    (1 << 18)
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| +#define IFX_PMU_MODULE_PPE_SLL01  (1 << 19)
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| +#define IFX_PMU_MODULE_PPE_TC     (1 << 21)
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| +#define IFX_PMU_MODULE_PPE_EMA    (1 << 22)
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| +#define IFX_PMU_MODULE_PPE_TOP    (1 << 29)
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| +
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| +#define ifx_pmu_set(a,b)	{if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);}
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| +
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| +#define PPE_TOP_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x))
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| +#define PPE_SLL01_PMU_SETUP(__x)  ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x))
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| +#define PPE_TC_PMU_SETUP(__x)     ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x))
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| +#define PPE_EMA_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x))
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| +#define PPE_QSB_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x))
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| +#define PPE_TPE_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x))
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| +#define DSL_DFE_PMU_SETUP(__x)    ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x))
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| +
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| +#define IFX_REG_W32(_v, _r)               __raw_writel((_v), (_r))
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| +
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| +#define CONFIG_IFXMIPS_DSL_CPE_MEI	y
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| +
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| +#endif
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| --- a/src/mei/ifxmips_atm_ppe_danube.h
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| +++ b/src/mei/ifxmips_atm_ppe_danube.h
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| @@ -1,7 +1,7 @@
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|  #ifndef IFXMIPS_ATM_PPE_DANUBE_H
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|  #define IFXMIPS_ATM_PPE_DANUBE_H
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|  
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| -
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| +#include <ifxmips_irq.h>
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|  
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|  /*
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|   *  FPI Configuration Bus Register and Memory Address Mapping
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| @@ -93,7 +93,7 @@
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|  /*
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|   *  Mailbox IGU1 Interrupt
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|   */
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| -#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24
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| +#define PPE_MAILBOX_IGU1_INT            IFXMIPS_PPE_MBOX_INT
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|  
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|  
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|  
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| --- a/src/mei/ifxmips_atm_danube.c
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| +++ b/src/mei/ifxmips_atm_danube.c
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| @@ -45,10 +45,9 @@
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|  /*
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|   *  Chip Specific Head File
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|   */
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| -#include <asm/ifx/ifx_types.h>
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| -#include <asm/ifx/ifx_regs.h>
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| -#include <asm/ifx/common_routines.h>
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| -#include <asm/ifx/ifx_pmu.h>
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| +#include <ifxmips.h>
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| +#include <ifxmips_pmu.h>
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| +#include "ifxmips_compat.h"
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|  #include "ifxmips_atm_core.h"
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|  #include "ifxmips_atm_fw_danube.h"
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|  
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