mirror of
				git://git.openwrt.org/openwrt/openwrt.git
				synced 2025-10-30 21:44:27 -04:00 
			
		
		
		
	Hardware specification:
  SoC: MediaTek MT7986A 4x A53
  Flash: ESMT F50L1G41LB 128MB
  RAM: W632GU6NB DDR3 256MB
  Ethernet: 1x 2.5G + 4x 1G
  WiFi1: MT7975N 2.4GHz 4T4R
  WiFi2: MT7975PN 5GHz 4T4R
  Button: Reset, WPS
  Power: DC 12V 2A
Flash instructions:
  1. Connect to the router using ssh or telnet,
     username: useradmin, password is the web
     login password of the router.
  2. Use scp to upload bl31-uboot.fip and flash:
     "mtd write xxx-preloader.bin spi0.0"
     "mtd write xxx-bl31-uboot.fip FIP"
     "mtd erase ubi"
  3. Connect to the router via the Lan port,
     set a static ip of your PC.
     (ip 192.168.1.254, gateway 192.168.1.1)
  4. Download initramfs image, reboot router,
     waiting for tftp recovery to complete.
  5. After openwrt boots up, perform sysupgrade.
Note:
  1. Back up all mtd partitions before flashing.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
		
	
			
		
			
				
	
	
		
			285 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			285 lines
		
	
	
		
			4.7 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 | |
| 
 | |
| /dts-v1/;
 | |
| #include <dt-bindings/gpio/gpio.h>
 | |
| #include <dt-bindings/input/input.h>
 | |
| #include <dt-bindings/leds/common.h>
 | |
| 
 | |
| #include "mt7986a.dtsi"
 | |
| 
 | |
| / {
 | |
| 	model = "Netcore N60";
 | |
| 	compatible = "netcore,n60", "mediatek,mt7986a";
 | |
| 
 | |
| 	aliases {
 | |
| 		serial0 = &uart0;
 | |
| 		label-mac-device = &gmac0;
 | |
| 		led-boot = &led_status_red;
 | |
| 		led-failsafe = &led_status_red;
 | |
| 		led-running = &led_status_blue;
 | |
| 		led-upgrade = &led_status_blue;
 | |
| 	};
 | |
| 
 | |
| 	chosen {
 | |
| 		stdout-path = "serial0:115200n8";
 | |
| 	};
 | |
| 
 | |
| 	memory {
 | |
| 		reg = <0 0x40000000 0 0x10000000>;
 | |
| 	};
 | |
| 
 | |
| 	keys {
 | |
| 		compatible = "gpio-keys";
 | |
| 
 | |
| 		reset {
 | |
| 			label = "reset";
 | |
| 			linux,code = <KEY_RESTART>;
 | |
| 			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
 | |
| 		};
 | |
| 
 | |
| 		mesh {
 | |
| 			label = "mesh";
 | |
| 			linux,code = <KEY_WPS_BUTTON>;
 | |
| 			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	leds {
 | |
| 		compatible = "gpio-leds";
 | |
| 
 | |
| 		led_status_red: status-red {
 | |
| 			color = <LED_COLOR_ID_RED>;
 | |
| 			function = LED_FUNCTION_STATUS;
 | |
| 			gpios = <&pio 29 GPIO_ACTIVE_LOW>;
 | |
| 		};
 | |
| 
 | |
| 		led_status_blue: status-blue {
 | |
| 			color = <LED_COLOR_ID_BLUE>;
 | |
| 			function = LED_FUNCTION_STATUS;
 | |
| 			gpios = <&pio 32 GPIO_ACTIVE_LOW>;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &crypto {
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| ð {
 | |
| 	status = "okay";
 | |
| 
 | |
| 	gmac0: mac@0 {
 | |
| 		compatible = "mediatek,eth-mac";
 | |
| 		reg = <0>;
 | |
| 		phy-mode = "2500base-x";
 | |
| 
 | |
| 		nvmem-cells = <&macaddr_lan>;
 | |
| 		nvmem-cell-names = "mac-address";
 | |
| 
 | |
| 		fixed-link {
 | |
| 			speed = <2500>;
 | |
| 			full-duplex;
 | |
| 			pause;
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	gmac1: mac@1 {
 | |
| 		compatible = "mediatek,eth-mac";
 | |
| 		reg = <1>;
 | |
| 		phy-handle = <&phy6>;
 | |
| 		phy-mode = "2500base-x";
 | |
| 
 | |
| 		nvmem-cells = <&macaddr_wan>;
 | |
| 		nvmem-cell-names = "mac-address";
 | |
| 	};
 | |
| 
 | |
| 	mdio: mdio-bus {
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &mdio {
 | |
| 	reset-delay-us = <600>;
 | |
| 	reset-post-delay-us = <20000>;
 | |
| 	reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 | |
| 
 | |
| 	phy6: phy@6 {
 | |
| 		compatible = "ethernet-phy-ieee802.3-c45";
 | |
| 		reg = <6>;
 | |
| 		mxl,led-config = <0x0 0x0 0x0 0x3f0>;
 | |
| 	};
 | |
| 
 | |
| 	switch: switch@1f {
 | |
| 		compatible = "mediatek,mt7531";
 | |
| 		reg = <31>;
 | |
| 		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 | |
| 		interrupt-controller;
 | |
| 		#interrupt-cells = <1>;
 | |
| 		interrupt-parent = <&pio>;
 | |
| 		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &switch {
 | |
| 	ports {
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 
 | |
| 		port@0 {
 | |
| 			reg = <0>;
 | |
| 			label = "lan1";
 | |
| 		};
 | |
| 
 | |
| 		port@1 {
 | |
| 			reg = <1>;
 | |
| 			label = "lan2";
 | |
| 		};
 | |
| 
 | |
| 		port@3 {
 | |
| 			reg = <3>;
 | |
| 			label = "lan3";
 | |
| 		};
 | |
| 
 | |
| 		port@4 {
 | |
| 			reg = <4>;
 | |
| 			label = "lan4";
 | |
| 		};
 | |
| 
 | |
| 		port@6 {
 | |
| 			reg = <6>;
 | |
| 			ethernet = <&gmac0>;
 | |
| 			phy-mode = "2500base-x";
 | |
| 
 | |
| 			fixed-link {
 | |
| 				speed = <2500>;
 | |
| 				full-duplex;
 | |
| 				pause;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &spi0 {
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&spi_flash_pins>;
 | |
| 	status = "okay";
 | |
| 
 | |
| 	flash@0 {
 | |
| 		compatible = "spi-nand";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <1>;
 | |
| 		reg = <0>;
 | |
| 
 | |
| 		spi-max-frequency = <20000000>;
 | |
| 		spi-tx-bus-width = <4>;
 | |
| 		spi-rx-bus-width = <4>;
 | |
| 
 | |
| 		partitions {
 | |
| 			compatible = "fixed-partitions";
 | |
| 			#address-cells = <1>;
 | |
| 			#size-cells = <1>;
 | |
| 
 | |
| 			partition@0 {
 | |
| 				label = "BL2";
 | |
| 				reg = <0x0000000 0x0100000>;
 | |
| 				read-only;
 | |
| 			};
 | |
| 
 | |
| 			partition@100000 {
 | |
| 				label = "u-boot-env";
 | |
| 				reg = <0x0100000 0x0080000>;
 | |
| 			};
 | |
| 
 | |
| 			factory: partition@180000 {
 | |
| 				label = "Factory";
 | |
| 				reg = <0x0180000 0x0200000>;
 | |
| 				read-only;
 | |
| 			};
 | |
| 
 | |
| 			partition@380000 {
 | |
| 				label = "FIP";
 | |
| 				reg = <0x0380000 0x0200000>;
 | |
| 				read-only;
 | |
| 			};
 | |
| 
 | |
| 			partition@580000 {
 | |
| 				label = "ubi";
 | |
| 				reg = <0x0580000 0x7280000>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &pio {
 | |
| 	spi_flash_pins: spi-flash-pins-33-to-38 {
 | |
| 		mux {
 | |
| 			function = "spi";
 | |
| 			groups = "spi0", "spi0_wp_hold";
 | |
| 		};
 | |
| 		conf-pu {
 | |
| 			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 | |
| 			drive-strength = <8>;
 | |
| 			mediatek,pull-up-adv = <0>; /* bias-disable */
 | |
| 		};
 | |
| 		conf-pd {
 | |
| 			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 | |
| 			drive-strength = <8>;
 | |
| 			mediatek,pull-down-adv = <0>; /* bias-disable */
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	wf_2g_5g_pins: wf_2g_5g-pins {
 | |
| 		mux {
 | |
| 			function = "wifi";
 | |
| 			groups = "wf_2g", "wf_5g";
 | |
| 		};
 | |
| 		conf {
 | |
| 			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 | |
| 			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 | |
| 			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 | |
| 			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 | |
| 			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 | |
| 			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 | |
| 			       "WF1_TOP_CLK", "WF1_TOP_DATA";
 | |
| 			drive-strength = <4>;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &trng {
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &uart0 {
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &watchdog {
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &wifi {
 | |
| 	status = "okay";
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&wf_2g_5g_pins>;
 | |
| 
 | |
| 	mediatek,mtd-eeprom = <&factory 0x0>;
 | |
| };
 | |
| 
 | |
| &factory {
 | |
| 	nvmem-layout {
 | |
| 		compatible = "fixed-layout";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <1>;
 | |
| 
 | |
| 		macaddr_lan: macaddr@1fef20 {
 | |
| 			reg = <0x1fef20 0x6>;
 | |
| 		};
 | |
| 
 | |
| 		macaddr_wan: macaddr@1fef26 {
 | |
| 			reg = <0x1fef26 0x6>;
 | |
| 		};
 | |
| 	};
 | |
| };
 |