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			7.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			235 lines
		
	
	
		
			7.4 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From: Lorenzo Bianconi <lorenzo@kernel.org>
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| Date: Mon, 18 Sep 2023 12:29:06 +0200
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| Subject: [PATCH] net: ethernet: mtk_wed: do not configure rx offload if not
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|  supported
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| 
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| Check if rx offload is supported running mtk_wed_get_rx_capa routine
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| before configuring it. This is a preliminary patch to introduce Wireless
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| Ethernet Dispatcher (WED) support for MT7988 SoC.
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| 
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| Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
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| Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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| Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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| Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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| ---
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| 
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| --- a/drivers/net/ethernet/mediatek/mtk_wed.c
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| +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
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| @@ -605,7 +605,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
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|  	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
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|  	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
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|  
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| -	if (mtk_wed_is_v1(dev->hw))
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| +	if (!mtk_wed_get_rx_capa(dev))
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|  		return;
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|  
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|  	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
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| @@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
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|  {
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|  	if (mtk_wed_is_v1(dev->hw)) {
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|  		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
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| -	} else {
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| -		mtk_wed_bus_init(dev);
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| -
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| -		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
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| -		wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
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| -		wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
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| -		wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
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| -		wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
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| -		wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
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| +		return;
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|  	}
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| +
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| +	mtk_wed_bus_init(dev);
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| +
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| +	wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
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| +	wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
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| +	wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
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| +	wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
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| +
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| +	if (!mtk_wed_get_rx_capa(dev))
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| +		return;
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| +
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| +	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
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| +	wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
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|  }
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|  
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|  static void
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| @@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
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|  			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
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|  	} else {
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|  		wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
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| -		/* rx hw init */
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| -		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
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| -			MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
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| -			MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
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| -		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
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| -
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| -		mtk_wed_rx_buffer_hw_init(dev);
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| -		mtk_wed_rro_hw_init(dev);
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| -		mtk_wed_route_qm_hw_init(dev);
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| +		if (mtk_wed_get_rx_capa(dev)) {
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| +			/* rx hw init */
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| +			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
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| +				MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
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| +				MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
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| +			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
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| +
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| +			mtk_wed_rx_buffer_hw_init(dev);
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| +			mtk_wed_rro_hw_init(dev);
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| +			mtk_wed_route_qm_hw_init(dev);
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| +		}
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|  	}
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|  
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|  	wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
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| @@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
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|  
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|  		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
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|  	} else {
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| -		wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
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| -					GENMASK(1, 0));
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|  		/* initail tx interrupt trigger */
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|  		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
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|  			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
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| @@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
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|  			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
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|  				   dev->wlan.txfree_tbit));
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|  
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| -		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
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| -			MTK_WED_WPDMA_INT_CTRL_RX0_EN |
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| -			MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
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| -			MTK_WED_WPDMA_INT_CTRL_RX1_EN |
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| -			MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
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| -			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
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| -				   dev->wlan.rx_tbit[0]) |
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| -			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
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| -				   dev->wlan.rx_tbit[1]));
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| +		if (mtk_wed_get_rx_capa(dev)) {
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| +			wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
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| +				MTK_WED_WPDMA_INT_CTRL_RX0_EN |
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| +				MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
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| +				MTK_WED_WPDMA_INT_CTRL_RX1_EN |
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| +				MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
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| +				FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
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| +					   dev->wlan.rx_tbit[0]) |
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| +				FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
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| +					   dev->wlan.rx_tbit[1]));
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| +
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| +			wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
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| +						GENMASK(1, 0));
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| +		}
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|  
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|  		wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
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|  		wed_set(dev, MTK_WED_WDMA_INT_CTRL,
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| @@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
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|  static void
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|  mtk_wed_dma_enable(struct mtk_wed_device *dev)
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|  {
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| +	int i;
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| +
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|  	wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
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|  
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|  	wed_set(dev, MTK_WED_GLO_CFG,
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| @@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
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|  	if (mtk_wed_is_v1(dev->hw)) {
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|  		wdma_set(dev, MTK_WDMA_GLO_CFG,
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|  			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
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| -	} else {
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| -		int i;
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| +		return;
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| +	}
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|  
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| -		wed_set(dev, MTK_WED_WPDMA_CTRL,
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| -			MTK_WED_WPDMA_CTRL_SDL1_FIXED);
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| +	wed_set(dev, MTK_WED_WPDMA_CTRL,
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| +		MTK_WED_WPDMA_CTRL_SDL1_FIXED);
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| +	wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
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| +		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
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| +		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
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| +	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
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| +		MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
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| +		MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
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|  
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| -		wed_set(dev, MTK_WED_WDMA_GLO_CFG,
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| -			MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
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| -			MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
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| +	if (!mtk_wed_get_rx_capa(dev))
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| +		return;
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|  
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| -		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
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| -			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
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| -			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
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| -
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| -		wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
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| -			MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
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| -			MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
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| +	wed_set(dev, MTK_WED_WDMA_GLO_CFG,
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| +		MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
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| +		MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
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|  
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| -		wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
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| -			MTK_WED_WPDMA_RX_D_RX_DRV_EN |
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| -			FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
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| -			FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
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| -				   0x2));
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| +	wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
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| +		MTK_WED_WPDMA_RX_D_RX_DRV_EN |
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| +		FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
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| +		FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
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| +			   0x2));
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|  
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| -		for (i = 0; i < MTK_WED_RX_QUEUES; i++)
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| -			mtk_wed_check_wfdma_rx_fill(dev, i);
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| -	}
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| +	for (i = 0; i < MTK_WED_RX_QUEUES; i++)
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| +		mtk_wed_check_wfdma_rx_fill(dev, i);
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|  }
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|  
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|  static void
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| @@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
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|  
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|  		val |= BIT(0) | (BIT(1) * !!dev->hw->index);
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|  		regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
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| -	} else {
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| +	} else if (mtk_wed_get_rx_capa(dev)) {
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|  		/* driver set mid ready and only once */
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|  		wed_w32(dev, MTK_WED_EXT_INT_MASK1,
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|  			MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
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| @@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
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|  
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|  		if (mtk_wed_rro_cfg(dev))
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|  			return;
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| -
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|  	}
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|  
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|  	mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
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| @@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
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|  	}
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|  
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|  	mtk_wed_hw_init_early(dev);
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| -	if (mtk_wed_is_v1(hw)) {
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| +	if (mtk_wed_is_v1(hw))
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|  		regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
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|  				   BIT(hw->index), 0);
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| -	} else {
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| +	else
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|  		dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
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| +
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| +	if (mtk_wed_get_rx_capa(dev))
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|  		ret = mtk_wed_wo_init(hw);
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| -	}
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|  out:
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|  	if (ret) {
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|  		dev_err(dev->hw->dev, "failed to attach wed device\n");
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| --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
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| +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
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| @@ -207,7 +207,7 @@ int mtk_wed_mcu_msg_update(struct mtk_we
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|  {
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|  	struct mtk_wed_wo *wo = dev->hw->wed_wo;
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|  
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| -	if (mtk_wed_is_v1(dev->hw))
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| +	if (!mtk_wed_get_rx_capa(dev))
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|  		return 0;
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|  
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|  	if (WARN_ON(!wo))
 |