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f0cdbfd7cc
Replace ipq40xx MDIO patch with upstream version now that the driver part got merged upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
206 lines
6.4 KiB
Diff
206 lines
6.4 KiB
Diff
From bdce82e960d1205d118662f575cec39379984e34 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 31 Jan 2024 03:26:04 +0100
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Subject: [PATCH] net: mdio: ipq4019: add support for clock-frequency property
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The IPQ4019 MDIO internally divide the clock feed by AHB based on the
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MDIO_MODE reg. On reset or power up, the default value for the
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divider is 0xff that reflect the divider set to /256.
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This makes the MDC run at a very low rate, that is, considering AHB is
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always fixed to 100Mhz, a value of 390KHz.
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This hasn't have been a problem as MDIO wasn't used for time sensitive
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operation, it is now that on IPQ807x is usually mounted with PHY that
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requires MDIO to load their firmware (example Aquantia PHY).
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To handle this problem and permit to set the correct designed MDC
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frequency for the SoC add support for the standard "clock-frequency"
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property for the MDIO node.
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The divider supports value from /1 to /256 and the common value are to
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set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
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12.5Mhz.
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To scan if the requested rate is supported by the divider, loop with
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each supported divider and stop when the requested rate match the final
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rate with the current divider. An error is returned if the rate doesn't
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match any value.
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On MDIO reset, the divider is restored to the requested value to prevent
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any kind of downclocking caused by the divider reverting to a default
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value.
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To follow 802.3 spec of 2.5MHz of default value, if divider is set at
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/256 and "clock-frequency" is not set in DT, assume nobody set the
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divider and try to find the closest MDC rate to 2.5MHz. (in the case of
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AHB set to 100MHz, it's 1.5625MHz)
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While at is also document other bits of the MDIO_MODE reg to have a
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clear idea of what is actually applied there.
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Documentation of some BITs is skipped as they are marked as reserved and
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their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
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1 file changed, 103 insertions(+), 6 deletions(-)
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--- a/drivers/net/mdio/mdio-ipq4019.c
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+++ b/drivers/net/mdio/mdio-ipq4019.c
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@@ -14,6 +14,20 @@
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#include <linux/clk.h>
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#define MDIO_MODE_REG 0x40
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+#define MDIO_MODE_MDC_MODE BIT(12)
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+/* 0 = Clause 22, 1 = Clause 45 */
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+#define MDIO_MODE_C45 BIT(8)
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+#define MDIO_MODE_DIV_MASK GENMASK(7, 0)
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+#define MDIO_MODE_DIV(x) FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
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+#define MDIO_MODE_DIV_1 0x0
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+#define MDIO_MODE_DIV_2 0x1
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+#define MDIO_MODE_DIV_4 0x3
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+#define MDIO_MODE_DIV_8 0x7
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+#define MDIO_MODE_DIV_16 0xf
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+#define MDIO_MODE_DIV_32 0x1f
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+#define MDIO_MODE_DIV_64 0x3f
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+#define MDIO_MODE_DIV_128 0x7f
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+#define MDIO_MODE_DIV_256 0xff
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#define MDIO_ADDR_REG 0x44
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#define MDIO_DATA_WRITE_REG 0x48
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#define MDIO_DATA_READ_REG 0x4c
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@@ -26,9 +40,6 @@
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#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1
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#define MDIO_CMD_ACCESS_CODE_C45_READ 2
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-/* 0 = Clause 22, 1 = Clause 45 */
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-#define MDIO_MODE_C45 BIT(8)
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-
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#define IPQ4019_MDIO_TIMEOUT 10000
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#define IPQ4019_MDIO_SLEEP 10
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@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
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void __iomem *membase;
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void __iomem *eth_ldo_rdy;
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struct clk *mdio_clk;
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+ unsigned int mdc_rate;
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};
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static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
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@@ -179,6 +191,38 @@ static int ipq4019_mdio_write(struct mii
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return 0;
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}
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+static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
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+{
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+ unsigned long ahb_rate;
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+ int div;
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+ u32 val;
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+
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+ /* If we don't have a clock for AHB use the fixed value */
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+ ahb_rate = IPQ_MDIO_CLK_RATE;
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+ if (priv->mdio_clk)
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+ ahb_rate = clk_get_rate(priv->mdio_clk);
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+
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+ /* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
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+ * While supported, internal documentation doesn't
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+ * assure correct functionality of the MDIO bus
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+ * with divider of 1, 2 or 4.
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+ */
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+ for (div = 8; div <= 256; div *= 2) {
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+ /* The requested rate is supported by the div */
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+ if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
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+ val = readl(priv->membase + MDIO_MODE_REG);
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+ val &= ~MDIO_MODE_DIV_MASK;
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+ val |= MDIO_MODE_DIV(div);
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+ writel(val, priv->membase + MDIO_MODE_REG);
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+
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+ return 0;
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+ }
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+ }
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+
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+ /* The requested rate is not supported */
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+ return -EINVAL;
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+}
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+
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static int ipq_mdio_reset(struct mii_bus *bus)
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{
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struct ipq4019_mdio_data *priv = bus->priv;
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@@ -201,10 +245,58 @@ static int ipq_mdio_reset(struct mii_bus
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return ret;
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ret = clk_prepare_enable(priv->mdio_clk);
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- if (ret == 0)
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- mdelay(10);
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+ if (ret)
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+ return ret;
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+
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+ mdelay(10);
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- return ret;
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+ /* Restore MDC rate */
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+ return ipq4019_mdio_set_div(priv);
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+}
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+
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+static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
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+ struct ipq4019_mdio_data *priv)
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+{
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+ unsigned long ahb_rate;
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+ int div;
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+ u32 val;
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+
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+ /* MDC rate defined in DT, we don't have to decide a default value */
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+ if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
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+ &priv->mdc_rate))
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+ return;
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+
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+ /* If we don't have a clock for AHB use the fixed value */
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+ ahb_rate = IPQ_MDIO_CLK_RATE;
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+ if (priv->mdio_clk)
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+ ahb_rate = clk_get_rate(priv->mdio_clk);
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+
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+ /* Check what is the current div set */
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+ val = readl(priv->membase + MDIO_MODE_REG);
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+ div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
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+
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+ /* div is not set to the default value of /256
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+ * Probably someone changed that (bootloader, other drivers)
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+ * Keep this and don't overwrite it.
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+ */
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+ if (div != MDIO_MODE_DIV_256) {
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+ priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
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+ return;
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+ }
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+
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+ /* If div is /256 assume nobody have set this value and
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+ * try to find one MDC rate that is close the 802.3 spec of
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+ * 2.5MHz
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+ */
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+ for (div = 256; div >= 8; div /= 2) {
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+ /* Stop as soon as we found a divider that
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+ * reached the closest value to 2.5MHz
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+ */
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+ if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
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+ break;
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+
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+ priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
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+ }
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}
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static int ipq4019_mdio_probe(struct platform_device *pdev)
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@@ -228,6 +320,11 @@ static int ipq4019_mdio_probe(struct pla
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if (IS_ERR(priv->mdio_clk))
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return PTR_ERR(priv->mdio_clk);
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+ ipq4019_mdio_select_mdc_rate(pdev, priv);
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+ ret = ipq4019_mdio_set_div(priv);
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+ if (ret)
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+ return ret;
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+
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/* The platform resource is provided on the chipset IPQ5018 */
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/* This resource is optional */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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